X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPlatformPkg%2FInclude%2FDrivers%2FPL061Gpio.h;h=38458f484476360f2ad31644f493e53f342d9289;hp=4daabff768a874c3bcf9980c49fbd22398725e0f;hb=0db25ccc6cf1d05dc6b8fd9b07d033b40c387c88;hpb=5a62a8b7f19019e7aa8d26d30ed7b7a22fc2a6d0;ds=sidebyside

diff --git a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
index 4daabff768..38458f4844 100644
--- a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
+++ b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -16,37 +16,35 @@
 #ifndef __PL061_GPIO_H__
 #define __PL061_GPIO_H__
 
-#include <Base.h>
 #include <Protocol/EmbeddedGpio.h>
-#include <ArmPlatform.h>
-
-// SP805 Watchdog Registers
-#define PL061_GPIO_DATA_REG             (PL061_GPIO_BASE + 0x000)
-#define PL061_GPIO_DIR_REG              (PL061_GPIO_BASE + 0x400)
-#define PL061_GPIO_IS_REG               (PL061_GPIO_BASE + 0x404)
-#define PL061_GPIO_IBE_REG              (PL061_GPIO_BASE + 0x408)
-#define PL061_GPIO_IEV_REG              (PL061_GPIO_BASE + 0x40C)
-#define PL061_GPIO_IE_REG               (PL061_GPIO_BASE + 0x410)
-#define PL061_GPIO_RIS_REG              (PL061_GPIO_BASE + 0x414)
-#define PL061_GPIO_MIS_REG              (PL061_GPIO_BASE + 0x410)
-#define PL061_GPIO_IC_REG               (PL061_GPIO_BASE + 0x41C)
-#define PL061_GPIO_AFSEL_REG            (PL061_GPIO_BASE + 0x420)
-
-#define PL061_GPIO_PERIPH_ID0           (PL061_GPIO_BASE + 0xFE0)
-#define PL061_GPIO_PERIPH_ID1           (PL061_GPIO_BASE + 0xFE4)
-#define PL061_GPIO_PERIPH_ID2           (PL061_GPIO_BASE + 0xFE8)
-#define PL061_GPIO_PERIPH_ID3           (PL061_GPIO_BASE + 0xFEC)
-
-#define PL061_GPIO_PCELL_ID0            (PL061_GPIO_BASE + 0xFF0)
-#define PL061_GPIO_PCELL_ID1            (PL061_GPIO_BASE + 0xFF4)
-#define PL061_GPIO_PCELL_ID2            (PL061_GPIO_BASE + 0xFF8)
-#define PL061_GPIO_PCELL_ID3            (PL061_GPIO_BASE + 0xFFC)
+
+// PL061 GPIO Registers
+#define PL061_GPIO_DATA_REG             ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)
+#define PL061_GPIO_DIR_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)
+#define PL061_GPIO_IS_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)
+#define PL061_GPIO_IBE_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x408)
+#define PL061_GPIO_IEV_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x40C)
+#define PL061_GPIO_IE_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)
+#define PL061_GPIO_RIS_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x414)
+#define PL061_GPIO_MIS_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)
+#define PL061_GPIO_IC_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x41C)
+#define PL061_GPIO_AFSEL_REG            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x420)
+
+#define PL061_GPIO_PERIPH_ID0           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE0)
+#define PL061_GPIO_PERIPH_ID1           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE4)
+#define PL061_GPIO_PERIPH_ID2           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE8)
+#define PL061_GPIO_PERIPH_ID3           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFEC)
+
+#define PL061_GPIO_PCELL_ID0            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF0)
+#define PL061_GPIO_PCELL_ID1            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF4)
+#define PL061_GPIO_PCELL_ID2            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF8)
+#define PL061_GPIO_PCELL_ID3            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFFC)
 
 
 // GPIO pins are numbered 0..7
 #define LAST_GPIO_PIN                   7
 
-// All bits low except one bit high, native bit lenght
+// All bits low except one bit high, native bit length
 #define GPIO_PIN_MASK(Pin)              (1UL << ((UINTN)(Pin)))
 // All bits low except one bit high, restricted to 8 bits (i.e. ensures zeros above 8bits)
 #define GPIO_PIN_MASK_HIGH_8BIT(Pin)    (GPIO_PIN_MASK(Pin) && 0xFF)