X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPlatformPkg%2FPrePeiCore%2FMainMPCore.c;h=25a11cf1bdfb6142e65dd0cd018d98346eb63ca3;hp=a369c6e49cb1299c6e7d5ecb1302f44ca31a2313;hb=77de7e5372fc188811acfc3222b3fd967b54de3f;hpb=55a0d64b883bf8cc4db2a7890e29528ec57a2884 diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index a369c6e49c..25a11cf1bd 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -18,8 +18,6 @@ #include "PrePeiCore.h" -extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; - /* * This is the main function for secondary cores. They loop around until a non Null value is written to * SYS_FLAGS register.The SYS_FLAGS register is platform specific. @@ -32,7 +30,7 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; VOID EFIAPI SecondaryMain ( - IN UINTN CoreId + IN UINTN MpId ) { // Function pointer to Secondary Core entry point @@ -45,7 +43,7 @@ SecondaryMain ( while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { ArmCallWFI(); // Acknowledge the interrupt and send End of Interrupt signal. - ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); + ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID); } secondary_start = (VOID (*)())secondary_entry_addr; @@ -64,6 +62,12 @@ PrimaryMain ( ) { EFI_SEC_PEI_HAND_OFF SecCoreData; + UINTN PpiListSize; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + UINTN TemporaryRamBase; + UINTN TemporaryRamSize; + + CreatePpiList (&PpiListSize, &PpiList); // Enable the GIC Distributor ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase)); @@ -74,21 +78,27 @@ PrimaryMain ( ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); } + // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at + // the base of the primary core stack + PpiListSize = ALIGN_VALUE(PpiListSize, 0x4); + TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize; + TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize; + // // Bind this information into the SEC hand-off state // Note: this must be in sync with the stuff in the asm file // Note also: HOBs (pei temp ram) MUST be above stack // SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); - SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) - SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); - SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize); + SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack) + SecCoreData.TemporaryRamSize = TemporaryRamSize; + SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase; SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; - SecCoreData.StackBase = SecCoreData.TemporaryRamBase; - SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; + SecCoreData.StackBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize/2)); + SecCoreData.StackSize = SecCoreData.TemporaryRamSize / 2; // Jump to PEI core entry point - (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); + (PeiCoreEntryPoint)(&SecCoreData, PpiList); }