X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ArmPlatformPkg%2FPrePeiCore%2FMainUniCore.c;h=134a46942742775c1f68262a5cc7fbe1f77ae54f;hp=cf7d029bf65626c31f0f8412bfd07bfae83df823;hb=f33d5d68abc02727dc828c1079e72ab65e1d63af;hpb=1d5d0ae92d95410f20bc6daab7a47e129fb2547a

diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
index cf7d029bf6..134a469427 100644
--- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -12,42 +12,52 @@
 *
 **/
 
-#include <PiPei.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-#include <Chipset/ArmV7.h>
-
-extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
+#include "PrePeiCore.h"
 
 VOID
 EFIAPI
-secondary_main(IN UINTN CoreId)
+SecondaryMain (
+  IN UINTN MpId
+  )
 {
-	ASSERT(FALSE);
+  ASSERT(FALSE);
 }
 
-VOID primary_main (
+VOID
+EFIAPI
+PrimaryMain (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
   )
 {
-	EFI_SEC_PEI_HAND_OFF        SecCoreData;
+  EFI_SEC_PEI_HAND_OFF        SecCoreData;
+  UINTN                       PpiListSize;
+  EFI_PEI_PPI_DESCRIPTOR      *PpiList;
+  UINTN                       TemporaryRamBase;
+  UINTN                       TemporaryRamSize;
+
+  CreatePpiList (&PpiListSize, &PpiList);
 
+  // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
+  // the base of the primary core stack
+  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
+  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
+  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
 
-	//
-	// Bind this information into the SEC hand-off state
-	// Note: this must be in sync with the stuff in the asm file
-	// Note also:  HOBs (pei temp ram) MUST be above stack
-	//
-	SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
-	SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdEmbeddedFdBaseAddress);
-	SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdEmbeddedFdSize);
-	SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
-	SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
-	SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
-	SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;
-	SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;
-	SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
+  //
+  // Bind this information into the SEC hand-off state
+  // Note: this must be in sync with the stuff in the asm file
+  // Note also:  HOBs (pei temp ram) MUST be above stack
+  //
+  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);
+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
+  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
+  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
+  SecCoreData.TemporaryRamSize       = TemporaryRamSize;
+  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;
+  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
+  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
+  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
 
-	// jump to pei core entry point
-	(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
+  // Jump to PEI core entry point
+  (PeiCoreEntryPoint)(&SecCoreData, PpiList);
 }