X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=IntelFrameworkModulePkg%2FBus%2FPci%2FPciBusDxe%2FPciCommand.c;h=39f5271e9bc142c172692b2886567475d87e2485;hp=ab9d3a0025e6012c5c265acee6d10eae600694b1;hb=9eb130ff8cd00411d5b84a7950bf03fa93ed267c;hpb=7bfed576b0f351ac62c280f0f040060d14788dc3

diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
index ab9d3a0025..39f5271e9b 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciCommand.c
@@ -43,13 +43,13 @@ PciOperateRegister (
   PciIo       = &PciIoDevice->PciIo;
 
   if (Operation != EFI_SET_REGISTER) {
-    Status = PciIoRead (
-               PciIo,
-               EfiPciIoWidthUint16,
-               Offset,
-               1,
-               &OldCommand
-               );
+    Status = PciIo->Pci.Read (
+                          PciIo,
+                          EfiPciIoWidthUint16,
+                          Offset,
+                          1,
+                          &OldCommand
+                          );
 
     if (Operation == EFI_GET_REGISTER) {
       *PtrCommand = OldCommand;
@@ -65,13 +65,13 @@ PciOperateRegister (
     OldCommand = Command;
   }
 
-  return PciIoWrite (
-           PciIo,
-           EfiPciIoWidthUint16,
-           Offset,
-           1,
-           &OldCommand
-           );
+  return PciIo->Pci.Write (
+                      PciIo,
+                      EfiPciIoWidthUint16,
+                      Offset,
+                      1,
+                      &OldCommand
+                      );
 }
 
 /**
@@ -134,33 +134,33 @@ LocateCapabilityRegBlock (
     CapabilityPtr = 0;
     if (IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
 
-      PciIoRead (
-        &PciIoDevice->PciIo,
-        EfiPciIoWidthUint8,
-        EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
-        1,
-        &CapabilityPtr
-        );
+      PciIoDevice->PciIo.Pci.Read (
+                               &PciIoDevice->PciIo,
+                               EfiPciIoWidthUint8,
+                               EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR,
+                               1,
+                               &CapabilityPtr
+                               );
     } else {
 
-      PciIoRead (
-        &PciIoDevice->PciIo,
-        EfiPciIoWidthUint8,
-        PCI_CAPBILITY_POINTER_OFFSET,
-        1,
-        &CapabilityPtr
-        );
+      PciIoDevice->PciIo.Pci.Read (
+                               &PciIoDevice->PciIo,
+                               EfiPciIoWidthUint8,
+                               PCI_CAPBILITY_POINTER_OFFSET,
+                               1,
+                               &CapabilityPtr
+                               );
     }
   }
 
   while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
-    PciIoRead (
-      &PciIoDevice->PciIo,
-      EfiPciIoWidthUint16,
-      CapabilityPtr,
-      1,
-      &CapabilityEntry
-      );
+    PciIoDevice->PciIo.Pci.Read (
+                             &PciIoDevice->PciIo,
+                             EfiPciIoWidthUint16,
+                             CapabilityPtr,
+                             1,
+                             &CapabilityEntry
+                             );
 
     CapabilityID = (UINT8) CapabilityEntry;