X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=IntelFsp2Pkg%2FFspSecCore%2FIa32%2FFspApiEntryM.nasm;h=f14c18c7b92cdb9c05e906311ed510343bc7af72;hp=b56427670bf5df73318c4c9d91391c123a28913d;hb=9672cd30563b22331bb2491377b77b57b71c52e4;hpb=c69071bd7e21c24cfe9f4b49a0464acfb8b301d4 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index b56427670b..f14c18c7b9 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -1,14 +1,8 @@ ;; @file ; Provide FSP API entry points. ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
-; This program and the accompanying materials -; are licensed and made available under the terms and conditions of the BSD License -; which accompanies this distribution. The full text of the license may be found at -; http://opensource.org/licenses/bsd-license.php. -; -; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent ;; SECTION .text @@ -19,6 +13,7 @@ extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) struc FSPM_UPD_COMMON ; FSP_UPD_HEADER { @@ -116,10 +111,10 @@ ASM_PFX(FspApiCommonContinue): sidt [esp] - ; Get Stackbase and StackSize from FSPM_UPD Param - mov edx, [esp + API_PARAM1_OFFSET] + ; Get Stackbase and StackSize from FSPM_UPD Param + mov edx, [esp + API_PARAM1_OFFSET] cmp edx, 0 - jnz FspStackSetup + jnz FspStackSetup ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null push eax @@ -127,16 +122,56 @@ ASM_PFX(FspApiCommonContinue): mov edx, [eax + FSP_HEADER_IMGBASE_OFFSET] add edx, [eax + FSP_HEADER_CFGREG_OFFSET] pop eax - - FspStackSetup: + +FspStackSetup: + ; + ; StackBase = temp memory base, StackSize = temp memory size + ; mov edi, [edx + FSPM_UPD_COMMON.StackBase] mov ecx, [edx + FSPM_UPD_COMMON.StackSize] + + ; + ; Keep using bootloader stack if heap size % is 0 + ; + mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))] + cmp bl, 0 + jz SkipStackSwitch + + ; + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't equal 0 + ; add edi, ecx ; - ; Setup new FSP stack + ; Switch to new FSP stack + ; + xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size + +SkipStackSwitch: + ; + ; If heap size % is 0: + ; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loader stack pointer) + ; ECX is FSPM_UPD_COMMON.StackSize + ; ESP is boot loader stack pointer (no stack switch) + ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.StackBase later) ; - xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size - mov ebx, esp ; Put Stack base + Stack size in ebx + ; If heap size % is not 0 + ; EDI is boot loader stack pointer + ; ECX is FSPM_UPD_COMMON.StackSize + ; ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackSize) + ; BL is NOT 0 to indicate stack has switched + ; + cmp bl, 0 + jnz StackHasBeenSwitched + + mov ebx, edi ; Put FSPM_UPD_COMMON.StackBase to ebx as temp memory base + mov edi, esp ; Put boot loader stack pointer to edi + jmp StackSetupDone + +StackHasBeenSwitched: + mov ebx, esp ; Put Stack base + Stack size in ebx + sub ebx, ecx ; Stack base + Stack size - Stack size as temp memory base + +StackSetupDone: ; ; Pass the API Idx to SecStartup @@ -170,7 +205,6 @@ ASM_PFX(FspApiCommonContinue): ; ; Pass stack base and size into the PEI Core ; - sub ebx, ecx ; Stack base + Stack size - Stack size push ebx push ecx