X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=IntelSiliconPkg%2FInclude%2FIndustryStandard%2FIgdOpRegion.h;h=4d5637c6ede4c55b56a627744013ec908e11f252;hp=9982c9c9befed2ee985b12c3ed4c9aeb618d777f;hb=98e059ba16549f436e3d9e04112e9b1659da3eed;hpb=5c66efd0ed8c994a13228096bf2e281c0b980b8d

diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index 9982c9c9be..4d5637c6ed 100644
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -2,14 +2,7 @@
   IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
   Specification.
 
-  https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
-
-  There are some mismatch between the specification and the implementation.
-  The definition follows the latest implementation.
-  1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]
-  2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]
-  3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]
-  4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB
+  https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
@@ -24,6 +17,13 @@
 #ifndef _IGD_OPREGION_H_
 #define _IGD_OPREGION_H_
 
+#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"
+#define IGD_OPREGION_HEADER_MBOX1 BIT0
+#define IGD_OPREGION_HEADER_MBOX2 BIT1
+#define IGD_OPREGION_HEADER_MBOX3 BIT2
+#define IGD_OPREGION_HEADER_MBOX4 BIT3
+#define IGD_OPREGION_HEADER_MBOX5 BIT4
+
 /**
   OpRegion structures:
   Sub-structures define the different parts of the OpRegion followed by the
@@ -36,8 +36,9 @@
 **/
 #pragma pack(1)
 ///
-/// OpRegion header (mailbox 0) structure. The OpRegion Header is used to
+/// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to
 /// identify a block of memory as the graphics driver OpRegion.
+/// Offset 0x0, Size 0x100
 ///
 typedef struct {
   CHAR8  SIGN[0x10];    ///< Offset 0x00 OpRegion Signature
@@ -48,17 +49,20 @@ typedef struct {
   UINT8  GVER[0x10];    ///< Offset 0x48 Graphic Driver Build Version
   UINT32 MBOX;          ///< Offset 0x58 Supported Mailboxes
   UINT32 DMOD;          ///< Offset 0x5C Driver Model
-  UINT8  RSV1[0xA0];    ///< Offset 0x60 Reserved
-} INTEL_IGD_OPREGION_HEADER;
+  UINT32 PCON;          ///< Offset 0x60 Platform Configuration
+  CHAR16 DVER[0x10]     ///< Offset 0x64 GOP Version
+  UINT8  RM01[0x7C];    ///< Offset 0x84 Reserved Must be zero
+} IGD_OPREGION_HEADER;
 
 ///
-/// OpRegion mailbox 1 (public ACPI Methods)
+/// OpRegion Mailbox 1 - Public ACPI Methods
+/// Offset 0x100, Size 0x100
 ///
 typedef struct {
   UINT32 DRDY;          ///< Offset 0x100 Driver Readiness
   UINT32 CSTS;          ///< Offset 0x104 Status
   UINT32 CEVT;          ///< Offset 0x108 Current Event
-  UINT8  RSV2[0x14];    ///< Offset 0x10C Reserved
+  UINT8  RM11[0x14];    ///< Offset 0x10C Reserved Must be Zero
   UINT32 DIDL[8];       ///< Offset 0x120 Supported Display Devices ID List
   UINT32 CPDL[8];       ///< Offset 0x140 Currently Attached Display Devices List
   UINT32 CADL[8];       ///< Offset 0x160 Currently Active Display Devices List
@@ -72,21 +76,25 @@ typedef struct {
   UINT32 EVTS;          ///< Offset 0x1B8 Events supported by ASL
   UINT32 CNOT;          ///< Offset 0x1BC Current OS Notification
   UINT32 NRDY;          ///< Offset 0x1C0 Driver Status
-  UINT8  RSV3[0x3C];    ///< Offset 0x1C4 - 0x1FF Reserved
-} INTEL_IGD_OPREGION_MBOX1;
+  UINT8  DID2[0x1C];    ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)
+  UINT8  CPD2[0x1C];    ///< Offset 0x1E0 Extended Attached Display Devices List
+  UINT8  RM12[4];       ///< Offset 0x1FC - 0x1FF Reserved Must be zero
+} IGD_OPREGION_MBOX1;
 
 ///
-/// OpRegion mailbox 2 (Software SCI Interface).
+/// OpRegion Mailbox 2 - Software SCI Interface
+/// Offset 0x200, Size 0x100
 ///
 typedef struct {
   UINT32 SCIC;          ///< Offset 0x200 Software SCI Command / Status / Data
   UINT32 PARM;          ///< Offset 0x204 Software SCI Parameters
   UINT32 DSLP;          ///< Offset 0x208 Driver Sleep Time Out
-  UINT8  RSV4[0xF4];    ///< Offset 0x20C - 0x2FF Reserved
-} INTEL_IGD_OPREGION_MBOX2;
+  UINT8  RM21[0xF4];    ///< Offset 0x20C - 0x2FF Reserved Must be zero
+} IGD_OPREGION_MBOX2;
 
 ///
-/// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support).
+/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support
+/// Offset 0x300, Size 0x100
 ///
 typedef struct {
   UINT32 ARDY;          ///< Offset 0x300 Driver Readiness
@@ -102,26 +110,44 @@ typedef struct {
   UINT8  PLUT[0x4A];    ///< Offset 0x34C Panel Look Up Table & Identifier
   UINT32 PFMB;          ///< Offset 0x396 PWM Frequency and Minimum Brightness
   UINT32 CCDV;          ///< Offset 0x39A Color Correction Default Values
-  UINT8  RSV5[0x62];    ///< Offset 0x39E - 0x3FF  Reserved
-} INTEL_IGD_OPREGION_MBOX3;
+  UINT32 PCFT;          ///< Offset 0x39E Power Conservation Features
+  UINT32 SROT;          ///< Offset 0x3A2 Supported Rotation Angles
+  UINT32 IUER;          ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register
+  UINT64 FDSS;          ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
+  UINT32 FDSP;          ///< Offset 0x3B2 Size of DSS buffer
+  UINT32 STAT;          ///< Offset 0x3B6 State Indicator
+  UINT8  RM31[0x45];    ///< Offset 0x3BA - 0x3FF  Reserved Must be zero
+} IGD_OPREGION_MBOX3;
 
 ///
-/// OpRegion mailbox 4 (VBT).
+/// OpRegion Mailbox 4 - VBT Video BIOS Table
+/// Offset 0x400, Size 0x1800
 ///
 typedef struct {
   UINT8  RVBT[0x1800];  ///< Offset 0x400 - 0x1BFF Raw VBT Data
-} INTEL_IGD_OPREGION_VBT;
+} IGD_OPREGION_MBOX4;
+
+///
+/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync
+/// Offset 0x1C00, Size 0x400
+///
+typedef struct {
+  UINT32 PHED;          ///< Offset 0x1C00 Panel Header
+  UINT8  BDDC[0x100];   ///< Offset 0x1C04 Panel EDID (DDC data)
+  UINT8  RM51[0x2FC];   ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero
+} IGD_OPREGION_MBOX5;
 
 ///
 /// IGD OpRegion Structure
 ///
 typedef struct {
-  INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)
-  INTEL_IGD_OPREGION_MBOX1  MBox1;  ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)
-  INTEL_IGD_OPREGION_MBOX2  MBox2;  ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
-  INTEL_IGD_OPREGION_MBOX3  MBox3;  ///< Mailbox 3: BIOS to Driver Communication (Offset 0x300, Size 0x100)
-  INTEL_IGD_OPREGION_VBT    VBT;    ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1200)
-} IGD_IGD_OPREGION_STRUCTURE;
+  IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)
+  IGD_OPREGION_MBOX1  MBox1;  ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)
+  IGD_OPREGION_MBOX2  MBox2;  ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
+  IGD_OPREGION_MBOX3  MBox3;  ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
+  IGD_OPREGION_MBOX4  MBox4;  ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
+  IGD_OPREGION_MBOX5  MBox5;  ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)
+} IGD_OPREGION_STRUCTURE;
 #pragma pack()
 
 #endif