X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=IntelSiliconPkg%2FInclude%2FIndustryStandard%2FIgdOpRegion.h;h=4d5637c6ede4c55b56a627744013ec908e11f252;hp=a0ee79d85307025c392c53f3c4d3f37858cc0ed0;hb=98e059ba16549f436e3d9e04112e9b1659da3eed;hpb=9fb16e2143009c3158ab4be11adc3380bdab44ff diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h index a0ee79d853..4d5637c6ed 100644 --- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h +++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h @@ -2,14 +2,7 @@ IGD OpRegion definition from Intel Integrated Graphics Device OpRegion Specification. - https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf - - There are some mismatch between the specification and the implementation. - The definition follows the latest implementation. - 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0] - 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C] - 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62] - 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1C00] + https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf Copyright (c) 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials @@ -24,103 +17,137 @@ #ifndef _IGD_OPREGION_H_ #define _IGD_OPREGION_H_ +#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem" +#define IGD_OPREGION_HEADER_MBOX1 BIT0 +#define IGD_OPREGION_HEADER_MBOX2 BIT1 +#define IGD_OPREGION_HEADER_MBOX3 BIT2 +#define IGD_OPREGION_HEADER_MBOX4 BIT3 +#define IGD_OPREGION_HEADER_MBOX5 BIT4 + /** - OpRegion structures: - Sub-structures define the different parts of the OpRegion followed by the - main structure representing the entire OpRegion. + OpRegion structures: + Sub-structures define the different parts of the OpRegion followed by the + main structure representing the entire OpRegion. - Note: These structures are packed to 1 byte offsets because the exact - data location is requred by the supporting design specification due to - the fact that the data is used by ASL and Graphics driver code compiled - separatly. + @note: These structures are packed to 1 byte offsets because the exact + data location is required by the supporting design specification due to + the fact that the data is used by ASL and Graphics driver code compiled + separately. **/ #pragma pack(1) /// -/// OpRegion header (mailbox 0) structure and defines. +/// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to +/// identify a block of memory as the graphics driver OpRegion. +/// Offset 0x0, Size 0x100 +/// +typedef struct { + CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature + UINT32 SIZE; ///< Offset 0x10 OpRegion Size + UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version + UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version + UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version + UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version + UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes + UINT32 DMOD; ///< Offset 0x5C Driver Model + UINT32 PCON; ///< Offset 0x60 Platform Configuration + CHAR16 DVER[0x10] ///< Offset 0x64 GOP Version + UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero +} IGD_OPREGION_HEADER; + +/// +/// OpRegion Mailbox 1 - Public ACPI Methods +/// Offset 0x100, Size 0x100 /// typedef struct { - CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion Signature - UINT32 SIZE; ///< Offset 16 OpRegion Size - UINT32 OVER; ///< Offset 20 OpRegion Structure Version - UINT8 SVER[0x20]; ///< Offset 24 System BIOS Build Version - UINT8 VVER[0x10]; ///< Offset 56 Video BIOS Build Version - UINT8 GVER[0x10]; ///< Offset 72 Graphic Driver Build Version - UINT32 MBOX; ///< Offset 88 Supported Mailboxes - UINT32 DMOD; ///< Offset 92 Driver Model - UINT8 RSV1[0xA0]; ///< Offset 96 Reserved -} INTEL_IGD_OPREGION_HEADER; + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List + UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List + UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index + UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on Sx State Resume + UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL + UINT32 CNOT; ///< Offset 0x1BC Current OS Notification + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1; /// -/// OpRegion mailbox 1 (public ACPI Methods). +/// OpRegion Mailbox 2 - Software SCI Interface +/// Offset 0x200, Size 0x100 /// typedef struct { - UINT32 DRDY; ///< Offset 0 Driver Readiness - UINT32 CSTS; ///< Offset 4 Status - UINT32 CEVT; ///< Offset 8 Current Event - UINT8 RSV2[0x14]; ///< Offset 12 Reserved - UINT32 DIDL[8]; ///< Offset 32 Supported Display Devices ID List - UINT32 CPDL[8]; ///< Offset 64 Currently Attached Display Devices List - UINT32 CADL[8]; ///< Offset 96 Currently Active Display Devices List - UINT32 NADL[8]; ///< Offset 128 Next Active Devices List - UINT32 ASLP; ///< Offset 160 ASL Sleep Time Out - UINT32 TIDX; ///< Offset 164 Toggle Table Index - UINT32 CHPD; ///< Offset 168 Current Hotplug Enable Indicator - UINT32 CLID; ///< Offset 172 Current Lid State Indicator - UINT32 CDCK; ///< Offset 176 Current Docking State Indicator - UINT32 SXSW; ///< Offset 180 Display Switch Notification on Sx State Resume - UINT32 EVTS; ///< Offset 184 Events supported by ASL - UINT32 CNOT; ///< Offset 188 Current OS Notification - UINT32 NRDY; ///< Offset 192 Driver Status - UINT8 RSV3[0x3C]; ///< Offset 196 Reserved -} INTEL_IGD_OPREGION_MBOX1; + UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data + UINT32 PARM; ///< Offset 0x204 Software SCI Parameters + UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out + UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero +} IGD_OPREGION_MBOX2; /// -/// OpRegion mailbox 2 (Software SCI Interface). +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support +/// Offset 0x300, Size 0x100 /// typedef struct { - UINT32 SCIC; ///< Offset 0 Software SCI Command / Status / Data - UINT32 PARM; ///< Offset 4 Software SCI Parameters - UINT32 DSLP; ///< Offset 8 Driver Sleep Time Out - UINT8 RSV4[0xF4]; ///< Offset 12 Reserved -} INTEL_IGD_OPREGION_MBOX2; + UINT32 ARDY; ///< Offset 0x300 Driver Readiness + UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status + UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator + UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading + UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness + UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request + UINT32 CBLV; ///< Offset 0x318 Current Brightness Level + UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table + UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode + UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes + UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier + UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness + UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values + UINT32 PCFT; ///< Offset 0x39E Power Conservation Features + UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles + UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register + UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature + UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer + UINT32 STAT; ///< Offset 0x3B6 State Indicator + UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero +} IGD_OPREGION_MBOX3; /// -/// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support). +/// OpRegion Mailbox 4 - VBT Video BIOS Table +/// Offset 0x400, Size 0x1800 /// typedef struct { - UINT32 ARDY; ///< Offset 0 Driver Readiness - UINT32 ASLC; ///< Offset 4 ASLE Interrupt Command / Status - UINT32 TCHE; ///< Offset 8 Technology Enabled Indicator - UINT32 ALSI; ///< Offset 12 Current ALS Luminance Reading - UINT32 BCLP; ///< Offset 16 Requested Backlight Britness - UINT32 PFIT; ///< Offset 20 Panel Fitting State or Request - UINT32 CBLV; ///< Offset 24 Current Brightness Level - UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Levels Duty Cycle Mapping Table - UINT32 CPFM; ///< Offset 68 Current Panel Fitting Mode - UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes - UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table & Identifier - UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness - UINT32 CCDV; ///< Offset 154 Color Correction Default Values - UINT8 RSV5[0x62]; ///< Offset 158 Reserved -} INTEL_IGD_OPREGION_MBOX3; + UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data +} IGD_OPREGION_MBOX4; /// -/// OpRegion mailbox 4 (VBT). +/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync +/// Offset 0x1C00, Size 0x400 /// typedef struct { - UINT8 RVBT[0x1C00]; ///< Offset 0 Raw VBT Data -} INTEL_IGD_OPREGION_VBT; + UINT32 PHED; ///< Offset 0x1C00 Panel Header + UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data) + UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero +} IGD_OPREGION_MBOX5; /// /// IGD OpRegion Structure /// typedef struct { - INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header - INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods - INTEL_IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface - INTEL_IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS/Driver Communication - INTEL_IGD_OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data) -} IGD_IGD_OPREGION_STRUCTURE; + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE; #pragma pack() #endif