X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FBus%2FAta%2FAtaAtapiPassThru%2FAhciMode.c;h=4d01c1dd7fca2c70d97250e9bace7840135e4d09;hp=0bc54abbf7255512837cf0f71e30cd1f52fe50a4;hb=6052a15f4a4297b430cf03f2456e51f8d3bb4598;hpb=7538d53684792266c37e91f11a3ce2b7fb1e32d9
diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
index 0bc54abbf7..4d01c1dd7f 100644
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -1,14 +1,15 @@
/** @file
The file for AHCI mode of ATA host controller.
-
- Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ (C) Copyright 2015 Hewlett Packard Enterprise Development LP
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -33,7 +34,7 @@ AhciReadReg (
UINT32 Data;
ASSERT (PciIo != NULL);
-
+
Data = 0;
PciIo->Mem.Read (
@@ -95,7 +96,7 @@ AhciAndReg (
)
{
UINT32 Data;
-
+
ASSERT (PciIo != NULL);
Data = AhciReadReg (PciIo, Offset);
@@ -133,36 +134,45 @@ AhciOrReg (
}
/**
- Wait for memory set to the test value.
-
+ Wait for the value of the specified MMIO register set to the test value.
+
@param PciIo The PCI IO protocol instance.
- @param Offset The memory address to test.
+ @param Offset The MMIO address to test.
@param MaskValue The mask value of memory.
@param TestValue The test value of memory.
- @param Timeout The time out value for wait memory set.
+ @param Timeout The time out value for wait memory set, uses 100ns as a unit.
- @retval EFI_DEVICE_ERROR The memory is not set.
- @retval EFI_TIMEOUT The memory setting is time out.
- @retval EFI_SUCCESS The memory is correct set.
+ @retval EFI_TIMEOUT The MMIO setting is time out.
+ @retval EFI_SUCCESS The MMIO is correct set.
**/
EFI_STATUS
EFIAPI
-AhciWaitMemSet (
+AhciWaitMmioSet (
IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
+ IN UINTN Offset,
IN UINT32 MaskValue,
IN UINT32 TestValue,
IN UINT64 Timeout
)
{
- UINT32 Value;
- UINT32 Delay;
+ UINT32 Value;
+ UINT64 Delay;
+ BOOLEAN InfiniteWait;
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
+ if (Timeout == 0) {
+ InfiniteWait = TRUE;
+ } else {
+ InfiniteWait = FALSE;
+ }
+
+ Delay = DivU64x32 (Timeout, 1000) + 1;
do {
- Value = AhciReadReg (PciIo, Offset) & MaskValue;
+ //
+ // Access PCI MMIO space to see if the value is the tested one.
+ //
+ Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
if (Value == TestValue) {
return EFI_SUCCESS;
@@ -175,23 +185,80 @@ AhciWaitMemSet (
Delay--;
- } while (Delay > 0);
+ } while (InfiniteWait || (Delay > 0));
- if (Delay == 0) {
- return EFI_TIMEOUT;
+ return EFI_TIMEOUT;
+}
+
+/**
+ Wait for the value of the specified system memory set to the test value.
+
+ @param Address The system memory address to test.
+ @param MaskValue The mask value of memory.
+ @param TestValue The test value of memory.
+ @param Timeout The time out value for wait memory set, uses 100ns as a unit.
+
+ @retval EFI_TIMEOUT The system memory setting is time out.
+ @retval EFI_SUCCESS The system memory is correct set.
+
+**/
+EFI_STATUS
+EFIAPI
+AhciWaitMemSet (
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue,
+ IN UINT64 Timeout
+ )
+{
+ UINT32 Value;
+ UINT64 Delay;
+ BOOLEAN InfiniteWait;
+
+ if (Timeout == 0) {
+ InfiniteWait = TRUE;
+ } else {
+ InfiniteWait = FALSE;
}
- return EFI_DEVICE_ERROR;
+ Delay = DivU64x32 (Timeout, 1000) + 1;
+
+ do {
+ //
+ // Access sytem memory to see if the value is the tested one.
+ //
+ // The system memory pointed by Address will be updated by the
+ // SATA Host Controller, "volatile" is introduced to prevent
+ // compiler from optimizing the access to the memory address
+ // to only read once.
+ //
+ Value = *(volatile UINT32 *) (UINTN) Address;
+ Value &= MaskValue;
+
+ if (Value == TestValue) {
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Stall for 100 microseconds.
+ //
+ MicroSecondDelay (100);
+
+ Delay--;
+
+ } while (InfiniteWait || (Delay > 0));
+
+ return EFI_TIMEOUT;
}
/**
Check the memory status to the test value.
-
- @param[in] PciIo The PCI IO protocol instance.
- @param[in] Offset The memory address to test.
+
+ @param[in] Address The memory address to test.
@param[in] MaskValue The mask value of memory.
@param[in] TestValue The test value of memory.
- @param[in, out] RetryTimes The retry times value for waitting memory set.
+ @param[in, out] Task Optional. Pointer to the ATA_NONBLOCK_TASK used by
+ non-blocking mode. If NULL, then just try once.
@retval EFI_NOTREADY The memory is not set.
@retval EFI_TIMEOUT The memory setting retry times out.
@@ -201,24 +268,26 @@ AhciWaitMemSet (
EFI_STATUS
EFIAPI
AhciCheckMemSet (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT32 Offset,
+ IN UINTN Address,
IN UINT32 MaskValue,
IN UINT32 TestValue,
- IN OUT UINTN *RetryTimes
+ IN OUT ATA_NONBLOCK_TASK *Task
)
{
UINT32 Value;
- (*RetryTimes) --;
-
- Value = AhciReadReg (PciIo, Offset) & MaskValue;
+ if (Task != NULL) {
+ Task->RetryTimes--;
+ }
+
+ Value = *(volatile UINT32 *) Address;
+ Value &= MaskValue;
if (Value == TestValue) {
return EFI_SUCCESS;
}
- if ((*RetryTimes) == 0) {
+ if ((Task != NULL) && !Task->InfiniteWait && (Task->RetryTimes == 0)) {
return EFI_TIMEOUT;
} else {
return EFI_NOT_READY;
@@ -226,13 +295,13 @@ AhciCheckMemSet (
}
/**
- Check if the device is still on port. It also checks if the AHCI controller
+ Check if the device is still on port. It also checks if the AHCI controller
supports the address and data count will be transferred.
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
- @retval EFI_SUCCESS The device is attached to port and the transfer data is
+ @retval EFI_SUCCESS The device is attached to port and the transfer data is
supported by AHCI controller.
@retval EFI_UNSUPPORTED The transfer address and count is not supported by AHCI
controller.
@@ -265,17 +334,17 @@ AhciCheckDeviceStatus (
Clear the port interrupt and error status. It will also clear
HBA interrupt status.
-
+
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
-
-**/
+
+**/
VOID
EFIAPI
AhciClearPortStatus (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Port
- )
+ )
{
UINT32 Offset;
@@ -302,6 +371,7 @@ AhciClearPortStatus (
in the Status Register, the Error Register's value is also be dumped.
@param PciIo The PCI IO protocol instance.
+ @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
@@ -310,24 +380,42 @@ VOID
EFIAPI
AhciDumpPortStatus (
IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
IN UINT8 Port,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
)
{
- UINT32 Offset;
+ UINTN Offset;
UINT32 Data;
+ UINTN FisBaseAddr;
+ EFI_STATUS Status;
ASSERT (PciIo != NULL);
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
- Data = AhciReadReg (PciIo, Offset);
-
if (AtaStatusBlock != NULL) {
ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
- AtaStatusBlock->AtaStatus = (UINT8)Data;
- if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
- AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
+ FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);
+ if (!EFI_ERROR (Status)) {
+ //
+ // If D2H FIS is received, update StatusBlock with its content.
+ //
+ CopyMem (AtaStatusBlock, (UINT8 *)Offset, sizeof (EFI_ATA_STATUS_BLOCK));
+ } else {
+ //
+ // If D2H FIS is not received, only update Status & Error field through PxTFD
+ // as there is no other way to get the content of the Shadow Register Block.
+ //
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ Data = AhciReadReg (PciIo, (UINT32)Offset);
+
+ AtaStatusBlock->AtaStatus = (UINT8)Data;
+ if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
+ AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
+ }
}
}
}
@@ -335,10 +423,10 @@ AhciDumpPortStatus (
/**
Enable the FIS running for giving port.
-
+
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
- @param Timeout The timeout value of enabling FIS.
+ @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.
@retval EFI_DEVICE_ERROR The FIS enable setting fails.
@retval EFI_TIMEOUT The FIS enable setting is time out.
@@ -358,13 +446,7 @@ AhciEnableFisReceive (
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
- return AhciWaitMemSet (
- PciIo,
- Offset,
- EFI_AHCI_PORT_CMD_FR,
- EFI_AHCI_PORT_CMD_FR,
- Timeout
- );
+ return EFI_SUCCESS;
}
/**
@@ -372,7 +454,7 @@ AhciEnableFisReceive (
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
- @param Timeout The timeout value of disabling FIS.
+ @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.
@retval EFI_DEVICE_ERROR The FIS disable setting fails.
@retval EFI_TIMEOUT The FIS disable setting is time out.
@@ -386,7 +468,7 @@ AhciDisableFisReceive (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Port,
IN UINT64 Timeout
- )
+ )
{
UINT32 Offset;
UINT32 Data;
@@ -400,7 +482,7 @@ AhciDisableFisReceive (
if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
return EFI_UNSUPPORTED;
}
-
+
//
// Check if the Fis receive DMA engine for the port is running.
//
@@ -410,7 +492,7 @@ AhciDisableFisReceive (
AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
- return AhciWaitMemSet (
+ return AhciWaitMmioSet (
PciIo,
Offset,
EFI_AHCI_PORT_CMD_FR,
@@ -423,7 +505,7 @@ AhciDisableFisReceive (
/**
Build the command list, command table and prepare the fis receiver.
-
+
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
@@ -436,7 +518,7 @@ AhciDisableFisReceive (
@param DataPhysicalAddr The pointer to the data buffer pci bus master address.
@param DataLength The data count to be transferred.
-**/
+**/
VOID
EFIAPI
AhciBuildCommand (
@@ -450,12 +532,12 @@ AhciBuildCommand (
IN UINT8 AtapiCommandLength,
IN UINT8 CommandSlotNumber,
IN OUT VOID *DataPhysicalAddr,
- IN UINT64 DataLength
- )
+ IN UINT32 DataLength
+ )
{
UINT64 BaseAddr;
- UINT64 PrdtNumber;
- UINT64 PrdtIndex;
+ UINT32 PrdtNumber;
+ UINT32 PrdtIndex;
UINTN RemainedData;
UINTN MemAddr;
DATA_64 Data64;
@@ -463,8 +545,8 @@ AhciBuildCommand (
//
// Filling the PRDT
- //
- PrdtNumber = (DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1) / EFI_AHCI_MAX_DATA_PER_PRDT;
+ //
+ PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);
//
// According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
@@ -476,13 +558,13 @@ AhciBuildCommand (
Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
BaseAddr = Data64.Uint64;
-
+
ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
-
+
ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
CommandFis->AhciCFisPmNum = PortMultiplier;
-
+
CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
@@ -495,17 +577,16 @@ AhciBuildCommand (
CommandList->AhciCmdA = 1;
CommandList->AhciCmdP = 1;
- CommandList->AhciCmdC = (DataLength == 0) ? 1 : 0;
AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
} else {
AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
}
-
+
RemainedData = (UINTN) DataLength;
MemAddr = (UINTN) DataPhysicalAddr;
- CommandList->AhciCmdPrdtl = (UINT32)PrdtNumber;
-
+ CommandList->AhciCmdPrdtl = PrdtNumber;
+
for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
@@ -531,7 +612,7 @@ AhciBuildCommand (
(VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
CommandList,
sizeof (EFI_AHCI_COMMAND_LIST)
- );
+ );
Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;
@@ -542,7 +623,7 @@ AhciBuildCommand (
/**
Buid a command FIS.
-
+
@param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.
@param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.
@@ -560,7 +641,7 @@ AhciBuildCommandFis (
//
// Indicator it's a command
//
- CmdFis->AhciCFisCmdInd = 0x1;
+ CmdFis->AhciCFisCmdInd = 0x1;
CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
@@ -583,7 +664,7 @@ AhciBuildCommandFis (
/**
Start a PIO data transfer on specific port.
-
+
@param[in] PciIo The PCI IO protocol instance.
@param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param[in] Port The number of port.
@@ -596,7 +677,7 @@ AhciBuildCommandFis (
@param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
@param[in, out] MemoryAddr The pointer to the data buffer.
@param[in] DataCount The data count to be transferred.
- @param[in] Timeout The timeout value of non data transfer.
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
used by non-blocking mode.
@@ -614,8 +695,8 @@ AhciPioTransfer (
IN UINT8 Port,
IN UINT8 PortMultiplier,
IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
- IN UINT8 AtapiCommandLength,
- IN BOOLEAN Read,
+ IN UINT8 AtapiCommandLength,
+ IN BOOLEAN Read,
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
IN OUT VOID *MemoryAddr,
@@ -626,15 +707,25 @@ AhciPioTransfer (
{
EFI_STATUS Status;
UINTN FisBaseAddr;
- UINT32 Offset;
- UINT32 Value;
+ UINTN Offset;
EFI_PHYSICAL_ADDRESS PhyAddr;
VOID *Map;
UINTN MapLength;
EFI_PCI_IO_PROTOCOL_OPERATION Flag;
- UINT32 Delay;
+ UINT64 Delay;
EFI_AHCI_COMMAND_FIS CFis;
EFI_AHCI_COMMAND_LIST CmdList;
+ UINT32 PortTfd;
+ UINT32 PrdCount;
+ BOOLEAN InfiniteWait;
+ BOOLEAN PioFisReceived;
+ BOOLEAN D2hFisReceived;
+
+ if (Timeout == 0) {
+ InfiniteWait = TRUE;
+ } else {
+ InfiniteWait = FALSE;
+ }
if (Read) {
Flag = EfiPciIoOperationBusMasterWrite;
@@ -658,7 +749,7 @@ AhciPioTransfer (
if (EFI_ERROR (Status) || (DataCount != MapLength)) {
return EFI_BAD_BUFFER_SIZE;
}
-
+
//
// Package read needed
//
@@ -681,8 +772,8 @@ AhciPioTransfer (
0,
(VOID *)(UINTN)PhyAddr,
DataCount
- );
-
+ );
+
Status = AhciStartCommand (
PciIo,
Port,
@@ -697,56 +788,83 @@ AhciPioTransfer (
// Check the status and wait the driver sending data
//
FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
- //
- // Wait device sends the PIO setup fis before data transfer
- //
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
- do {
- Value = *(volatile UINT32 *) (FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET);
-
- if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_PIO_SETUP) {
- break;
- }
+ if (Read && (AtapiCommand == 0)) {
//
- // Stall for 100 microseconds.
+ // Wait device sends the PIO setup fis before data transfer
//
- MicroSecondDelay(100);
+ Status = EFI_TIMEOUT;
+ Delay = DivU64x32 (Timeout, 1000) + 1;
+ do {
+ PioFisReceived = FALSE;
+ D2hFisReceived = FALSE;
+ Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, NULL);
+ if (!EFI_ERROR (Status)) {
+ PioFisReceived = TRUE;
+ }
+ //
+ // According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
+ // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
+ // after the transaction is finished successfully.
+ // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.
+ // By this way, we can know if there is a real error happened.
+ //
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);
+ if (!EFI_ERROR (Status)) {
+ D2hFisReceived = TRUE;
+ }
- Delay--;
- } while (Delay > 0);
+ if (PioFisReceived || D2hFisReceived) {
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
+ //
+ // PxTFD will be updated if there is a D2H or SetupFIS received.
+ //
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
- if (Delay == 0) {
- Status = EFI_TIMEOUT;
- goto Exit;
- }
+ PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
+ if (PrdCount == DataCount) {
+ Status = EFI_SUCCESS;
+ break;
+ }
+ }
- //
- // Wait for command compelte
- //
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
- Status = AhciWaitMemSet (
- PciIo,
- Offset,
- 0xFFFFFFFF,
- 0,
- Timeout
- );
+ //
+ // Stall for 100 microseconds.
+ //
+ MicroSecondDelay(100);
- if (EFI_ERROR (Status)) {
- goto Exit;
- }
+ Delay--;
+ if (Delay == 0) {
+ Status = EFI_TIMEOUT;
+ }
+ } while (InfiniteWait || (Delay > 0));
+ } else {
+ //
+ // Wait for D2H Fis is received
+ //
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ Status = AhciWaitMemSet (
+ Offset,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ Timeout
+ );
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
- Status = AhciWaitMemSet (
- PciIo,
- Offset,
- EFI_AHCI_PORT_IS_PSS,
- EFI_AHCI_PORT_IS_PSS,
- Timeout
- );
- if (EFI_ERROR (Status)) {
- goto Exit;
+ if (EFI_ERROR (Status)) {
+ goto Exit;
+ }
+
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ }
}
Exit:
@@ -755,7 +873,7 @@ Exit:
Port,
Timeout
);
-
+
AhciDisableFisReceive (
PciIo,
Port,
@@ -767,7 +885,7 @@ Exit:
Map
);
- AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
+ AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
return Status;
}
@@ -787,7 +905,7 @@ Exit:
@param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
@param[in, out] MemoryAddr The pointer to the data buffer.
@param[in] DataCount The data count to be transferred.
- @param[in] Timeout The timeout value of non data transfer.
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
used by non-blocking mode.
@@ -806,26 +924,28 @@ AhciDmaTransfer (
IN UINT8 PortMultiplier,
IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
IN UINT8 AtapiCommandLength,
- IN BOOLEAN Read,
+ IN BOOLEAN Read,
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
IN OUT VOID *MemoryAddr,
- IN UINTN DataCount,
+ IN UINT32 DataCount,
IN UINT64 Timeout,
IN ATA_NONBLOCK_TASK *Task
)
{
EFI_STATUS Status;
- UINT32 Offset;
+ UINTN Offset;
EFI_PHYSICAL_ADDRESS PhyAddr;
VOID *Map;
UINTN MapLength;
EFI_PCI_IO_PROTOCOL_OPERATION Flag;
EFI_AHCI_COMMAND_FIS CFis;
EFI_AHCI_COMMAND_LIST CmdList;
+ UINTN FisBaseAddr;
+ UINT32 PortTfd;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_TPL OldTpl;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_TPL OldTpl;
Map = NULL;
PciIo = Instance->PciIo;
@@ -839,15 +959,15 @@ AhciDmaTransfer (
// BlockIO tasks.
// Delay 100us to simulate the blocking time out checking.
//
+ OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
- OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
AsyncNonBlockingTransferRoutine (NULL, Instance);
- gBS->RestoreTPL (OldTpl);
//
// Stall for 100us.
//
MicroSecondDelay (100);
}
+ gBS->RestoreTPL (OldTpl);
if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {
//
@@ -855,7 +975,6 @@ AhciDmaTransfer (
//
if (Task != NULL) {
Task->IsStart = TRUE;
- Task->RetryTimes = (UINT32) (DivU64x32(Timeout, 1000) + 1);
}
if (Read) {
Flag = EfiPciIoOperationBusMasterWrite;
@@ -916,45 +1035,28 @@ AhciDmaTransfer (
if (EFI_ERROR (Status)) {
goto Exit;
}
-
- //
- // Wait device PRD processed
- //
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
- Status = AhciWaitMemSet (
- PciIo,
- Offset,
- EFI_AHCI_PORT_IS_DPS,
- EFI_AHCI_PORT_IS_DPS,
- Timeout
- );
-
- if (EFI_ERROR (Status)) {
- goto Exit;
- }
}
//
// Wait for command compelte
//
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
+ FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
if (Task != NULL) {
//
// For Non-blocking
//
Status = AhciCheckMemSet (
- PciIo,
Offset,
- 0xFFFFFFFF,
- 0,
- (UINTN *) (&Task->RetryTimes)
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ Task
);
} else {
Status = AhciWaitMemSet (
- PciIo,
Offset,
- 0xFFFFFFFF,
- 0,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
Timeout
);
}
@@ -963,52 +1065,31 @@ AhciDmaTransfer (
goto Exit;
}
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
-
- if (Task != NULL) {
- //
- // For Non-blocking
- //
- Status = AhciCheckMemSet (
- PciIo,
- Offset,
- EFI_AHCI_PORT_IS_DHRS,
- EFI_AHCI_PORT_IS_DHRS,
- (UINTN *) (&Task->RetryTimes)
- );
- } else {
- Status = AhciWaitMemSet (
- PciIo,
- Offset,
- EFI_AHCI_PORT_IS_DHRS,
- EFI_AHCI_PORT_IS_DHRS,
- Timeout
- );
- }
-
- if (EFI_ERROR (Status)) {
- goto Exit;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
}
Exit:
//
// For Blocking mode, the command should be stopped, the Fis should be disabled
// and the PciIo should be unmapped.
- // For non-blocking mode, only when a error is happened (if the return status is
- // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
+ // For non-blocking mode, only when a error is happened (if the return status is
+ // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
// context cleanup, then set the packet's Asb status.
//
if (Task == NULL ||
((Task != NULL) && (Status != EFI_NOT_READY))
) {
AhciStopCommand (
- PciIo,
+ PciIo,
Port,
Timeout
);
AhciDisableFisReceive (
- PciIo,
+ PciIo,
Port,
Timeout
);
@@ -1023,13 +1104,13 @@ Exit:
}
}
- AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
+ AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
return Status;
}
/**
Start a non data transfer on specific port.
-
+
@param[in] PciIo The PCI IO protocol instance.
@param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param[in] Port The number of port.
@@ -1039,7 +1120,7 @@ Exit:
@param[in] AtapiCommandLength The length of the atapi command.
@param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
@param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
- @param[in] Timeout The timeout value of non data transfer.
+ @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
@param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
used by non-blocking mode.
@@ -1048,7 +1129,7 @@ Exit:
@retval EFI_UNSUPPORTED The device is not ready for transfer.
@retval EFI_SUCCESS The non data transfer executes successfully.
-**/
+**/
EFI_STATUS
EFIAPI
AhciNonDataTransfer (
@@ -1066,10 +1147,8 @@ AhciNonDataTransfer (
{
EFI_STATUS Status;
UINTN FisBaseAddr;
- UINT32 Offset;
- UINT32 Value;
- UINT32 Delay;
-
+ UINTN Offset;
+ UINT32 PortTfd;
EFI_AHCI_COMMAND_FIS CFis;
EFI_AHCI_COMMAND_LIST CmdList;
@@ -1110,39 +1189,23 @@ AhciNonDataTransfer (
// Wait device sends the Response Fis
//
FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
- //
- // Wait device sends the PIO setup fis before data transfer
- //
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
- do {
- Value = *(volatile UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
+ Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
+ Status = AhciWaitMemSet (
+ Offset,
+ EFI_AHCI_FIS_TYPE_MASK,
+ EFI_AHCI_FIS_REGISTER_D2H,
+ Timeout
+ );
- if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
- break;
- }
-
- //
- // Stall for 100 microseconds.
- //
- MicroSecondDelay(100);
-
- Delay --;
- } while (Delay > 0);
-
- if (Delay == 0) {
- Status = EFI_TIMEOUT;
+ if (EFI_ERROR (Status)) {
goto Exit;
}
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
-
- Status = AhciWaitMemSet (
- PciIo,
- Offset,
- 0xFFFFFFFF,
- 0,
- Timeout
- );
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
+ if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ }
Exit:
AhciStopCommand (
@@ -1157,18 +1220,18 @@ Exit:
Timeout
);
- AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
+ AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
return Status;
}
/**
Stop command running for giving port
-
+
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
- @param Timeout The timeout value of stop.
-
+ @param Timeout The timeout value of stop, uses 100ns as a unit.
+
@retval EFI_DEVICE_ERROR The command stop unsuccessfully.
@retval EFI_TIMEOUT The operation is time out.
@retval EFI_SUCCESS The command stop successfully.
@@ -1196,7 +1259,7 @@ AhciStopCommand (
AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
}
- return AhciWaitMemSet (
+ return AhciWaitMmioSet (
PciIo,
Offset,
EFI_AHCI_PORT_CMD_CR,
@@ -1211,7 +1274,7 @@ AhciStopCommand (
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
@param CommandSlot The number of Command Slot.
- @param Timeout The timeout value of start.
+ @param Timeout The timeout value of start, uses 100ns as a unit.
@retval EFI_DEVICE_ERROR The command start unsuccessfully.
@retval EFI_TIMEOUT The operation is time out.
@@ -1248,7 +1311,7 @@ AhciStartCommand (
);
Status = AhciEnableFisReceive (
- PciIo,
+ PciIo,
Port,
Timeout
);
@@ -1275,7 +1338,7 @@ AhciStartCommand (
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);
- AhciWaitMemSet (
+ AhciWaitMmioSet (
PciIo,
Offset,
EFI_AHCI_PORT_CMD_CLO,
@@ -1291,10 +1354,6 @@ AhciStartCommand (
//
// Setting the command
//
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SACT;
- AhciAndReg (PciIo, Offset, 0);
- AhciOrReg (PciIo, Offset, CmdSlotBit);
-
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
AhciAndReg (PciIo, Offset, 0);
AhciOrReg (PciIo, Offset, CmdSlotBit);
@@ -1307,8 +1366,8 @@ AhciStartCommand (
@param PciIo The PCI IO protocol instance.
@param Port The number of port.
- @param Timeout The timeout value of reset.
-
+ @param Timeout The timeout value of reset, uses 100ns as a unit.
+
@retval EFI_DEVICE_ERROR The port reset unsuccessfully
@retval EFI_TIMEOUT The reset operation is time out.
@retval EFI_SUCCESS The port reset successfully.
@@ -1353,7 +1412,7 @@ AhciPortReset (
// Wait for communication to be re-established
//
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
- Status = AhciWaitMemSet (
+ Status = AhciWaitMmioSet (
PciIo,
Offset,
EFI_AHCI_PORT_SSTS_DET_MASK,
@@ -1362,6 +1421,7 @@ AhciPortReset (
);
if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Port %d COMRESET failed: %r\n", Port, Status));
return Status;
}
@@ -1375,7 +1435,7 @@ AhciPortReset (
Do AHCI HBA reset.
@param PciIo The PCI IO protocol instance.
- @param Timeout The timeout value of reset.
+ @param Timeout The timeout value of reset, uses 100ns as a unit.
@retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.
@retval EFI_TIMEOUT The reset operation is time out.
@@ -1387,16 +1447,23 @@ EFIAPI
AhciReset (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT64 Timeout
- )
+ )
{
- UINT32 Delay;
+ UINT64 Delay;
UINT32 Value;
- AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
+ //
+ // Make sure that GHC.AE bit is set before accessing any AHCI registers.
+ //
+ Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
+
+ if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
+ AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
+ }
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
- Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
+ Delay = DivU64x32(Timeout, 1000) + 1;
do {
Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
@@ -1426,7 +1493,7 @@ AhciReset (
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
- @param PortMultiplier The timeout value of stop.
+ @param PortMultiplier The port multiplier port number.
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
@retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
@@ -1474,9 +1541,18 @@ AhciAtaSmartReturnStatusCheck (
);
if (EFI_ERROR (Status)) {
+ REPORT_STATUS_CODE (
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
+ );
return EFI_DEVICE_ERROR;
}
+ REPORT_STATUS_CODE (
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
+ );
+
FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
@@ -1490,12 +1566,19 @@ AhciAtaSmartReturnStatusCheck (
// The threshold exceeded condition is not detected by the device
//
DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
-
+ REPORT_STATUS_CODE (
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
+ );
} else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
//
// The threshold exceeded condition is detected by the device
//
DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
+ REPORT_STATUS_CODE (
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
+ );
}
}
@@ -1508,7 +1591,7 @@ AhciAtaSmartReturnStatusCheck (
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
- @param PortMultiplier The timeout value of stop.
+ @param PortMultiplier The port multiplier port number.
@param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
@@ -1534,13 +1617,23 @@ AhciAtaSmartSupport (
//
// S.M.A.R.T is not supported by the device
//
- DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
+ DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
Port, PortMultiplier));
+ REPORT_STATUS_CODE (
+ EFI_ERROR_CODE | EFI_ERROR_MINOR,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
+ );
} else {
//
// Check if the feature is enabled. If not, then enable S.M.A.R.T.
//
if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
+
+ REPORT_STATUS_CODE (
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
+ );
+
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
@@ -1610,11 +1703,11 @@ AhciAtaSmartSupport (
/**
Send Buffer cmd to specific device.
-
+
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
- @param PortMultiplier The timeout value of stop.
+ @param PortMultiplier The port multiplier port number.
@param Buffer The data buffer to store IDENTIFY PACKET data.
@retval EFI_DEVICE_ERROR The cmd abort with error occurs.
@@ -1630,7 +1723,7 @@ AhciIdentify (
IN EFI_AHCI_REGISTERS *AhciRegisters,
IN UINT8 Port,
IN UINT8 PortMultiplier,
- IN OUT EFI_IDENTIFY_DATA *Buffer
+ IN OUT EFI_IDENTIFY_DATA *Buffer
)
{
EFI_STATUS Status;
@@ -1659,7 +1752,7 @@ AhciIdentify (
&AtaStatusBlock,
Buffer,
sizeof (EFI_IDENTIFY_DATA),
- ATA_ATAPI_TIMEOUT,
+ ATA_ATAPI_TIMEOUT,
NULL
);
@@ -1668,11 +1761,11 @@ AhciIdentify (
/**
Send Buffer cmd to specific device.
-
+
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
- @param PortMultiplier The timeout value of stop.
+ @param PortMultiplier The port multiplier port number.
@param Buffer The data buffer to store IDENTIFY PACKET data.
@retval EFI_DEVICE_ERROR The cmd abort with error occurs.
@@ -1688,7 +1781,7 @@ AhciIdentifyPacket (
IN EFI_AHCI_REGISTERS *AhciRegisters,
IN UINT8 Port,
IN UINT8 PortMultiplier,
- IN OUT EFI_IDENTIFY_DATA *Buffer
+ IN OUT EFI_IDENTIFY_DATA *Buffer
)
{
EFI_STATUS Status;
@@ -1726,11 +1819,11 @@ AhciIdentifyPacket (
/**
Send SET FEATURE cmd on specific device.
-
+
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@param Port The number of port.
- @param PortMultiplier The timeout value of stop.
+ @param PortMultiplier The port multiplier port number.
@param Feature The data to send Feature register.
@param FeatureSpecificData The specific data for SET FEATURE cmd.
@@ -1775,7 +1868,7 @@ AhciDeviceSetFeature (
0,
&AtaCommandBlock,
&AtaStatusBlock,
- ATA_ATAPI_TIMEOUT,
+ ATA_ATAPI_TIMEOUT,
NULL
);
@@ -1783,12 +1876,12 @@ AhciDeviceSetFeature (
}
/**
- This function is used to send out ATAPI commands conforms to the Packet Command
+ This function is used to send out ATAPI commands conforms to the Packet Command
with PIO Protocol.
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
- @param Port The number of port.
+ @param Port The number of port.
@param PortMultiplier The number of port multiplier.
@param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
@@ -1852,7 +1945,7 @@ AhciPacketCommandExecute (
Packet->CdbLength,
&AtaCommandBlock,
&AtaStatusBlock,
- Packet->Timeout,
+ Packet->Timeout,
NULL
);
} else {
@@ -1868,7 +1961,7 @@ AhciPacketCommandExecute (
&AtaStatusBlock,
Buffer,
Length,
- Packet->Timeout,
+ Packet->Timeout,
NULL
);
}
@@ -1877,7 +1970,7 @@ AhciPacketCommandExecute (
/**
Allocate transfer-related data struct which is used at AHCI mode.
-
+
@param PciIo The PCI IO protocol instance.
@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
@@ -1894,6 +1987,7 @@ AhciCreateTransferDescriptor (
VOID *Buffer;
UINT32 Capability;
+ UINT32 PortImplementBitMap;
UINT8 MaxPortNumber;
UINT8 MaxCommandSlotNumber;
BOOLEAN Support64Bit;
@@ -1909,12 +2003,20 @@ AhciCreateTransferDescriptor (
// Collect AHCI controller information
//
Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
- MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
//
// Get the number of command slots per port supported by this HBA.
//
MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
Support64Bit = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
+
+ PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
+ //
+ // Get the highest bit of implemented ports which decides how many bytes are allocated for recived FIS.
+ //
+ MaxPortNumber = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);
+ if (MaxPortNumber == 0) {
+ return EFI_DEVICE_ERROR;
+ }
MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
Status = PciIo->AllocateBuffer (
@@ -1947,7 +2049,7 @@ AhciCreateTransferDescriptor (
if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {
//
- // Map error or unable to map the whole RFis buffer into a contiguous region.
+ // Map error or unable to map the whole RFis buffer into a contiguous region.
//
Status = EFI_OUT_OF_RESOURCES;
goto Error6;
@@ -1979,7 +2081,7 @@ AhciCreateTransferDescriptor (
if (EFI_ERROR (Status)) {
//
- // Free mapped resource.
+ // Free mapped resource.
//
Status = EFI_OUT_OF_RESOURCES;
goto Error5;
@@ -2035,7 +2137,7 @@ AhciCreateTransferDescriptor (
if (EFI_ERROR (Status)) {
//
- // Free mapped resource.
+ // Free mapped resource.
//
Status = EFI_OUT_OF_RESOURCES;
goto Error3;
@@ -2075,7 +2177,7 @@ AhciCreateTransferDescriptor (
return EFI_SUCCESS;
//
- // Map error or unable to map the whole CmdList buffer into a contiguous region.
+ // Map error or unable to map the whole CmdList buffer into a contiguous region.
//
Error1:
PciIo->Unmap (
@@ -2117,8 +2219,8 @@ Error6:
/**
Initialize ATA host controller at AHCI mode.
- The function is designed to initialize ATA host controller.
-
+ The function is designed to initialize ATA host controller.
+
@param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
**/
@@ -2146,6 +2248,7 @@ AhciModeInitialization (
EFI_ATA_COLLECTIVE_MODE *SupportedModes;
EFI_ATA_TRANSFER_MODE TransferMode;
UINT32 PhyDetectDelay;
+ UINT32 Value;
if (Instance == NULL) {
return EFI_INVALID_PARAMETER;
@@ -2154,21 +2257,43 @@ AhciModeInitialization (
PciIo = Instance->PciIo;
IdeInit = Instance->IdeControllerInit;
- Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
+ Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
if (EFI_ERROR (Status)) {
return EFI_DEVICE_ERROR;
}
//
- // Enable AE before accessing any AHCI registers
+ // Collect AHCI controller information
//
- AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
+ Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
//
- // Collect AHCI controller information
+ // Make sure that GHC.AE bit is set before accessing any AHCI registers.
//
- Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
+ Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
+
+ if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
+ AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
+ }
+
+ //
+ // Enable 64-bit DMA support in the PCI layer if this controller
+ // supports it.
+ //
+ if ((Capability & EFI_AHCI_CAP_S64A) != 0) {
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_WARN,
+ "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",
+ Status));
+ }
+ }
//
// Get the number of command slots per port supported by this HBA.
@@ -2177,10 +2302,10 @@ AhciModeInitialization (
//
// Get the bit map of those ports exposed by this HBA.
- // It indicates which ports that the HBA supports are available for software to use.
+ // It indicates which ports that the HBA supports are available for software to use.
//
PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
-
+
AhciRegisters = &Instance->AhciRegisters;
Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
@@ -2188,8 +2313,19 @@ AhciModeInitialization (
return EFI_OUT_OF_RESOURCES;
}
- for (Port = 0; Port < MaxPortNumber; Port ++) {
+ for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {
if ((PortImplementBitMap & (BIT0 << Port)) != 0) {
+ //
+ // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
+ //
+ if ((MaxPortNumber--) == 0) {
+ //
+ // Should never be here.
+ //
+ ASSERT (FALSE);
+ return EFI_SUCCESS;
+ }
+
IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
//
@@ -2238,16 +2374,6 @@ AhciModeInitialization (
//
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
- Status = AhciWaitMemSet (
- PciIo,
- Offset,
- EFI_AHCI_PORT_CMD_FR,
- EFI_AHCI_PORT_CMD_FR,
- EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT
- );
- if (EFI_ERROR (Status)) {
- continue;
- }
//
// Wait no longer than 10 ms to wait the Phy to detect the presence of a device.
@@ -2268,7 +2394,10 @@ AhciModeInitialization (
if (PhyDetectDelay == 0) {
//
// No device detected at this port.
+ // Clear PxCMD.SUD for those ports at which there are no device present.
//
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_SUD));
continue;
}
@@ -2292,8 +2421,9 @@ AhciModeInitialization (
MicroSecondDelay (1000);
PhyDetectDelay--;
} while (PhyDetectDelay > 0);
-
+
if (PhyDetectDelay == 0) {
+ DEBUG ((EFI_D_ERROR, "Port %d Device presence detected but phy not ready (TFD=0x%X)\n", Port, Data));
continue;
}
@@ -2301,8 +2431,8 @@ AhciModeInitialization (
// When the first D2H register FIS is received, the content of PxSIG register is updated.
//
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
- Status = AhciWaitMemSet (
- PciIo,
+ Status = AhciWaitMmioSet (
+ PciIo,
Offset,
0x0000FFFF,
0x00000101,
@@ -2333,13 +2463,13 @@ AhciModeInitialization (
} else {
continue;
}
- DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",
+ DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",
Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
//
// If the device is a hard disk, then try to enable S.M.A.R.T feature
//
- if (DeviceType == EfiIdeHarddisk) {
+ if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
AhciAtaSmartSupport (
PciIo,
AhciRegisters,
@@ -2391,7 +2521,7 @@ AhciModeInitialization (
TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
} else if (SupportedModes->MultiWordDmaMode.Valid) {
TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
- TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
+ TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
}
Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));
@@ -2403,7 +2533,7 @@ AhciModeInitialization (
//
// Found a ATA or ATAPI device, add it into the device list.
//
- CreateNewDeviceInfo (Instance, Port, 0, DeviceType, &Buffer);
+ CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);
if (DeviceType == EfiIdeHarddisk) {
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
}