X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FPciBusDxe%2FPciDeviceSupport.c;h=97bb971a5966a2d869d8da42b47cb4e5be386f27;hp=0d1518a43d01c99bf1a68cfecf73ce6ceaffdde7;hb=8315563285719f09f13e69a408f34558fc41c822;hpb=cd5ebaa06dca3e6ef3c464081e6defe00d358c69

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 0d1518a43d..97bb971a59 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -1,7 +1,7 @@
 /** @file
   Supporting functions implementaion for PCI devices management.
 
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -215,10 +215,6 @@ RegisterPciDevice (
   EFI_PCI_IO_PROTOCOL *PciIo;
   UINT8               Data8;
   BOOLEAN             HasEfiImage;
-  PCI_IO_DEVICE       *ParrentPciIoDevice;
-  EFI_PCI_IO_PROTOCOL *ParrentPciIo;
-  UINT16              Data16;
-  UINT32              Data32;
 
   //
   // Install the pciio protocol, device path protocol
@@ -255,35 +251,7 @@ RegisterPciDevice (
   PciIo = &(PciIoDevice->PciIo);
   Data8 = PCI_INT_LINE_UNKNOWN;
   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
-  
-  //
-  // PCI-IOV programming
-  //
-  if (((FeaturePcdGet(PcdAriSupport) & EFI_PCI_IOV_POLICY_ARI) != 0) && (PciIoDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport) & EFI_PCI_IOV_POLICY_SRIOV) != 0) &&
-      (PciIoDevice->SrIovCapabilityOffset != 0)) {
-    //
-    // Check its parrent ARI forwarding capability
-    //
-    ParrentPciIoDevice = PciIoDevice->Parent;
-    ParrentPciIo = &(ParrentPciIoDevice->PciIo);
-    ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, 1, &Data32);
-    if ((Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) != 0) {
-      //
-      // ARI forward support in bridge, so enable it.
-      //
-      ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
-      Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
-      ParrentPciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
-
-      //
-      // Set ARI Capable Hierarchy for device
-      //
-      PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
-      Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
-    }
-  }
-  
+ 
   //
   // Process OpRom
   //
@@ -300,6 +268,7 @@ RegisterPciDevice (
                                        &PlatformOpRomSize
                                        );
       if (!EFI_ERROR (Status)) {
+        PciIoDevice->EmbeddedRom    = FALSE;
         PciIoDevice->RomSize        = PlatformOpRomSize;
         PciIoDevice->PciIo.RomSize  = PlatformOpRomSize;
         PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
@@ -313,7 +282,7 @@ RegisterPciDevice (
           PciIoDevice->BusNumber,
           PciIoDevice->DeviceNumber,
           PciIoDevice->FunctionNumber,
-          (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,
+          PciIoDevice->PciIo.RomImage,
           PciIoDevice->PciIo.RomSize
           );
       }
@@ -325,6 +294,7 @@ RegisterPciDevice (
                                        &PlatformOpRomSize
                                        );
       if (!EFI_ERROR (Status)) {
+        PciIoDevice->EmbeddedRom    = FALSE;
         PciIoDevice->RomSize        = PlatformOpRomSize;
         PciIoDevice->PciIo.RomSize  = PlatformOpRomSize;
         PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
@@ -338,7 +308,7 @@ RegisterPciDevice (
           PciIoDevice->BusNumber,
           PciIoDevice->DeviceNumber,
           PciIoDevice->FunctionNumber,
-          (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,
+          PciIoDevice->PciIo.RomImage,
           PciIoDevice->PciIo.RomSize
           );
       }   
@@ -726,7 +696,7 @@ StartPciDevicesOnBridge (
       //
       // If it is a PPB
       //
-      if (!IsListEmpty (&PciIoDevice->ChildList)) {
+      if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
         Status = StartPciDevicesOnBridge (
                    Controller,
                    PciIoDevice,
@@ -741,7 +711,12 @@ StartPciDevicesOnBridge (
                              0,
                              &Supports
                              );
-        Supports &= EFI_PCI_DEVICE_ENABLE;
+        //
+        // By default every bridge's IO and MMIO spaces are enabled.
+        // Bridge's Bus Master will be enabled when any device behind it requests
+        // to enable Bus Master.
+        //
+        Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
         PciIoDevice->PciIo.Attributes (
                              &(PciIoDevice->PciIo),
                              EfiPciIoAttributeOperationEnable,
@@ -778,7 +753,7 @@ StartPciDevicesOnBridge (
         (*NumberOfChildren)++;
       }
 
-      if (!IsListEmpty (&PciIoDevice->ChildList)) {
+      if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
         Status = StartPciDevicesOnBridge (
                    Controller,
                    PciIoDevice,
@@ -793,7 +768,12 @@ StartPciDevicesOnBridge (
                              0,
                              &Supports
                              );
-        Supports &= EFI_PCI_DEVICE_ENABLE;
+        //
+        // By default every bridge's IO and MMIO spaces are enabled.
+        // Bridge's Bus Master will be enabled when any device behind it requests
+        // to enable Bus Master.
+        //
+        Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
         PciIoDevice->PciIo.Attributes (
                              &(PciIoDevice->PciIo),
                              EfiPciIoAttributeOperationEnable,