X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FPciBusDxe%2FPciDeviceSupport.c;h=97bb971a5966a2d869d8da42b47cb4e5be386f27;hp=8ba5fc57ead108a59ae7f6c473cbd44f6a099f48;hb=8315563285719f09f13e69a408f34558fc41c822;hpb=4ed4e19c084e03fcb8cfdcb159145136093d4180
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 8ba5fc57ea..97bb971a59 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -1,7 +1,7 @@
/** @file
Supporting functions implementaion for PCI devices management.
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -282,7 +282,7 @@ RegisterPciDevice (
PciIoDevice->BusNumber,
PciIoDevice->DeviceNumber,
PciIoDevice->FunctionNumber,
- (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,
+ PciIoDevice->PciIo.RomImage,
PciIoDevice->PciIo.RomSize
);
}
@@ -308,7 +308,7 @@ RegisterPciDevice (
PciIoDevice->BusNumber,
PciIoDevice->DeviceNumber,
PciIoDevice->FunctionNumber,
- (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,
+ PciIoDevice->PciIo.RomImage,
PciIoDevice->PciIo.RomSize
);
}
@@ -711,7 +711,12 @@ StartPciDevicesOnBridge (
0,
&Supports
);
- Supports &= EFI_PCI_DEVICE_ENABLE;
+ //
+ // By default every bridge's IO and MMIO spaces are enabled.
+ // Bridge's Bus Master will be enabled when any device behind it requests
+ // to enable Bus Master.
+ //
+ Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
PciIoDevice->PciIo.Attributes (
&(PciIoDevice->PciIo),
EfiPciIoAttributeOperationEnable,
@@ -763,7 +768,12 @@ StartPciDevicesOnBridge (
0,
&Supports
);
- Supports &= EFI_PCI_DEVICE_ENABLE;
+ //
+ // By default every bridge's IO and MMIO spaces are enabled.
+ // Bridge's Bus Master will be enabled when any device behind it requests
+ // to enable Bus Master.
+ //
+ Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
PciIoDevice->PciIo.Attributes (
&(PciIoDevice->PciIo),
EfiPciIoAttributeOperationEnable,