X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FPciBusDxe%2FPciDeviceSupport.c;h=e76c8f00468a87e9db7d6b014b3cffa257cd2a89;hp=25387bd257c7707da4127a97906189d14a64c4f0;hb=a8035b908655afd59321173752b29970ae61601b;hpb=9060e3ec6dfd6048724832947933650cde873381

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
index 25387bd257..e76c8f0046 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
@@ -1,8 +1,8 @@
 /** @file
   Supporting functions implementaion for PCI devices management.
 
-Copyright (c) 2006 - 2009, Intel Corporation
-All rights reserved. This program and the accompanying materials
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
 http://opensource.org/licenses/bsd-license.php
@@ -215,10 +215,6 @@ RegisterPciDevice (
   EFI_PCI_IO_PROTOCOL *PciIo;
   UINT8               Data8;
   BOOLEAN             HasEfiImage;
-  PCI_IO_DEVICE       *ParrentPciIoDevice;
-  EFI_PCI_IO_PROTOCOL *ParrentPciIo;
-  UINT16              Data16;
-  UINT32              Data32;
 
   //
   // Install the pciio protocol, device path protocol
@@ -255,35 +251,7 @@ RegisterPciDevice (
   PciIo = &(PciIoDevice->PciIo);
   Data8 = PCI_INT_LINE_UNKNOWN;
   PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);
-  
-  //
-  // PCI-IOV programming
-  //
-  if (((FeaturePcdGet(PcdAriSupport) & EFI_PCI_IOV_POLICY_ARI) != 0) && (PciIoDevice->AriCapabilityOffset != 0) && ((FeaturePcdGet(PcdSrIovSupport) & EFI_PCI_IOV_POLICY_SRIOV) != 0) &&
-      (PciIoDevice->SrIovCapabilityOffset != 0)) {
-    //
-    // Check its parrent ARI forwarding capability
-    //
-    ParrentPciIoDevice = PciIoDevice->Parent;
-    ParrentPciIo = &(ParrentPciIoDevice->PciIo);
-    ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET, 1, &Data32);
-    if (Data32 & EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) {
-      //
-      // ARI forward support in bridge, so enable it.
-      //
-      ParrentPciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
-      Data32 |= EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING;
-      ParrentPciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, ParrentPciIoDevice->PciExpressCapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET, 1, &Data32);
-
-      //
-      // Set ARI Capable Hierarchy for device
-      //
-      PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
-      Data16 |= EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY;
-      PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, PciIoDevice->SrIovCapabilityOffset + EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL, 1, &Data16);
-    }
-  }
-  
+ 
   //
   // Process OpRom
   //
@@ -300,6 +268,7 @@ RegisterPciDevice (
                                        &PlatformOpRomSize
                                        );
       if (!EFI_ERROR (Status)) {
+        PciIoDevice->EmbeddedRom    = FALSE;
         PciIoDevice->RomSize        = PlatformOpRomSize;
         PciIoDevice->PciIo.RomSize  = PlatformOpRomSize;
         PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
@@ -313,7 +282,7 @@ RegisterPciDevice (
           PciIoDevice->BusNumber,
           PciIoDevice->DeviceNumber,
           PciIoDevice->FunctionNumber,
-          (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,
+          PciIoDevice->PciIo.RomImage,
           PciIoDevice->PciIo.RomSize
           );
       }
@@ -325,6 +294,7 @@ RegisterPciDevice (
                                        &PlatformOpRomSize
                                        );
       if (!EFI_ERROR (Status)) {
+        PciIoDevice->EmbeddedRom    = FALSE;
         PciIoDevice->RomSize        = PlatformOpRomSize;
         PciIoDevice->PciIo.RomSize  = PlatformOpRomSize;
         PciIoDevice->PciIo.RomImage = PlatformOpRomBuffer;
@@ -338,7 +308,7 @@ RegisterPciDevice (
           PciIoDevice->BusNumber,
           PciIoDevice->DeviceNumber,
           PciIoDevice->FunctionNumber,
-          (UINT64) (UINTN) PciIoDevice->PciIo.RomImage,
+          PciIoDevice->PciIo.RomImage,
           PciIoDevice->PciIo.RomSize
           );
       }   
@@ -726,7 +696,7 @@ StartPciDevicesOnBridge (
       //
       // If it is a PPB
       //
-      if (!IsListEmpty (&PciIoDevice->ChildList)) {
+      if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
         Status = StartPciDevicesOnBridge (
                    Controller,
                    PciIoDevice,
@@ -741,7 +711,7 @@ StartPciDevicesOnBridge (
                              0,
                              &Supports
                              );
-        Supports &= EFI_PCI_DEVICE_ENABLE;
+        Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
         PciIoDevice->PciIo.Attributes (
                              &(PciIoDevice->PciIo),
                              EfiPciIoAttributeOperationEnable,
@@ -778,7 +748,7 @@ StartPciDevicesOnBridge (
         (*NumberOfChildren)++;
       }
 
-      if (!IsListEmpty (&PciIoDevice->ChildList)) {
+      if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
         Status = StartPciDevicesOnBridge (
                    Controller,
                    PciIoDevice,
@@ -793,7 +763,7 @@ StartPciDevicesOnBridge (
                              0,
                              &Supports
                              );
-        Supports &= EFI_PCI_DEVICE_ENABLE;
+        Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
         PciIoDevice->PciIo.Attributes (
                              &(PciIoDevice->PciIo),
                              EfiPciIoAttributeOperationEnable,