X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FXhciDxe%2FXhciReg.c;h=4d5937de538f8b907c44ec5ecf1a002a44ef3cfc;hp=0e1c86cc16f4b7f2464b3e2e69bc44842c353713;hb=16f6922709952c7ad468dcdee6ef94b3e5a3cd90;hpb=95ba3d92dca2616715e2af89d2bbeca9577a3e2c diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c index 0e1c86cc16..4d5937de53 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -2,7 +2,7 @@ The XHCI register operation routines. -Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -112,7 +112,7 @@ XhcReadOpReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->CapLength + Offset), + Xhc->CapLength + Offset, 1, &Data ); @@ -148,7 +148,7 @@ XhcWriteOpReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->CapLength + Offset), + Xhc->CapLength + Offset, 1, &Data ); @@ -181,7 +181,7 @@ XhcWriteOpReg16 ( Xhc->PciIo, EfiPciIoWidthUint16, XHC_BAR_INDEX, - (UINT64) (Xhc->CapLength + Offset), + Xhc->CapLength + Offset, 1, &Data ); @@ -215,7 +215,7 @@ XhcReadDoorBellReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->DBOff + Offset), + Xhc->DBOff + Offset, 1, &Data ); @@ -251,7 +251,7 @@ XhcWriteDoorBellReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->DBOff + Offset), + Xhc->DBOff + Offset, 1, &Data ); @@ -285,7 +285,7 @@ XhcReadRuntimeReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->RTSOff + Offset), + Xhc->RTSOff + Offset, 1, &Data ); @@ -321,7 +321,7 @@ XhcWriteRuntimeReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->RTSOff + Offset), + Xhc->RTSOff + Offset, 1, &Data ); @@ -355,7 +355,7 @@ XhcReadExtCapReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->ExtCapRegBase + Offset), + Xhc->ExtCapRegBase + Offset, 1, &Data ); @@ -391,7 +391,7 @@ XhcWriteExtCapReg ( Xhc->PciIo, EfiPciIoWidthUint32, XHC_BAR_INDEX, - (UINT64) (Xhc->ExtCapRegBase + Offset), + Xhc->ExtCapRegBase + Offset, 1, &Data );