X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FXhciDxe%2FXhciSched.c;h=f7f3409686b8c9d13484b0f2cbb571475b63809b;hp=1130b6aac14bdbc6718e6d1f1f05fffc7565e091;hb=396ae94d46906c52875054a0487d37cad2ff1216;hpb=fd5d2dd2f55eedb3cf6001cc00587020c90411f5
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 1130b6aac1..f7f3409686 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2,7 +2,7 @@
XHCI transfer scheduling routines.
-Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -604,8 +604,6 @@ XhcInitSched (
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRingPhy));
XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRingPhy));
- DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));
-
//
// Disable the 'interrupter enable' bit in USB_CMD
// and clear IE & IP bit in all Interrupter X Management Registers.
@@ -620,7 +618,10 @@ XhcInitSched (
// Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer
//
CreateEventRing (Xhc, &Xhc->EventRing);
- DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));
+ DEBUG ((DEBUG_INFO, "XhcInitSched: Created CMD ring [%p~%p) EVENT ring [%p~%p)\n",
+ Xhc->CmdRing.RingSeg0, (UINTN)Xhc->CmdRing.RingSeg0 + sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER,
+ Xhc->EventRing.EventRingSeg0, (UINTN)Xhc->EventRing.EventRingSeg0 + sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER
+ ));
}
/**
@@ -977,41 +978,42 @@ XhcFreeSched (
}
/**
- Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
+ Check if the Trb is a transaction of the URB.
- @param Xhc The XHCI Instance.
- @param Trb The TRB to be checked.
- @param Urb The pointer to the matched Urb.
+ @param Trb The TRB to be checked
+ @param Urb The URB to be checked.
- @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
- @retval FALSE The Trb is not matched with any URBs in the async list.
+ @retval TRUE It is a transaction of the URB.
+ @retval FALSE It is not any transaction of the URB.
**/
BOOLEAN
-IsAsyncIntTrb (
+IsTransferRingTrb (
IN USB_XHCI_INSTANCE *Xhc,
IN TRB_TEMPLATE *Trb,
- OUT URB **Urb
+ IN URB *Urb
)
{
- LIST_ENTRY *Entry;
- LIST_ENTRY *Next;
- TRB_TEMPLATE *CheckedTrb;
- URB *CheckedUrb;
- UINTN Index;
+ LINK_TRB *LinkTrb;
+ TRB_TEMPLATE *CheckedTrb;
+ UINTN Index;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
- CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
- CheckedTrb = CheckedUrb->TrbStart;
- for (Index = 0; Index < CheckedUrb->TrbNum; Index++) {
- if (Trb == CheckedTrb) {
- *Urb = CheckedUrb;
- return TRUE;
- }
- CheckedTrb++;
- if ((UINTN)CheckedTrb >= ((UINTN) CheckedUrb->Ring->RingSeg0 + sizeof (TRB_TEMPLATE) * CheckedUrb->Ring->TrbNumber)) {
- CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0;
- }
+ CheckedTrb = Urb->TrbStart;
+ for (Index = 0; Index < Urb->TrbNum; Index++) {
+ if (Trb == CheckedTrb) {
+ return TRUE;
+ }
+ CheckedTrb++;
+ //
+ // If the checked TRB is the link TRB at the end of the transfer ring,
+ // recircle it to the head of the ring.
+ //
+ if (CheckedTrb->Type == TRB_TYPE_LINK) {
+ LinkTrb = (LINK_TRB *) CheckedTrb;
+ PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32));
+ CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE));
+ ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
}
}
@@ -1019,38 +1021,39 @@ IsAsyncIntTrb (
}
/**
- Check if the Trb is a transaction of the URB.
+ Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.
- @param Trb The TRB to be checked
- @param Urb The transfer ring to be checked.
+ @param Xhc The XHCI Instance.
+ @param Trb The TRB to be checked.
+ @param Urb The pointer to the matched Urb.
- @retval TRUE It is a transaction of the URB.
- @retval FALSE It is not any transaction of the URB.
+ @retval TRUE The Trb is matched with a transaction of the URBs in the async list.
+ @retval FALSE The Trb is not matched with any URBs in the async list.
**/
BOOLEAN
-IsTransferRingTrb (
+IsAsyncIntTrb (
+ IN USB_XHCI_INSTANCE *Xhc,
IN TRB_TEMPLATE *Trb,
- IN URB *Urb
+ OUT URB **Urb
)
{
- TRB_TEMPLATE *CheckedTrb;
- UINTN Index;
-
- CheckedTrb = Urb->Ring->RingSeg0;
-
- ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER);
+ LIST_ENTRY *Entry;
+ LIST_ENTRY *Next;
+ URB *CheckedUrb;
- for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) {
- if (Trb == CheckedTrb) {
+ EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
+ if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {
+ *Urb = CheckedUrb;
return TRUE;
}
- CheckedTrb++;
}
return FALSE;
}
+
/**
Check the URB's execution result and update the URB's
result accordingly.
@@ -1127,7 +1130,7 @@ XhcCheckUrbResult (
// This way is used to avoid that those completed async transfer events don't get
// handled in time and are flushed by newer coming events.
//
- if (IsTransferRingTrb (TRBPtr, Urb)) {
+ if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) {
CheckedUrb = Urb;
} else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) {
CheckedUrb = AsyncUrb;
@@ -1163,7 +1166,7 @@ XhcCheckUrbResult (
case TRB_COMPLETION_SHORT_PACKET:
case TRB_COMPLETION_SUCCESS:
if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {
- DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: short packet happens!\n"));
+ DEBUG ((EFI_D_VERBOSE, "XhcCheckUrbResult: short packet happens!\n"));
}
TRBType = (UINT8) (TRBPtr->Type);
@@ -1315,6 +1318,7 @@ XhciDelAsyncIntTransfer (
LIST_ENTRY *Next;
URB *Urb;
EFI_USB_DATA_DIRECTION Direction;
+ EFI_STATUS Status;
Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
EpNum &= 0x0F;
@@ -1326,6 +1330,15 @@ XhciDelAsyncIntTransfer (
if ((Urb->Ep.BusAddr == BusAddr) &&
(Urb->Ep.EpAddr == EpNum) &&
(Urb->Ep.Direction == Direction)) {
+ //
+ // Device doesn't finish the IntTransfer until real data comes
+ // So the TRB should be removed as well.
+ //
+ Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "XhciDelAsyncIntTransfer: XhcDequeueTrbFromEndpoint failed\n"));
+ }
+
RemoveEntryList (&Urb->UrbList);
FreePool (Urb->Data);
XhcFreeUrb (Xhc, Urb);
@@ -1350,9 +1363,20 @@ XhciDelAllAsyncIntTransfers (
LIST_ENTRY *Entry;
LIST_ENTRY *Next;
URB *Urb;
+ EFI_STATUS Status;
EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
+
+ //
+ // Device doesn't finish the IntTransfer until real data comes
+ // So the TRB should be removed as well.
+ //
+ Status = XhcDequeueTrbFromEndpoint (Xhc, Urb);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "XhciDelAllAsyncIntTransfers: XhcDequeueTrbFromEndpoint failed\n"));
+ }
+
RemoveEntryList (&Urb->UrbList);
FreePool (Urb->Data);
XhcFreeUrb (Xhc, Urb);
@@ -2111,6 +2135,10 @@ XhcInitializeDeviceSlot (
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above.
//
+ // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
+ // to device.
+ //
+ gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
@@ -2317,6 +2345,10 @@ XhcInitializeDeviceSlot64 (
// 8) Issue an Address Device Command for the Device Slot, where the command points to the Input
// Context data structure described above.
//
+ // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5 before sending SetAddress() request
+ // to device.
+ //
+ gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
@@ -2637,6 +2669,11 @@ XhcInitializeEndpointContext (
EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2648,6 +2685,20 @@ XhcInitializeEndpointContext (
InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+ //
+ // Get the bInterval from descriptor and init the the interval field of endpoint context.
+ // Refer to XHCI 1.1 spec section 6.2.3.6.
+ //
+ if (DeviceSpeed == EFI_USB_SPEED_FULL) {
+ Interval = EpDesc->Interval;
+ ASSERT (Interval >= 1 && Interval <= 16);
+ InputContext->EP[Dci-1].Interval = Interval + 2;
+ } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
+ Interval = EpDesc->Interval;
+ ASSERT (Interval >= 1 && Interval <= 16);
+ InputContext->EP[Dci-1].Interval = Interval - 1;
+ }
+
//
// Do not support isochronous transfer now.
//
@@ -2691,6 +2742,11 @@ XhcInitializeEndpointContext (
EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((DEBUG_INFO, "Endpoint[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2805,6 +2861,11 @@ XhcInitializeEndpointContext64 (
EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created BULK ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;
@@ -2816,6 +2877,20 @@ XhcInitializeEndpointContext64 (
InputContext->EP[Dci-1].CErr = 0;
InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
}
+ //
+ // Get the bInterval from descriptor and init the the interval field of endpoint context.
+ // Refer to XHCI 1.1 spec section 6.2.3.6.
+ //
+ if (DeviceSpeed == EFI_USB_SPEED_FULL) {
+ Interval = EpDesc->Interval;
+ ASSERT (Interval >= 1 && Interval <= 16);
+ InputContext->EP[Dci-1].Interval = Interval + 2;
+ } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {
+ Interval = EpDesc->Interval;
+ ASSERT (Interval >= 1 && Interval <= 16);
+ InputContext->EP[Dci-1].Interval = Interval - 1;
+ }
+
//
// Do not support isochronous transfer now.
//
@@ -2859,6 +2934,11 @@ XhcInitializeEndpointContext64 (
EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));
Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;
CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);
+ DEBUG ((DEBUG_INFO, "Endpoint64[%x]: Created INT ring [%p~%p)\n",
+ EpDesc->EndpointAddress,
+ EndpointTransferRing->RingSeg0,
+ (UINTN) EndpointTransferRing->RingSeg0 + TR_RING_TRB_NUMBER * sizeof (TRB_TEMPLATE)
+ ));
}
break;