X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FCore%2FDxeIplPeim%2FIa32%2FDxeLoadFunc.c;h=8a939b6c24870f03f6e9ce0f7de633afc03e279b;hp=33c77374a963ae1fe5b2d322133d9614a3ba69de;hb=98d20e44dc72d9858523687fda11ab8fc570fcec;hpb=99cc7b9507fa4d1efbf1b509b538905418712add
diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
index 33c77374a9..8a939b6c24 100644
--- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
+++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
@@ -1,7 +1,7 @@
/** @file
Ia32-specific functionality for DxeLoad.
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -73,7 +73,7 @@ Create4GPageTablesIa32Pae (
IN EFI_PHYSICAL_ADDRESS StackBase,
IN UINTN StackSize
)
-{
+{
UINT8 PhysicalAddressBits;
EFI_PHYSICAL_ADDRESS PhysicalAddress;
UINTN IndexOfPdpEntries;
@@ -99,7 +99,7 @@ Create4GPageTablesIa32Pae (
NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, (PhysicalAddressBits - 30));
TotalPagesNum = NumberOfPdpEntriesNeeded + 1;
- PageAddress = (UINTN) AllocatePages (TotalPagesNum);
+ PageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);
ASSERT (PageAddress != 0);
PageMap = (VOID *) PageAddress;
@@ -112,7 +112,7 @@ Create4GPageTablesIa32Pae (
//
// Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
- //
+ //
PageDirectoryEntry = (VOID *) PageAddress;
PageAddress += SIZE_4KB;
@@ -149,6 +149,12 @@ Create4GPageTablesIa32Pae (
);
}
+ //
+ // Protect the page table by marking the memory used for page table to be
+ // read-only.
+ //
+ EnablePageTableProtection ((UINTN)PageMap, FALSE);
+
return (UINTN) PageMap;
}
@@ -211,37 +217,41 @@ IsExecuteDisableBitAvailable (
return Available;
}
-/**
- The function will check if page table should be setup or not.
-
- @retval TRUE Page table should be created.
- @retval FALSE Page table should not be created.
-
-**/
-BOOLEAN
-ToBuildPageTable (
- VOID
- )
-{
- if (!IsIa32PaeSupport ()) {
- return FALSE;
- }
-
- if (IsNullDetectionEnabled ()) {
- return TRUE;
- }
-
- if (PcdGet8 (PcdHeapGuardPropertyMask) != 0) {
- return TRUE;
- }
-
- if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) {
- return TRUE;
- }
-
- return FALSE;
-}
-
+/**
+ The function will check if page table should be setup or not.
+
+ @retval TRUE Page table should be created.
+ @retval FALSE Page table should not be created.
+
+**/
+BOOLEAN
+ToBuildPageTable (
+ VOID
+ )
+{
+ if (!IsIa32PaeSupport ()) {
+ return FALSE;
+ }
+
+ if (IsNullDetectionEnabled ()) {
+ return TRUE;
+ }
+
+ if (PcdGet8 (PcdHeapGuardPropertyMask) != 0) {
+ return TRUE;
+ }
+
+ if (PcdGetBool (PcdCpuStackGuard)) {
+ return TRUE;
+ }
+
+ if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable ()) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
/**
Transfers control to DxeCore.
@@ -310,7 +320,9 @@ HandOffToDxeCore (
//
// End of PEI phase signal
//
+ PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
+ PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
ASSERT_EFI_ERROR (Status);
AsmWriteCr3 (PageTables);
@@ -416,7 +428,7 @@ HandOffToDxeCore (
TopOfStack = (EFI_PHYSICAL_ADDRESS) (UINTN) ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
PageTables = 0;
- BuildPageTablesIa32Pae = ToBuildPageTable ();
+ BuildPageTablesIa32Pae = ToBuildPageTable ();
if (BuildPageTablesIa32Pae) {
PageTables = Create4GPageTablesIa32Pae (BaseOfStack, STACK_SIZE);
if (IsExecuteDisableBitAvailable ()) {
@@ -427,7 +439,9 @@ HandOffToDxeCore (
//
// End of PEI phase signal
//
+ PERF_EVENT_SIGNAL_BEGIN (gEndOfPeiSignalPpi.Guid);
Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
+ PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid);
ASSERT_EFI_ERROR (Status);
if (BuildPageTablesIa32Pae) {