X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdeModulePkg%2FCore%2FPei%2FIpf%2FIpfCpuCore.i;fp=MdeModulePkg%2FCore%2FPei%2FIpf%2FIpfCpuCore.i;h=0000000000000000000000000000000000000000;hp=c8a209debce060d3fc75223c9d8766e36f87e849;hb=974a1fd139ee3a51aa89362870694f2850c267eb;hpb=e4571e3d73b72967bbe0d38fe01aa7ba17be3772 diff --git a/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i b/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i deleted file mode 100644 index c8a209debc..0000000000 --- a/MdeModulePkg/Core/Pei/Ipf/IpfCpuCore.i +++ /dev/null @@ -1,93 +0,0 @@ -//++ -// Copyright (c) 2006, Intel Corporation -// All rights reserved. This program and the accompanying materials -// are licensed and made available under the terms and conditions of the BSD License -// which accompanies this distribution. The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -// -// Module Name: -// -// IpfCpuCore.i -// -// Abstract: -// IPF CPU definitions -// -//-- - -#ifndef _IPF_CPU_CORE_ -#define _IPF_CPU_CORE_ - -#define PEI_BSP_STORE_SIZE 0x4000 -#define ResetFn 0x00 -#define MachineCheckFn 0x01 -#define InitFn 0x02 -#define RecoveryFn 0x03 -#define GuardBand 0x10 - -// -// Define hardware RSE Configuration Register -// - -// -// RS Configuration (RSC) bit field positions -// -#define RSC_MODE 0 -#define RSC_PL 2 -#define RSC_BE 4 -// -// RSC bits 5-15 reserved -// -#define RSC_MBZ0 5 -#define RSC_MBZ0_V 0x3ff -#define RSC_LOADRS 16 -#define RSC_LOADRS_LEN 14 -// -// RSC bits 30-63 reserved -// -#define RSC_MBZ1 30 -#define RSC_MBZ1_V 0x3ffffffffULL - -// -// RSC modes -// - -// -// Lazy -// -#define RSC_MODE_LY (0x0) -// -// Store intensive -// -#define RSC_MODE_SI (0x1) -// -// Load intensive -// -#define RSC_MODE_LI (0x2) -// -// Eager -// -#define RSC_MODE_EA (0x3) - -// -// RSC Endian bit values -// -#define RSC_BE_LITTLE 0 -#define RSC_BE_BIG 1 - -// -// RSC while in kernel: enabled, little endian, pl = 0, eager mode -// -#define RSC_KERNEL ((RSC_MODE_EA<