X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FInclude%2FIndustryStandard%2FPci22.h;h=96a76801d3e95166abfe6142aecef4ba938e6fe5;hp=78ec6b316629fc9d876413924011da7dd6c44d50;hb=90ebd67808df57e435d7113a28ad26add429a766;hpb=0e8768b65a10e96b5a044181b3bdd8b1c5cdcefd
diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 78ec6b3166..96a76801d3 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -5,11 +5,10 @@
PCI Local Bus Specification, 2.2
PCI-to-PCI Bridge Architecture Specification, Revision 1.2
PC Card Standard, 8.0
+ PCI Power Management Interface Specifiction, Revision 1.2
-
-
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
- Copyright (c) 2014 - 2105, Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -636,6 +635,7 @@ typedef union {
#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04
#define EFI_PCI_CAPABILITY_ID_MSI 0x05
#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C
///
/// Capabilities List Header
@@ -646,18 +646,6 @@ typedef struct {
UINT8 NextItemPtr;
} EFI_PCI_CAPABILITY_HDR;
-///
-/// Power Management Register Block Definition
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
-///
-typedef struct {
- EFI_PCI_CAPABILITY_HDR Hdr;
- UINT16 PMC;
- UINT16 PMCSR;
- UINT8 BridgeExtention;
- UINT8 Data;
-} EFI_PCI_CAPABILITY_PMI;
-
///
/// PMC - Power Management Capabilities
/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
@@ -666,7 +654,7 @@ typedef union {
struct {
UINT16 Version : 3;
UINT16 PmeClock : 1;
- UINT16 : 1;
+ UINT16 Reserved : 1;
UINT16 DeviceSpecificInitialization : 1;
UINT16 AuxCurrent : 3;
UINT16 D1Support : 1;
@@ -685,7 +673,9 @@ typedef union {
typedef union {
struct {
UINT16 PowerState : 2;
- UINT16 : 6;
+ UINT16 ReservedForPciExpress : 1;
+ UINT16 NoSoftReset : 1;
+ UINT16 Reserved : 4;
UINT16 PmeEnable : 1;
UINT16 DataSelect : 4;
UINT16 DataScale : 2;
@@ -694,6 +684,36 @@ typedef union {
UINT16 Data;
} EFI_PCI_PMCSR;
+#define PCI_POWER_STATE_D0 0
+#define PCI_POWER_STATE_D1 1
+#define PCI_POWER_STATE_D2 2
+#define PCI_POWER_STATE_D3_HOT 3
+
+///
+/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
+/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
+///
+typedef union {
+ struct {
+ UINT8 Reserved : 6;
+ UINT8 B2B3 : 1;
+ UINT8 BusPowerClockControl : 1;
+ } Bits;
+ UINT8 Uint8;
+} EFI_PCI_PMCSR_BSE;
+
+///
+/// Power Management Register Block Definition
+/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
+///
+typedef struct {
+ EFI_PCI_CAPABILITY_HDR Hdr;
+ EFI_PCI_PMC PMC;
+ EFI_PCI_PMCSR PMCSR;
+ EFI_PCI_PMCSR_BSE BridgeExtention;
+ UINT8 Data;
+} EFI_PCI_CAPABILITY_PMI;
+
///
/// A.G.P Capability
/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
@@ -760,22 +780,12 @@ typedef struct {
///
} EFI_PCI_CAPABILITY_HOTPLUG;
-#define DEVICE_ID_NOCARE 0xFFFF
-
-#define PCI_ACPI_UNUSED 0
-#define PCI_BAR_NOCHANGE 0
-#define PCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL
-#define PCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
-
#define PCI_BAR_IDX0 0x00
#define PCI_BAR_IDX1 0x01
#define PCI_BAR_IDX2 0x02
#define PCI_BAR_IDX3 0x03
#define PCI_BAR_IDX4 0x04
#define PCI_BAR_IDX5 0x05
-#define PCI_BAR_ALL 0xFF
///
/// EFI PCI Option ROM definitions