X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FInclude%2FIndustryStandard%2FPciExpress30.h;h=db6a427bc8749e65d55ab4e9dc7cafafcb3e298f;hp=6e9e105da912d29b201e29e2a4313fe3381c8927;hb=cbedba8698b1a9f6e2e440219d03a263e09d2822;hpb=dd85dd0731e971c5782fb94b2cbac8669b33312b

diff --git a/MdePkg/Include/IndustryStandard/PciExpress30.h b/MdePkg/Include/IndustryStandard/PciExpress30.h
index 6e9e105da9..db6a427bc8 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress30.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -3,7 +3,7 @@
 
   This header file may not define all structures.  Please extend as required.
 
-  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials                          
   are licensed and made available under the terms and conditions of the BSD License         
   which accompanies this distribution.  The full text of the license may be found at        
@@ -17,16 +17,41 @@
 #ifndef _PCIEXPRESS30_H_
 #define _PCIEXPRESS30_H_
 
-#include "PciExpress21.h"
+#include <IndustryStandard/PciExpress21.h>
+
+#pragma pack(1)
 
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID    0x0019
 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1  0x1
 
+typedef union {
+  struct {
+    UINT32 PerformEqualization : 1;
+    UINT32 LinkEqualizationRequestInterruptEnable : 1;
+    UINT32 Reserved : 30;
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_LINK_CONTROL3;
+
+typedef union {
+  struct {
+    UINT16 DownstreamPortTransmitterPreset : 4;
+    UINT16 DownstreamPortReceiverPresetHint : 3;
+    UINT16 Reserved : 1;
+    UINT16 UpstreamPortTransmitterPreset : 4;
+    UINT16 UpstreamPortReceiverPresetHint : 3;
+    UINT16 Reserved2 : 1;
+  } Bits;
+  UINT16   Uint16;
+} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
+
 typedef struct {
   PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                Header;
-  UINT32                                                  LinkControl3;
+  PCI_EXPRESS_REG_LINK_CONTROL3                           LinkControl3;
   UINT32                                                  LaneErrorStatus;
-  UINT16                                                  EqualizationControl[2];
+  PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL               EqualizationControl[2];
 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
 
+#pragma pack()
+
 #endif