X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FInclude%2FLibrary%2FBaseLib.h;h=6f25f236bc3ab8a101547b29dc46c2883aee68b4;hp=0dfdd7dc91747009d1b77fa3afca61f0f4fbb2bc;hb=720d3c5fb31b6b2df535f7a281d5d9d297c5eede;hpb=7ca066f99b88aa0c5c07c92e109b5dcfe0b8a7c7 diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 0dfdd7dc91..6f25f236bc 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -2,7 +2,7 @@ Provides string functions, linked list functions, math functions, synchronization functions, and CPU architecture specific functions. -Copyright (c) 2006 - 2008, Intel Corporation +Copyright (c) 2006 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -16,11 +16,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #ifndef __BASE_LIB__ #define __BASE_LIB__ -/// -/// Definitions for SPIN_LOCK -/// -typedef volatile UINTN SPIN_LOCK; - // // Definitions for architecture specific types // @@ -93,7 +88,7 @@ typedef struct { #if defined (MDE_CPU_X64) /// -/// X64 context buffer used by SetJump() and LongJump() +/// x64 context buffer used by SetJump() and LongJump() /// typedef struct { UINT64 Rbx; @@ -178,7 +173,7 @@ StrCpy ( If Length > 0 and Destination is NULL, then ASSERT(). If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT(). If Length > 0 and Source is NULL, then ASSERT(). - If Length > 0 and Source is not aligned on a 16-bit bounadry, then ASSERT(). + If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT(). If Source and Destination overlap, then ASSERT(). If PcdMaximumUnicodeStringLength is not zero, and Source contains more than PcdMaximumUnicodeStringLength Unicode characters not including the @@ -297,9 +292,9 @@ StrCmp ( subtracted from the first mismatched Unicode character in FirstString. If Length > 0 and FirstString is NULL, then ASSERT(). - If Length > 0 and FirstString is not aligned on a 16-bit bounadary, then ASSERT(). + If Length > 0 and FirstString is not aligned on a 16-bit boundary, then ASSERT(). If Length > 0 and SecondString is NULL, then ASSERT(). - If Length > 0 and SecondString is not aligned on a 16-bit bounadary, then ASSERT(). + If Length > 0 and SecondString is not aligned on a 16-bit boundary, then ASSERT(). If PcdMaximumUnicodeStringLength is not zero, and FirstString contains more than PcdMaximumUnicodeStringLength Unicode characters not including the Null-terminator, then ASSERT(). @@ -335,9 +330,9 @@ StrnCmp ( results are undefined. If Destination is NULL, then ASSERT(). - If Destination is not aligned on a 16-bit bounadary, then ASSERT(). + If Destination is not aligned on a 16-bit boundary, then ASSERT(). If Source is NULL, then ASSERT(). - If Source is not aligned on a 16-bit bounadary, then ASSERT(). + If Source is not aligned on a 16-bit boundary, then ASSERT(). If Source and Destination overlap, then ASSERT(). If PcdMaximumUnicodeStringLength is not zero, and Destination contains more than PcdMaximumUnicodeStringLength Unicode characters not including the @@ -1220,7 +1215,7 @@ BcdToDecimal8 ( instead if calling the InitializeListHead() function to perform the equivalent operation. - @param ListHead The head note of a list to initiailize. + @param ListHead The head note of a list to initialize. **/ #define INITIALIZE_LIST_HEAD_VARIABLE(ListHead) {&(ListHead), &(ListHead)} @@ -1626,7 +1621,7 @@ LRotU32 ( @param Operand The 32-bit operand to rotate right. @param Count The number of bits to rotate right. - @return Operand >>> Count + @return Operand >> Count **/ UINT32 @@ -1815,9 +1810,9 @@ GetPowerOfTwo64 ( from little endian to big endian or vice versa. The byte swapped value is returned. - @param Value Operand A 16-bit unsigned value. + @param Value A 16-bit unsigned value. - @return The byte swapped Operand. + @return The byte swapped Value. **/ UINT16 @@ -1834,9 +1829,9 @@ SwapBytes16 ( from little endian to big endian or vice versa. The byte swapped value is returned. - @param Value Operand A 32-bit unsigned value. + @param Value A 32-bit unsigned value. - @return The byte swapped Operand. + @return The byte swapped Value. **/ UINT32 @@ -1853,9 +1848,9 @@ SwapBytes32 ( from little endian to big endian or vice versa. The byte swapped value is returned. - @param Value Operand A 64-bit unsigned value. + @param Value A 64-bit unsigned value. - @return The byte swapped Operand. + @return The byte swapped Value. **/ UINT64 @@ -1895,8 +1890,6 @@ MultU64x32 ( unsigned value Multiplier and generates a 64-bit unsigned result. This 64- bit unsigned result is returned. - If the result overflows, then ASSERT(). - @param Multiplicand A 64-bit unsigned value. @param Multiplier A 64-bit unsigned value. @@ -2309,7 +2302,7 @@ BitFieldWrite8 ( Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the result. - Performs a bitwise inclusive OR between the bit field specified by StartBit + Performs a bitwise OR between the bit field specified by StartBit and EndBit in Operand and the value specified by OrData. All other bits in Operand are preserved. The new 8-bit value is returned. @@ -2376,8 +2369,8 @@ BitFieldAnd8 ( bitwise OR, and returns the result. Performs a bitwise AND between the bit field specified by StartBit and EndBit - in Operand and the value specified by AndData, followed by a bitwise - inclusive OR with value specified by OrData. All other bits in Operand are + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are preserved. The new 8-bit value is returned. If 8-bit operations are not supported, then ASSERT(). @@ -2471,7 +2464,7 @@ BitFieldWrite16 ( Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the result. - Performs a bitwise inclusive OR between the bit field specified by StartBit + Performs a bitwise OR between the bit field specified by StartBit and EndBit in Operand and the value specified by OrData. All other bits in Operand are preserved. The new 16-bit value is returned. @@ -2538,8 +2531,8 @@ BitFieldAnd16 ( bitwise OR, and returns the result. Performs a bitwise AND between the bit field specified by StartBit and EndBit - in Operand and the value specified by AndData, followed by a bitwise - inclusive OR with value specified by OrData. All other bits in Operand are + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are preserved. The new 16-bit value is returned. If 16-bit operations are not supported, then ASSERT(). @@ -2633,7 +2626,7 @@ BitFieldWrite32 ( Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the result. - Performs a bitwise inclusive OR between the bit field specified by StartBit + Performs a bitwise OR between the bit field specified by StartBit and EndBit in Operand and the value specified by OrData. All other bits in Operand are preserved. The new 32-bit value is returned. @@ -2700,8 +2693,8 @@ BitFieldAnd32 ( bitwise OR, and returns the result. Performs a bitwise AND between the bit field specified by StartBit and EndBit - in Operand and the value specified by AndData, followed by a bitwise - inclusive OR with value specified by OrData. All other bits in Operand are + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are preserved. The new 32-bit value is returned. If 32-bit operations are not supported, then ASSERT(). @@ -2795,7 +2788,7 @@ BitFieldWrite64 ( Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the result. - Performs a bitwise inclusive OR between the bit field specified by StartBit + Performs a bitwise OR between the bit field specified by StartBit and EndBit in Operand and the value specified by OrData. All other bits in Operand are preserved. The new 64-bit value is returned. @@ -2862,8 +2855,8 @@ BitFieldAnd64 ( bitwise OR, and returns the result. Performs a bitwise AND between the bit field specified by StartBit and EndBit - in Operand and the value specified by AndData, followed by a bitwise - inclusive OR with value specified by OrData. All other bits in Operand are + in Operand and the value specified by AndData, followed by a bitwise + OR with value specified by OrData. All other bits in Operand are preserved. The new 64-bit value is returned. If 64-bit operations are not supported, then ASSERT(). @@ -2892,255 +2885,6 @@ BitFieldAndThenOr64 ( IN UINT64 OrData ); - -// -// Base Library Synchronization Functions -// - -/** - Retrieves the architecture specific spin lock alignment requirements for - optimal spin lock performance. - - This function retrieves the spin lock alignment requirements for optimal - performance on a given CPU architecture. The spin lock alignment must be a - power of two and is returned by this function. If there are no alignment - requirements, then 1 must be returned. The spin lock synchronization - functions must function correctly if the spin lock size and alignment values - returned by this function are not used at all. These values are hints to the - consumers of the spin lock synchronization functions to obtain optimal spin - lock performance. - - @return The architecture specific spin lock alignment. - -**/ -UINTN -EFIAPI -GetSpinLockProperties ( - VOID - ); - - -/** - Initializes a spin lock to the released state and returns the spin lock. - - This function initializes the spin lock specified by SpinLock to the released - state, and returns SpinLock. Optimal performance can be achieved by calling - GetSpinLockProperties() to determine the size and alignment requirements for - SpinLock. - - If SpinLock is NULL, then ASSERT(). - - @param SpinLock A pointer to the spin lock to initialize to the released - state. - - @return SpinLock in release state. - -**/ -SPIN_LOCK * -EFIAPI -InitializeSpinLock ( - OUT SPIN_LOCK *SpinLock - ); - - -/** - Waits until a spin lock can be placed in the acquired state. - - This function checks the state of the spin lock specified by SpinLock. If - SpinLock is in the released state, then this function places SpinLock in the - acquired state and returns SpinLock. Otherwise, this function waits - indefinitely for the spin lock to be released, and then places it in the - acquired state and returns SpinLock. All state transitions of SpinLock must - be performed using MP safe mechanisms. - - If SpinLock is NULL, then ASSERT(). - If SpinLock was not initialized with InitializeSpinLock(), then ASSERT(). - If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in - PcdSpinLockTimeout microseconds, then ASSERT(). - - @param SpinLock A pointer to the spin lock to place in the acquired state. - - @return SpinLock acquired lock. - -**/ -SPIN_LOCK * -EFIAPI -AcquireSpinLock ( - IN OUT SPIN_LOCK *SpinLock - ); - - -/** - Attempts to place a spin lock in the acquired state. - - This function checks the state of the spin lock specified by SpinLock. If - SpinLock is in the released state, then this function places SpinLock in the - acquired state and returns TRUE. Otherwise, FALSE is returned. All state - transitions of SpinLock must be performed using MP safe mechanisms. - - If SpinLock is NULL, then ASSERT(). - If SpinLock was not initialized with InitializeSpinLock(), then ASSERT(). - - @param SpinLock A pointer to the spin lock to place in the acquired state. - - @retval TRUE SpinLock was placed in the acquired state. - @retval FALSE SpinLock could not be acquired. - -**/ -BOOLEAN -EFIAPI -AcquireSpinLockOrFail ( - IN OUT SPIN_LOCK *SpinLock - ); - - -/** - Releases a spin lock. - - This function places the spin lock specified by SpinLock in the release state - and returns SpinLock. - - If SpinLock is NULL, then ASSERT(). - If SpinLock was not initialized with InitializeSpinLock(), then ASSERT(). - - @param SpinLock A pointer to the spin lock to release. - - @return SpinLock released lock. - -**/ -SPIN_LOCK * -EFIAPI -ReleaseSpinLock ( - IN OUT SPIN_LOCK *SpinLock - ); - - -/** - Performs an atomic increment of an 32-bit unsigned integer. - - Performs an atomic increment of the 32-bit unsigned integer specified by - Value and returns the incremented value. The increment operation must be - performed using MP safe mechanisms. The state of the return value is not - guaranteed to be MP safe. - - If Value is NULL, then ASSERT(). - - @param Value A pointer to the 32-bit value to increment. - - @return The incremented value. - -**/ -UINT32 -EFIAPI -InterlockedIncrement ( - IN UINT32 *Value - ); - - -/** - Performs an atomic decrement of an 32-bit unsigned integer. - - Performs an atomic decrement of the 32-bit unsigned integer specified by - Value and returns the decremented value. The decrement operation must be - performed using MP safe mechanisms. The state of the return value is not - guaranteed to be MP safe. - - If Value is NULL, then ASSERT(). - - @param Value A pointer to the 32-bit value to decrement. - - @return The decremented value. - -**/ -UINT32 -EFIAPI -InterlockedDecrement ( - IN UINT32 *Value - ); - - -/** - Performs an atomic compare exchange operation on a 32-bit unsigned integer. - - Performs an atomic compare exchange operation on the 32-bit unsigned integer - specified by Value. If Value is equal to CompareValue, then Value is set to - ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue, - then Value is returned. The compare exchange operation must be performed using - MP safe mechanisms. - - If Value is NULL, then ASSERT(). - - @param Value A pointer to the 32-bit value for the compare exchange - operation. - @param CompareValue 32-bit value used in compare operation. - @param ExchangeValue 32-bit value used in exchange operation. - - @return The original *Value before exchange. - -**/ -UINT32 -EFIAPI -InterlockedCompareExchange32 ( - IN OUT UINT32 *Value, - IN UINT32 CompareValue, - IN UINT32 ExchangeValue - ); - - -/** - Performs an atomic compare exchange operation on a 64-bit unsigned integer. - - Performs an atomic compare exchange operation on the 64-bit unsigned integer specified - by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and - CompareValue is returned. If Value is not equal to CompareValue, then Value is returned. - The compare exchange operation must be performed using MP safe mechanisms. - - If Value is NULL, then ASSERT(). - - @param Value A pointer to the 64-bit value for the compare exchange - operation. - @param CompareValue 64-bit value used in compare operation. - @param ExchangeValue 64-bit value used in exchange operation. - - @return The original *Value before exchange. - -**/ -UINT64 -EFIAPI -InterlockedCompareExchange64 ( - IN OUT UINT64 *Value, - IN UINT64 CompareValue, - IN UINT64 ExchangeValue - ); - - -/** - Performs an atomic compare exchange operation on a pointer value. - - Performs an atomic compare exchange operation on the pointer value specified - by Value. If Value is equal to CompareValue, then Value is set to - ExchangeValue and CompareValue is returned. If Value is not equal to - CompareValue, then Value is returned. The compare exchange operation must be - performed using MP safe mechanisms. - - If Value is NULL, then ASSERT(). - - @param Value A pointer to the pointer value for the compare exchange - operation. - @param CompareValue Pointer value used in compare operation. - @param ExchangeValue Pointer value used in exchange operation. - - @return The original *Value before exchange. -**/ -VOID * -EFIAPI -InterlockedCompareExchangePointer ( - IN OUT VOID **Value, - IN VOID *CompareValue, - IN VOID *ExchangeValue - ); - - // // Base Library Checksum Functions // @@ -3362,9 +3106,17 @@ CalculateCheckSum64 ( ); -/// -/// Base Library CPU Functions -/// +// +// Base Library CPU Functions +// + +/** + Function entry point used when a stack switch is requested with SwitchStack() + + @param Context1 Context1 parameter passed into SwitchStack(). + @param Context2 Context2 parameter passed into SwitchStack(). + +**/ typedef VOID (EFIAPI *SWITCH_STACK_ENTRY_POINT)( @@ -3608,6 +3360,7 @@ EFIAPI CpuDeadLoop ( VOID ); + #if defined (MDE_CPU_IPF) /** @@ -3737,6 +3490,8 @@ AsmWritePsr ( /** Reads the current value of 64-bit Kernel Register #0 (KR0). + + Reads and returns the current value of KR0. This function is only available on IPF. @return The current value of KR0. @@ -3751,6 +3506,8 @@ AsmReadKr0 ( /** Reads the current value of 64-bit Kernel Register #1 (KR1). + + Reads and returns the current value of KR1. This function is only available on IPF. @return The current value of KR1. @@ -3765,6 +3522,8 @@ AsmReadKr1 ( /** Reads the current value of 64-bit Kernel Register #2 (KR2). + + Reads and returns the current value of KR2. This function is only available on IPF. @return The current value of KR2. @@ -3779,6 +3538,8 @@ AsmReadKr2 ( /** Reads the current value of 64-bit Kernel Register #3 (KR3). + + Reads and returns the current value of KR3. This function is only available on IPF. @return The current value of KR3. @@ -3793,8 +3554,10 @@ AsmReadKr3 ( /** Reads the current value of 64-bit Kernel Register #4 (KR4). - This function is only available on IPF. + Reads and returns the current value of KR4. + This function is only available on IPF. + @return The current value of KR4. **/ @@ -3807,6 +3570,8 @@ AsmReadKr4 ( /** Reads the current value of 64-bit Kernel Register #5 (KR5). + + Reads and returns the current value of KR5. This function is only available on IPF. @return The current value of KR5. @@ -3821,6 +3586,8 @@ AsmReadKr5 ( /** Reads the current value of 64-bit Kernel Register #6 (KR6). + + Reads and returns the current value of KR6. This function is only available on IPF. @return The current value of KR6. @@ -3835,6 +3602,8 @@ AsmReadKr6 ( /** Reads the current value of 64-bit Kernel Register #7 (KR7). + + Reads and returns the current value of KR7. This function is only available on IPF. @return The current value of KR7. @@ -3849,7 +3618,9 @@ AsmReadKr7 ( /** Write the current value of 64-bit Kernel Register #0 (KR0). - This function is only available on IPF. + + Writes the current value of KR0. The 64-bit value written to + the KR0 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR0. @@ -3865,7 +3636,9 @@ AsmWriteKr0 ( /** Write the current value of 64-bit Kernel Register #1 (KR1). - This function is only available on IPF. + + Writes the current value of KR1. The 64-bit value written to + the KR1 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR1. @@ -3881,7 +3654,9 @@ AsmWriteKr1 ( /** Write the current value of 64-bit Kernel Register #2 (KR2). - This function is only available on IPF. + + Writes the current value of KR2. The 64-bit value written to + the KR2 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR2. @@ -3897,7 +3672,9 @@ AsmWriteKr2 ( /** Write the current value of 64-bit Kernel Register #3 (KR3). - This function is only available on IPF. + + Writes the current value of KR3. The 64-bit value written to + the KR3 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR3. @@ -3913,7 +3690,9 @@ AsmWriteKr3 ( /** Write the current value of 64-bit Kernel Register #4 (KR4). - This function is only available on IPF. + + Writes the current value of KR4. The 64-bit value written to + the KR4 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR4. @@ -3929,7 +3708,9 @@ AsmWriteKr4 ( /** Write the current value of 64-bit Kernel Register #5 (KR5). - This function is only available on IPF. + + Writes the current value of KR5. The 64-bit value written to + the KR5 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR5. @@ -3945,7 +3726,9 @@ AsmWriteKr5 ( /** Write the current value of 64-bit Kernel Register #6 (KR6). - This function is only available on IPF. + + Writes the current value of KR6. The 64-bit value written to + the KR6 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR6. @@ -3961,7 +3744,9 @@ AsmWriteKr6 ( /** Write the current value of 64-bit Kernel Register #7 (KR7). - This function is only available on IPF. + + Writes the current value of KR7. The 64-bit value written to + the KR7 is returned. This function is only available on IPF. @param Value The 64-bit value to write to KR7. @@ -3977,6 +3762,8 @@ AsmWriteKr7 ( /** Reads the current value of Interval Timer Counter Register (ITC). + + Reads and returns the current value of ITC. This function is only available on IPF. @return The current value of ITC. @@ -3991,6 +3778,8 @@ AsmReadItc ( /** Reads the current value of Interval Timer Vector Register (ITV). + + Reads and returns the current value of ITV. This function is only available on IPF. @return The current value of ITV. @@ -4005,6 +3794,8 @@ AsmReadItv ( /** Reads the current value of Interval Timer Match Register (ITM). + + Reads and returns the current value of ITM. This function is only available on IPF. @return The current value of ITM. @@ -4018,6 +3809,8 @@ AsmReadItm ( /** Writes the current value of 64-bit Interval Timer Counter Register (ITC). + + Writes the current value of ITC. The 64-bit value written to the ITC is returned. This function is only available on IPF. @param Value The 64-bit value to write to ITC. @@ -4034,6 +3827,8 @@ AsmWriteItc ( /** Writes the current value of 64-bit Interval Timer Match Register (ITM). + + Writes the current value of ITM. The 64-bit value written to the ITM is returned. This function is only available on IPF. @param Value The 64-bit value to write to ITM. @@ -4050,6 +3845,8 @@ AsmWriteItm ( /** Writes the current value of 64-bit Interval Timer Vector Register (ITV). + + Writes the current value of ITV. The 64-bit value written to the ITV is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4070,7 +3867,8 @@ AsmWriteItv ( /** Reads the current value of Default Control Register (DCR). - This function is only available on IPF. + + Reads and returns the current value of DCR. This function is only available on IPF. @return The current value of DCR. @@ -4084,7 +3882,8 @@ AsmReadDcr ( /** Reads the current value of Interruption Vector Address Register (IVA). - This function is only available on IPF. + + Reads and returns the current value of IVA. This function is only available on IPF. @return The current value of IVA. **/ @@ -4097,7 +3896,8 @@ AsmReadIva ( /** Reads the current value of Page Table Address Register (PTA). - This function is only available on IPF. + + Reads and returns the current value of PTA. This function is only available on IPF. @return The current value of PTA. @@ -4111,6 +3911,8 @@ AsmReadPta ( /** Writes the current value of 64-bit Default Control Register (DCR). + + Writes the current value of DCR. The 64-bit value written to the DCR is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4131,6 +3933,8 @@ AsmWriteDcr ( /** Writes the current value of 64-bit Interruption Vector Address Register (IVA). + + Writes the current value of IVA. The 64-bit value written to the IVA is returned. The size of vector table is 32 K bytes and is 32 K bytes aligned the low 15 bits of Value is ignored when written. This function is only available on IPF. @@ -4149,6 +3953,8 @@ AsmWriteIva ( /** Writes the current value of 64-bit Page Table Address Register (PTA). + + Writes the current value of PTA. The 64-bit value written to the PTA is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4168,7 +3974,8 @@ AsmWritePta ( /** Reads the current value of Local Interrupt ID Register (LID). - This function is only available on IPF. + + Reads and returns the current value of LID. This function is only available on IPF. @return The current value of LID. @@ -4182,7 +3989,8 @@ AsmReadLid ( /** Reads the current value of External Interrupt Vector Register (IVR). - This function is only available on IPF. + + Reads and returns the current value of IVR. This function is only available on IPF. @return The current value of IVR. @@ -4196,7 +4004,8 @@ AsmReadIvr ( /** Reads the current value of Task Priority Register (TPR). - This function is only available on IPF. + + Reads and returns the current value of TPR. This function is only available on IPF. @return The current value of TPR. @@ -4210,7 +4019,8 @@ AsmReadTpr ( /** Reads the current value of External Interrupt Request Register #0 (IRR0). - This function is only available on IPF. + + Reads and returns the current value of IRR0. This function is only available on IPF. @return The current value of IRR0. @@ -4224,7 +4034,8 @@ AsmReadIrr0 ( /** Reads the current value of External Interrupt Request Register #1 (IRR1). - This function is only available on IPF. + + Reads and returns the current value of IRR1. This function is only available on IPF. @return The current value of IRR1. @@ -4238,7 +4049,8 @@ AsmReadIrr1 ( /** Reads the current value of External Interrupt Request Register #2 (IRR2). - This function is only available on IPF. + + Reads and returns the current value of IRR2. This function is only available on IPF. @return The current value of IRR2. @@ -4252,7 +4064,8 @@ AsmReadIrr2 ( /** Reads the current value of External Interrupt Request Register #3 (IRR3). - This function is only available on IPF. + + Reads and returns the current value of IRR3. This function is only available on IPF. @return The current value of IRR3. @@ -4266,7 +4079,8 @@ AsmReadIrr3 ( /** Reads the current value of Performance Monitor Vector Register (PMV). - This function is only available on IPF. + + Reads and returns the current value of PMV. This function is only available on IPF. @return The current value of PMV. @@ -4280,7 +4094,8 @@ AsmReadPmv ( /** Reads the current value of Corrected Machine Check Vector Register (CMCV). - This function is only available on IPF. + + Reads and returns the current value of CMCV. This function is only available on IPF. @return The current value of CMCV. @@ -4294,7 +4109,8 @@ AsmReadCmcv ( /** Reads the current value of Local Redirection Register #0 (LRR0). - This function is only available on IPF. + + Reads and returns the current value of LRR0. This function is only available on IPF. @return The current value of LRR0. @@ -4308,7 +4124,8 @@ AsmReadLrr0 ( /** Reads the current value of Local Redirection Register #1 (LRR1). - This function is only available on IPF. + + Reads and returns the current value of LRR1. This function is only available on IPF. @return The current value of LRR1. @@ -4322,6 +4139,8 @@ AsmReadLrr1 ( /** Writes the current value of 64-bit Page Local Interrupt ID Register (LID). + + Writes the current value of LID. The 64-bit value written to the LID is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of LID must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4342,6 +4161,8 @@ AsmWriteLid ( /** Writes the current value of 64-bit Task Priority Register (TPR). + + Writes the current value of TPR. The 64-bit value written to the TPR is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4362,6 +4183,7 @@ AsmWriteTpr ( /** Performs a write operation on End OF External Interrupt Register (EOI). + Writes a value of 0 to the EOI Register. This function is only available on IPF. **/ @@ -4374,6 +4196,8 @@ AsmWriteEoi ( /** Writes the current value of 64-bit Performance Monitor Vector Register (PMV). + + Writes the current value of PMV. The 64-bit value written to the PMV is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4394,6 +4218,8 @@ AsmWritePmv ( /** Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV). + + Writes the current value of CMCV. The 64-bit value written to the CMCV is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4414,6 +4240,8 @@ AsmWriteCmcv ( /** Writes the current value of 64-bit Local Redirection Register #0 (LRR0). + + Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must set up @@ -4434,6 +4262,8 @@ AsmWriteLrr0 ( /** Writes the current value of 64-bit Local Redirection Register #1 (LRR1). + + Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned. No parameter checking is performed on Value. All bits of Value corresponding to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur. The caller must either guarantee that Value is valid, or the caller must @@ -4517,8 +4347,8 @@ AsmReadDbr ( @param Index The 8-bit Performance Monitor Configuration Register index to read. - @return The current value of Performance Monitor Configuration Register - specified by Index. + @return The current value of Performance Monitor Configuration Register + specified by Index. **/ UINT64 @@ -4813,6 +4643,50 @@ AsmReadApplicationRegister ( ); +/** + Reads the current value of a Machine Specific Register (MSR). + + Reads and returns the current value of the Machine Specific Register specified by Index. No + parameter checking is performed on Index, and if the Index value is beyond the implemented MSR + register range, a Reserved Register/Field fault may occur. The caller must either guarantee that + Index is valid, or the caller must set up fault handlers to catch the faults. This function is + only available on IPF. + + @param Index The 8-bit Machine Specific Register index to read. + + @return The current value of the Machine Specific Register specified by Index. + +**/ +UINT64 +EFIAPI +AsmReadMsr ( + IN UINT8 Index + ); + + +/** + Writes the current value of a Machine Specific Register (MSR). + + Writes Value to the Machine Specific Register specified by Index. Value is returned. No + parameter checking is performed on Index, and if the Index value is beyond the implemented MSR + register range, a Reserved Register/Field fault may occur. The caller must either guarantee that + Index is valid, or the caller must set up fault handlers to catch the faults. This function is + only available on IPF. + + @param Index The 8-bit Machine Specific Register index to write. + @param Value The 64-bit value to write to the Machine Specific Register. + + @return The 64-bit value to write to the Machine Specific Register. + +**/ +UINT64 +EFIAPI +AsmWriteMsr ( + IN UINT8 Index, + IN UINT64 Value + ); + + /** Determines if the CPU is currently executing in virtual, physical, or mixed mode. @@ -4875,30 +4749,30 @@ AsmPalCall ( IN UINT64 Arg3, IN UINT64 Arg4 ); +#endif - -#elif defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) /// -/// IA32 and X64 Specific Functions +/// IA32 and x64 Specific Functions /// Byte packed structure for 16-bit Real Mode EFLAGS /// typedef union { struct { - UINT32 CF:1; /// Carry Flag - UINT32 Reserved_0:1; /// Reserved - UINT32 PF:1; /// Parity Flag - UINT32 Reserved_1:1; /// Reserved - UINT32 AF:1; /// Auxiliary Carry Flag - UINT32 Reserved_2:1; /// Reserved - UINT32 ZF:1; /// Zero Flag - UINT32 SF:1; /// Sign Flag - UINT32 TF:1; /// Trap Flag - UINT32 IF:1; /// Interrupt Enable Flag - UINT32 DF:1; /// Direction Flag - UINT32 OF:1; /// Overflow Flag - UINT32 IOPL:2; /// I/O Privilege Level - UINT32 NT:1; /// Nested Task - UINT32 Reserved_3:1; /// Reserved + UINT32 CF:1; ///< Carry Flag + UINT32 Reserved_0:1; ///< Reserved + UINT32 PF:1; ///< Parity Flag + UINT32 Reserved_1:1; ///< Reserved + UINT32 AF:1; ///< Auxiliary Carry Flag + UINT32 Reserved_2:1; ///< Reserved + UINT32 ZF:1; ///< Zero Flag + UINT32 SF:1; ///< Sign Flag + UINT32 TF:1; ///< Trap Flag + UINT32 IF:1; ///< Interrupt Enable Flag + UINT32 DF:1; ///< Direction Flag + UINT32 OF:1; ///< Overflow Flag + UINT32 IOPL:2; ///< I/O Privilege Level + UINT32 NT:1; ///< Nested Task + UINT32 Reserved_3:1; ///< Reserved } Bits; UINT16 Uint16; } IA32_FLAGS16; @@ -4906,32 +4780,32 @@ typedef union { /// /// Byte packed structure for EFLAGS/RFLAGS /// 32-bits on IA-32 -/// 64-bits on X64. The upper 32-bits on X64 are reserved +/// 64-bits on x64. The upper 32-bits on x64 are reserved /// typedef union { struct { - UINT32 CF:1; /// Carry Flag - UINT32 Reserved_0:1; /// Reserved - UINT32 PF:1; /// Parity Flag - UINT32 Reserved_1:1; /// Reserved - UINT32 AF:1; /// Auxiliary Carry Flag - UINT32 Reserved_2:1; /// Reserved - UINT32 ZF:1; /// Zero Flag - UINT32 SF:1; /// Sign Flag - UINT32 TF:1; /// Trap Flag - UINT32 IF:1; /// Interrupt Enable Flag - UINT32 DF:1; /// Direction Flag - UINT32 OF:1; /// Overflow Flag - UINT32 IOPL:2; /// I/O Privilege Level - UINT32 NT:1; /// Nested Task - UINT32 Reserved_3:1; /// Reserved - UINT32 RF:1; /// Resume Flag - UINT32 VM:1; /// Virtual 8086 Mode - UINT32 AC:1; /// Alignment Check - UINT32 VIF:1; /// Virtual Interrupt Flag - UINT32 VIP:1; /// Virtual Interrupt Pending - UINT32 ID:1; /// ID Flag - UINT32 Reserved_4:10; /// Reserved + UINT32 CF:1; ///< Carry Flag + UINT32 Reserved_0:1; ///< Reserved + UINT32 PF:1; ///< Parity Flag + UINT32 Reserved_1:1; ///< Reserved + UINT32 AF:1; ///< Auxiliary Carry Flag + UINT32 Reserved_2:1; ///< Reserved + UINT32 ZF:1; ///< Zero Flag + UINT32 SF:1; ///< Sign Flag + UINT32 TF:1; ///< Trap Flag + UINT32 IF:1; ///< Interrupt Enable Flag + UINT32 DF:1; ///< Direction Flag + UINT32 OF:1; ///< Overflow Flag + UINT32 IOPL:2; ///< I/O Privilege Level + UINT32 NT:1; ///< Nested Task + UINT32 Reserved_3:1; ///< Reserved + UINT32 RF:1; ///< Resume Flag + UINT32 VM:1; ///< Virtual 8086 Mode + UINT32 AC:1; ///< Alignment Check + UINT32 VIF:1; ///< Virtual Interrupt Flag + UINT32 VIP:1; ///< Virtual Interrupt Pending + UINT32 ID:1; ///< ID Flag + UINT32 Reserved_4:10; ///< Reserved } Bits; UINTN UintN; } IA32_EFLAGS32; @@ -4939,24 +4813,24 @@ typedef union { /// /// Byte packed structure for Control Register 0 (CR0) /// 32-bits on IA-32 -/// 64-bits on X64. The upper 32-bits on X64 are reserved +/// 64-bits on x64. The upper 32-bits on x64 are reserved /// typedef union { struct { - UINT32 PE:1; /// Protection Enable - UINT32 MP:1; /// Monitor Coprocessor - UINT32 EM:1; /// Emulation - UINT32 TS:1; /// Task Switched - UINT32 ET:1; /// Extension Type - UINT32 NE:1; /// Numeric Error - UINT32 Reserved_0:10; /// Reserved - UINT32 WP:1; /// Write Protect - UINT32 Reserved_1:1; /// Reserved - UINT32 AM:1; /// Alignment Mask - UINT32 Reserved_2:10; /// Reserved - UINT32 NW:1; /// Mot Write-through - UINT32 CD:1; /// Cache Disable - UINT32 PG:1; /// Paging + UINT32 PE:1; ///< Protection Enable + UINT32 MP:1; ///< Monitor Coprocessor + UINT32 EM:1; ///< Emulation + UINT32 TS:1; ///< Task Switched + UINT32 ET:1; ///< Extension Type + UINT32 NE:1; ///< Numeric Error + UINT32 Reserved_0:10; ///< Reserved + UINT32 WP:1; ///< Write Protect + UINT32 Reserved_1:1; ///< Reserved + UINT32 AM:1; ///< Alignment Mask + UINT32 Reserved_2:10; ///< Reserved + UINT32 NW:1; ///< Mot Write-through + UINT32 CD:1; ///< Cache Disable + UINT32 PG:1; ///< Paging } Bits; UINTN UintN; } IA32_CR0; @@ -4964,28 +4838,28 @@ typedef union { /// /// Byte packed structure for Control Register 4 (CR4) /// 32-bits on IA-32 -/// 64-bits on X64. The upper 32-bits on X64 are reserved +/// 64-bits on x64. The upper 32-bits on x64 are reserved /// typedef union { struct { - UINT32 VME:1; /// Virtual-8086 Mode Extensions - UINT32 PVI:1; /// Protected-Mode Virtual Interrupts - UINT32 TSD:1; /// Time Stamp Disable - UINT32 DE:1; /// Debugging Extensions - UINT32 PSE:1; /// Page Size Extensions - UINT32 PAE:1; /// Physical Address Extension - UINT32 MCE:1; /// Machine Check Enable - UINT32 PGE:1; /// Page Global Enable - UINT32 PCE:1; /// Performance Monitoring Counter - /// Enable - UINT32 OSFXSR:1; /// Operating System Support for - /// FXSAVE and FXRSTOR instructions - UINT32 OSXMMEXCPT:1; /// Operating System Support for - /// Unmasked SIMD Floating Point - /// Exceptions - UINT32 Reserved_0:2; /// Reserved - UINT32 VMXE:1; /// VMX Enable - UINT32 Reserved_1:18; /// Reseved + UINT32 VME:1; ///< Virtual-8086 Mode Extensions + UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts + UINT32 TSD:1; ///< Time Stamp Disable + UINT32 DE:1; ///< Debugging Extensions + UINT32 PSE:1; ///< Page Size Extensions + UINT32 PAE:1; ///< Physical Address Extension + UINT32 MCE:1; ///< Machine Check Enable + UINT32 PGE:1; ///< Page Global Enable + UINT32 PCE:1; ///< Performance Monitoring Counter + ///< Enable + UINT32 OSFXSR:1; ///< Operating System Support for + ///< FXSAVE and FXRSTOR instructions + UINT32 OSXMMEXCPT:1; ///< Operating System Support for + ///< Unmasked SIMD Floating Point + ///< Exceptions + UINT32 Reserved_0:2; ///< Reserved + UINT32 VMXE:1; ///< VMX Enable + UINT32 Reserved_1:18; ///< Reserved } Bits; UINTN UintN; } IA32_CR4; @@ -5006,18 +4880,18 @@ typedef struct { #define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E #define IA32_IDT_GATE_TYPE_TRAP_32 0x8F + +#if defined (MDE_CPU_IA32) /// -/// Byte packed structure for an Interrupt Gate Descriptor +/// Byte packed structure for an IA32 Interrupt Gate Descriptor /// -#if defined (MDE_CPU_IA32) - typedef union { struct { - UINT32 OffsetLow:16; // Offset bits 15..0 - UINT32 Selector:16; // Selector - UINT32 Reserved_0:8; // Reserved - UINT32 GateType:8; // Gate Type. See #defines above - UINT32 OffsetHigh:16; // Offset bits 31..16 + UINT32 OffsetLow:16; ///< Offset bits 15..0 + UINT32 Selector:16; ///< Selector + UINT32 Reserved_0:8; ///< Reserved + UINT32 GateType:8; ///< Gate Type. See #defines above + UINT32 OffsetHigh:16; ///< Offset bits 31..16 } Bits; UINT64 Uint64; } IA32_IDT_GATE_DESCRIPTOR; @@ -5025,19 +4899,23 @@ typedef union { #endif #if defined (MDE_CPU_X64) - +/// +/// Byte packed structure for an x64 Interrupt Gate Descriptor +/// typedef union { struct { - UINT32 OffsetLow:16; // Offset bits 15..0 - UINT32 Selector:16; // Selector - UINT32 Reserved_0:8; // Reserved - UINT32 GateType:8; // Gate Type. See #defines above - UINT32 OffsetHigh:16; // Offset bits 31..16 - UINT32 OffsetUpper:32; // Offset bits 63..32 - UINT32 Reserved_1:32; // Reserved + UINT32 OffsetLow:16; ///< Offset bits 15..0 + UINT32 Selector:16; ///< Selector + UINT32 Reserved_0:8; ///< Reserved + UINT32 GateType:8; ///< Gate Type. See #defines above + UINT32 OffsetHigh:16; ///< Offset bits 31..16 + UINT32 OffsetUpper:32; ///< Offset bits 63..32 + UINT32 Reserved_1:32; ///< Reserved } Bits; - UINT64 Uint64; - UINT64 Uint64_1; + struct { + UINT64 Uint64; + UINT64 Uint64_1; + } Uint128; } IA32_IDT_GATE_DESCRIPTOR; #endif @@ -5138,7 +5016,7 @@ typedef struct { If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx. If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx. If Edx is not NULL, then the value of EDX after CPUID is returned in Edx. - This function is only available on IA-32 and X64. + This function is only available on IA-32 and x64. @param Index The 32-bit value to load into EAX prior to invoking the CPUID instruction. @@ -5151,7 +5029,7 @@ typedef struct { @param Edx Pointer to the 32-bit EDX value returned by the CPUID instruction. This is an optional parameter that may be NULL. - @return Index + @return Index. **/ UINT32 @@ -5194,7 +5072,7 @@ AsmCpuid ( instruction. This is an optional parameter that may be NULL. - @return Index + @return Index. **/ UINT32 @@ -5244,7 +5122,7 @@ AsmEnableCache ( No parameter checking is performed on Index, and some Index values may cause CPU exceptions. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function - is only available on IA-32 and X64. + is only available on IA-32 and x64. @param Index The 32-bit MSR index to read. @@ -5267,7 +5145,7 @@ AsmReadMsr32 ( the MSR is returned. No parameter checking is performed on Index or Value, and some of these may cause CPU exceptions. The caller must either guarantee that Index and Value are valid, or the caller must establish proper exception - handlers. This function is only available on IA-32 and X64. + handlers. This function is only available on IA-32 and x64. @param Index The 32-bit MSR index to write. @param Value The 32-bit value to write to the MSR. @@ -5284,17 +5162,17 @@ AsmWriteMsr32 ( /** - Reads a 64-bit MSR, performs a bitwise inclusive OR on the lower 32-bits, and + Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and writes the result back to the 64-bit MSR. - Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR + Reads the 64-bit MSR specified by Index, performs a bitwise OR between the lower 32-bits of the read result and the value specified by OrData, and writes the result to the 64-bit MSR specified by Index. The lower 32-bits of the value written to the MSR is returned. No parameter checking is performed on Index or OrData, and some of these may cause CPU exceptions. The caller must either guarantee that Index and OrData are valid, or the caller must establish proper exception handlers. This function is only available on - IA-32 and X64. + IA-32 and x64. @param Index The 32-bit MSR index to write. @param OrData The value to OR with the read value from the MSR. @@ -5321,7 +5199,7 @@ AsmMsrOr32 ( on Index or AndData, and some of these may cause CPU exceptions. The caller must either guarantee that Index and AndData are valid, or the caller must establish proper exception handlers. This function is only available on IA-32 - and X64. + and x64. @param Index The 32-bit MSR index to write. @param AndData The value to AND with the read value from the MSR. @@ -5338,19 +5216,19 @@ AsmMsrAnd32 ( /** - Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive OR + Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR on the lower 32-bits, and writes the result back to the 64-bit MSR. Reads the 64-bit MSR specified by Index, performs a bitwise AND between the lower 32-bits of the read result and the value specified by AndData - preserving the upper 32-bits, performs a bitwise inclusive OR between the + preserving the upper 32-bits, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 64-bit MSR specified by Address. The lower 32-bits of the value written to the MSR is returned. No parameter checking is performed on Index, AndData, or OrData, and some of these may cause CPU exceptions. The caller must either guarantee that Index, AndData, and OrData are valid, or the caller must establish proper exception handlers. This function is only - available on IA-32 and X64. + available on IA-32 and x64. @param Index The 32-bit MSR index to write. @param AndData The value to AND with the read value from the MSR. @@ -5375,7 +5253,7 @@ AsmMsrAndThenOr32 ( specified by the StartBit and the EndBit. The value of the bit field is returned. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function is only - available on IA-32 and X64. + available on IA-32 and x64. If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). @@ -5402,13 +5280,12 @@ AsmMsrBitFieldRead32 ( /** Writes a bit field to an MSR. - Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit + Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit field is specified by the StartBit and the EndBit. All other bits in the destination MSR are preserved. The lower 32-bits of the MSR written is - returned. Extra left bits in Value are stripped. The caller must either - guarantee that Index and the data written is valid, or the caller must set up - exception handlers to catch the exceptions. This function is only available - on IA-32 and X64. + returned. The caller must either guarantee that Index and the data written + is valid, or the caller must set up exception handlers to catch the exceptions. + This function is only available on IA-32 and x64. If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). @@ -5438,13 +5315,13 @@ AsmMsrBitFieldWrite32 ( Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the result back to the bit field in the 64-bit MSR. - Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR + Reads the 64-bit MSR specified by Index, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 64-bit MSR specified by Index. The lower 32-bits of the value written to the MSR are returned. Extra left bits in OrData are stripped. The caller must either guarantee that Index and the data written is valid, or the caller must set up exception handlers to catch the exceptions. This - function is only available on IA-32 and X64. + function is only available on IA-32 and x64. If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). @@ -5480,7 +5357,7 @@ AsmMsrBitFieldOr32 ( MSR are returned. Extra left bits in AndData are stripped. The caller must either guarantee that Index and the data written is valid, or the caller must set up exception handlers to catch the exceptions. This function is only - available on IA-32 and X64. + available on IA-32 and x64. If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). @@ -5508,17 +5385,17 @@ AsmMsrBitFieldAnd32 ( /** Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a - bitwise inclusive OR, and writes the result back to the bit field in the + bitwise OR, and writes the result back to the bit field in the 64-bit MSR. Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by a - bitwise inclusive OR between the read result and the value specified by + bitwise OR between the read result and the value specified by AndData, and writes the result to the 64-bit MSR specified by Index. The lower 32-bits of the value written to the MSR are returned. Extra left bits in both AndData and OrData are stripped. The caller must either guarantee that Index and the data written is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available on IA-32 - and X64. + and x64. If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). @@ -5553,7 +5430,7 @@ AsmMsrBitFieldAndThenOr32 ( performed on Index, and some Index values may cause CPU exceptions. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available - on IA-32 and X64. + on IA-32 and x64. @param Index The 32-bit MSR index to read. @@ -5576,7 +5453,7 @@ AsmReadMsr64 ( performed on Index or Value, and some of these may cause CPU exceptions. The caller must either guarantee that Index and Value are valid, or the caller must establish proper exception handlers. This function is only available on - IA-32 and X64. + IA-32 and x64. @param Index The 32-bit MSR index to write. @param Value The 64-bit value to write to the MSR. @@ -5593,16 +5470,16 @@ AsmWriteMsr64 ( /** - Reads a 64-bit MSR, performs a bitwise inclusive OR, and writes the result + Reads a 64-bit MSR, performs a bitwise OR, and writes the result back to the 64-bit MSR. - Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR + Reads the 64-bit MSR specified by Index, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 64-bit MSR specified by Index. The value written to the MSR is returned. No parameter checking is performed on Index or OrData, and some of these may cause CPU exceptions. The caller must either guarantee that Index and OrData are valid, or the caller must establish proper exception handlers. - This function is only available on IA-32 and X64. + This function is only available on IA-32 and x64. @param Index The 32-bit MSR index to write. @param OrData The value to OR with the read value from the MSR. @@ -5628,7 +5505,7 @@ AsmMsrOr64 ( parameter checking is performed on Index or OrData, and some of these may cause CPU exceptions. The caller must either guarantee that Index and OrData are valid, or the caller must establish proper exception handlers. This - function is only available on IA-32 and X64. + function is only available on IA-32 and x64. @param Index The 32-bit MSR index to write. @param AndData The value to AND with the read value from the MSR. @@ -5645,18 +5522,18 @@ AsmMsrAnd64 ( /** - Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise inclusive + Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR, and writes the result back to the 64-bit MSR. Reads the 64-bit MSR specified by Index, performs a bitwise AND between read - result and the value specified by AndData, performs a bitwise inclusive OR + result and the value specified by AndData, performs a bitwise OR between the result of the AND operation and the value specified by OrData, and writes the result to the 64-bit MSR specified by Index. The value written to the MSR is returned. No parameter checking is performed on Index, AndData, or OrData, and some of these may cause CPU exceptions. The caller must either guarantee that Index, AndData, and OrData are valid, or the caller must establish proper exception handlers. This function is only available on IA-32 - and X64. + and x64. @param Index The 32-bit MSR index to write. @param AndData The value to AND with the read value from the MSR. @@ -5681,7 +5558,7 @@ AsmMsrAndThenOr64 ( StartBit and the EndBit. The value of the bit field is returned. The caller must either guarantee that Index is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available - on IA-32 and X64. + on IA-32 and x64. If StartBit is greater than 63, then ASSERT(). If EndBit is greater than 63, then ASSERT(). @@ -5710,10 +5587,9 @@ AsmMsrBitFieldRead64 ( Writes Value to a bit field in a 64-bit MSR. The bit field is specified by the StartBit and the EndBit. All other bits in the destination MSR are - preserved. The MSR written is returned. Extra left bits in Value are - stripped. The caller must either guarantee that Index and the data written is - valid, or the caller must set up exception handlers to catch the exceptions. - This function is only available on IA-32 and X64. + preserved. The MSR written is returned. The caller must either guarantee + that Index and the data written is valid, or the caller must set up exception + handlers to catch the exceptions. This function is only available on IA-32 and x64. If StartBit is greater than 63, then ASSERT(). If EndBit is greater than 63, then ASSERT(). @@ -5740,16 +5616,16 @@ AsmMsrBitFieldWrite64 ( /** - Reads a bit field in a 64-bit MSR, performs a bitwise inclusive OR, and + Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the result back to the bit field in the 64-bit MSR. - Reads the 64-bit MSR specified by Index, performs a bitwise inclusive OR + Reads the 64-bit MSR specified by Index, performs a bitwise OR between the read result and the value specified by OrData, and writes the result to the 64-bit MSR specified by Index. The value written to the MSR is returned. Extra left bits in OrData are stripped. The caller must either guarantee that Index and the data written is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available - on IA-32 and X64. + on IA-32 and x64. If StartBit is greater than 63, then ASSERT(). If EndBit is greater than 63, then ASSERT(). @@ -5785,7 +5661,7 @@ AsmMsrBitFieldOr64 ( Extra left bits in AndData are stripped. The caller must either guarantee that Index and the data written is valid, or the caller must set up exception handlers to catch the exceptions. This function is only available on IA-32 - and X64. + and x64. If StartBit is greater than 63, then ASSERT(). If EndBit is greater than 63, then ASSERT(). @@ -5813,16 +5689,16 @@ AsmMsrBitFieldAnd64 ( /** Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a - bitwise inclusive OR, and writes the result back to the bit field in the + bitwise OR, and writes the result back to the bit field in the 64-bit MSR. Reads the 64-bit MSR specified by Index, performs a bitwise AND followed by - a bitwise inclusive OR between the read result and the value specified by + a bitwise OR between the read result and the value specified by AndData, and writes the result to the 64-bit MSR specified by Index. The value written to the MSR is returned. Extra left bits in both AndData and OrData are stripped. The caller must either guarantee that Index and the data written is valid, or the caller must set up exception handlers to catch the - exceptions. This function is only available on IA-32 and X64. + exceptions. This function is only available on IA-32 and x64. If StartBit is greater than 63, then ASSERT(). If EndBit is greater than 63, then ASSERT(). @@ -5854,10 +5730,10 @@ AsmMsrBitFieldAndThenOr64 ( Reads the current value of the EFLAGS register. Reads and returns the current value of the EFLAGS register. This function is - only available on IA-32 and X64. This returns a 32-bit value on IA-32 and a - 64-bit value on X64. + only available on IA-32 and x64. This returns a 32-bit value on IA-32 and a + 64-bit value on x64. - @return EFLAGS on IA-32 or RFLAGS on X64. + @return EFLAGS on IA-32 or RFLAGS on x64. **/ UINTN @@ -5871,8 +5747,8 @@ AsmReadEflags ( Reads the current value of the Control Register 0 (CR0). Reads and returns the current value of CR0. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of the Control Register 0 (CR0). @@ -5888,8 +5764,8 @@ AsmReadCr0 ( Reads the current value of the Control Register 2 (CR2). Reads and returns the current value of CR2. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of the Control Register 2 (CR2). @@ -5905,8 +5781,8 @@ AsmReadCr2 ( Reads the current value of the Control Register 3 (CR3). Reads and returns the current value of CR3. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of the Control Register 3 (CR3). @@ -5922,8 +5798,8 @@ AsmReadCr3 ( Reads the current value of the Control Register 4 (CR4). Reads and returns the current value of CR4. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of the Control Register 4 (CR4). @@ -5939,7 +5815,7 @@ AsmReadCr4 ( Writes a value to Control Register 0 (CR0). Writes and returns a new value to CR0. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Cr0 The value to write to CR0. @@ -5957,7 +5833,7 @@ AsmWriteCr0 ( Writes a value to Control Register 2 (CR2). Writes and returns a new value to CR2. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Cr2 The value to write to CR2. @@ -5975,7 +5851,7 @@ AsmWriteCr2 ( Writes a value to Control Register 3 (CR3). Writes and returns a new value to CR3. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Cr3 The value to write to CR3. @@ -5993,7 +5869,7 @@ AsmWriteCr3 ( Writes a value to Control Register 4 (CR4). Writes and returns a new value to CR4. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Cr4 The value to write to CR4. @@ -6011,8 +5887,8 @@ AsmWriteCr4 ( Reads the current value of Debug Register 0 (DR0). Reads and returns the current value of DR0. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 0 (DR0). @@ -6028,8 +5904,8 @@ AsmReadDr0 ( Reads the current value of Debug Register 1 (DR1). Reads and returns the current value of DR1. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 1 (DR1). @@ -6045,8 +5921,8 @@ AsmReadDr1 ( Reads the current value of Debug Register 2 (DR2). Reads and returns the current value of DR2. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 2 (DR2). @@ -6062,8 +5938,8 @@ AsmReadDr2 ( Reads the current value of Debug Register 3 (DR3). Reads and returns the current value of DR3. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 3 (DR3). @@ -6079,8 +5955,8 @@ AsmReadDr3 ( Reads the current value of Debug Register 4 (DR4). Reads and returns the current value of DR4. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 4 (DR4). @@ -6096,8 +5972,8 @@ AsmReadDr4 ( Reads the current value of Debug Register 5 (DR5). Reads and returns the current value of DR5. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 5 (DR5). @@ -6113,8 +5989,8 @@ AsmReadDr5 ( Reads the current value of Debug Register 6 (DR6). Reads and returns the current value of DR6. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 6 (DR6). @@ -6130,8 +6006,8 @@ AsmReadDr6 ( Reads the current value of Debug Register 7 (DR7). Reads and returns the current value of DR7. This function is only available - on IA-32 and X64. This returns a 32-bit value on IA-32 and a 64-bit value on - X64. + on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on + x64. @return The value of Debug Register 7 (DR7). @@ -6147,7 +6023,7 @@ AsmReadDr7 ( Writes a value to Debug Register 0 (DR0). Writes and returns a new value to DR0. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr0 The value to write to Dr0. @@ -6165,7 +6041,7 @@ AsmWriteDr0 ( Writes a value to Debug Register 1 (DR1). Writes and returns a new value to DR1. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr1 The value to write to Dr1. @@ -6183,7 +6059,7 @@ AsmWriteDr1 ( Writes a value to Debug Register 2 (DR2). Writes and returns a new value to DR2. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr2 The value to write to Dr2. @@ -6201,7 +6077,7 @@ AsmWriteDr2 ( Writes a value to Debug Register 3 (DR3). Writes and returns a new value to DR3. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr3 The value to write to Dr3. @@ -6219,7 +6095,7 @@ AsmWriteDr3 ( Writes a value to Debug Register 4 (DR4). Writes and returns a new value to DR4. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr4 The value to write to Dr4. @@ -6237,7 +6113,7 @@ AsmWriteDr4 ( Writes a value to Debug Register 5 (DR5). Writes and returns a new value to DR5. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr5 The value to write to Dr5. @@ -6255,7 +6131,7 @@ AsmWriteDr5 ( Writes a value to Debug Register 6 (DR6). Writes and returns a new value to DR6. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr6 The value to write to Dr6. @@ -6273,7 +6149,7 @@ AsmWriteDr6 ( Writes a value to Debug Register 7 (DR7). Writes and returns a new value to DR7. This function is only available on - IA-32 and X64. This writes a 32-bit value on IA-32 and a 64-bit value on X64. + IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64. @param Dr7 The value to write to Dr7. @@ -6291,7 +6167,7 @@ AsmWriteDr7 ( Reads the current value of Code Segment Register (CS). Reads and returns the current value of CS. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of CS. @@ -6307,7 +6183,7 @@ AsmReadCs ( Reads the current value of Data Segment Register (DS). Reads and returns the current value of DS. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of DS. @@ -6323,7 +6199,7 @@ AsmReadDs ( Reads the current value of Extra Segment Register (ES). Reads and returns the current value of ES. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of ES. @@ -6339,7 +6215,7 @@ AsmReadEs ( Reads the current value of FS Data Segment Register (FS). Reads and returns the current value of FS. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of FS. @@ -6355,7 +6231,7 @@ AsmReadFs ( Reads the current value of GS Data Segment Register (GS). Reads and returns the current value of GS. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of GS. @@ -6371,7 +6247,7 @@ AsmReadGs ( Reads the current value of Stack Segment Register (SS). Reads and returns the current value of SS. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of SS. @@ -6387,7 +6263,7 @@ AsmReadSs ( Reads the current value of Task Register (TR). Reads and returns the current value of TR. This function is only available on - IA-32 and X64. + IA-32 and x64. @return The current value of TR. @@ -6403,7 +6279,7 @@ AsmReadTr ( Reads the current Global Descriptor Table Register(GDTR) descriptor. Reads and returns the current GDTR descriptor and returns it in Gdtr. This - function is only available on IA-32 and X64. + function is only available on IA-32 and x64. If Gdtr is NULL, then ASSERT(). @@ -6421,7 +6297,7 @@ AsmReadGdtr ( Writes the current Global Descriptor Table Register (GDTR) descriptor. Writes and the current GDTR descriptor specified by Gdtr. This function is - only available on IA-32 and X64. + only available on IA-32 and x64. If Gdtr is NULL, then ASSERT(). @@ -6439,7 +6315,7 @@ AsmWriteGdtr ( Reads the current Interrupt Descriptor Table Register(IDTR) descriptor. Reads and returns the current IDTR descriptor and returns it in Idtr. This - function is only available on IA-32 and X64. + function is only available on IA-32 and x64. If Idtr is NULL, then ASSERT(). @@ -6457,7 +6333,7 @@ AsmReadIdtr ( Writes the current Interrupt Descriptor Table Register(IDTR) descriptor. Writes the current IDTR descriptor and returns it in Idtr. This function is - only available on IA-32 and X64. + only available on IA-32 and x64. If Idtr is NULL, then ASSERT(). @@ -6475,7 +6351,7 @@ AsmWriteIdtr ( Reads the current Local Descriptor Table Register(LDTR) selector. Reads and returns the current 16-bit LDTR descriptor value. This function is - only available on IA-32 and X64. + only available on IA-32 and x64. @return The current selector of LDT. @@ -6491,7 +6367,7 @@ AsmReadLdtr ( Writes the current Local Descriptor Table Register (LDTR) selector. Writes and the current LDTR descriptor specified by Ldtr. This function is - only available on IA-32 and X64. + only available on IA-32 and x64. @param Ldtr 16-bit LDTR selector value. @@ -6508,7 +6384,7 @@ AsmWriteLdtr ( Saves the current floating point/SSE/SSE2 state to the buffer specified by Buffer. Buffer must be aligned on a 16-byte boundary. This function is only - available on IA-32 and X64. + available on IA-32 and x64. If Buffer is NULL, then ASSERT(). If Buffer is not aligned on a 16-byte boundary, then ASSERT(). @@ -6528,7 +6404,7 @@ AsmFxSave ( Restores the current floating point/SSE/SSE2 state from the buffer specified by Buffer. Buffer must be aligned on a 16-byte boundary. This function is - only available on IA-32 and X64. + only available on IA-32 and x64. If Buffer is NULL, then ASSERT(). If Buffer is not aligned on a 16-byte boundary, then ASSERT(). @@ -6548,7 +6424,7 @@ AsmFxRestore ( Reads the current value of 64-bit MMX Register #0 (MM0). Reads and returns the current value of MM0. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM0. @@ -6564,7 +6440,7 @@ AsmReadMm0 ( Reads the current value of 64-bit MMX Register #1 (MM1). Reads and returns the current value of MM1. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM1. @@ -6580,7 +6456,7 @@ AsmReadMm1 ( Reads the current value of 64-bit MMX Register #2 (MM2). Reads and returns the current value of MM2. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM2. @@ -6596,7 +6472,7 @@ AsmReadMm2 ( Reads the current value of 64-bit MMX Register #3 (MM3). Reads and returns the current value of MM3. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM3. @@ -6612,7 +6488,7 @@ AsmReadMm3 ( Reads the current value of 64-bit MMX Register #4 (MM4). Reads and returns the current value of MM4. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM4. @@ -6628,7 +6504,7 @@ AsmReadMm4 ( Reads the current value of 64-bit MMX Register #5 (MM5). Reads and returns the current value of MM5. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM5. @@ -6644,7 +6520,7 @@ AsmReadMm5 ( Reads the current value of 64-bit MMX Register #6 (MM6). Reads and returns the current value of MM6. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM6. @@ -6660,7 +6536,7 @@ AsmReadMm6 ( Reads the current value of 64-bit MMX Register #7 (MM7). Reads and returns the current value of MM7. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of MM7. @@ -6676,7 +6552,7 @@ AsmReadMm7 ( Writes the current value of 64-bit MMX Register #0 (MM0). Writes the current value of MM0. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM0. @@ -6692,7 +6568,7 @@ AsmWriteMm0 ( Writes the current value of 64-bit MMX Register #1 (MM1). Writes the current value of MM1. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM1. @@ -6708,7 +6584,7 @@ AsmWriteMm1 ( Writes the current value of 64-bit MMX Register #2 (MM2). Writes the current value of MM2. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM2. @@ -6724,7 +6600,7 @@ AsmWriteMm2 ( Writes the current value of 64-bit MMX Register #3 (MM3). Writes the current value of MM3. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM3. @@ -6740,7 +6616,7 @@ AsmWriteMm3 ( Writes the current value of 64-bit MMX Register #4 (MM4). Writes the current value of MM4. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM4. @@ -6756,7 +6632,7 @@ AsmWriteMm4 ( Writes the current value of 64-bit MMX Register #5 (MM5). Writes the current value of MM5. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM5. @@ -6772,7 +6648,7 @@ AsmWriteMm5 ( Writes the current value of 64-bit MMX Register #6 (MM6). Writes the current value of MM6. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM6. @@ -6788,7 +6664,7 @@ AsmWriteMm6 ( Writes the current value of 64-bit MMX Register #7 (MM7). Writes the current value of MM7. This function is only available on IA32 and - X64. + x64. @param Value The 64-bit value to write to MM7. @@ -6804,7 +6680,7 @@ AsmWriteMm7 ( Reads the current value of Time Stamp Counter (TSC). Reads and returns the current value of TSC. This function is only available - on IA-32 and X64. + on IA-32 and x64. @return The current value of TSC @@ -6820,7 +6696,7 @@ AsmReadTsc ( Reads the current value of a Performance Counter (PMC). Reads and returns the current value of performance counter specified by - Index. This function is only available on IA-32 and X64. + Index. This function is only available on IA-32 and x64. @param Index The 32-bit Performance Counter index to read. @@ -6838,7 +6714,7 @@ AsmReadPmc ( Sets up a monitor buffer that is used by AsmMwait(). Executes a MONITOR instruction with the register state specified by Eax, Ecx - and Edx. Returns Eax. This function is only available on IA-32 and X64. + and Edx. Returns Eax. This function is only available on IA-32 and x64. @param Eax The value to load into EAX or RAX before executing the MONITOR instruction. @@ -6863,7 +6739,7 @@ AsmMonitor ( Executes an MWAIT instruction. Executes an MWAIT instruction with the register state specified by Eax and - Ecx. Returns Eax. This function is only available on IA-32 and X64. + Ecx. Returns Eax. This function is only available on IA-32 and x64. @param Eax The value to load into EAX or RAX before executing the MONITOR instruction. @@ -6885,7 +6761,7 @@ AsmMwait ( Executes a WBINVD instruction. Executes a WBINVD instruction. This function is only available on IA-32 and - X64. + x64. **/ VOID @@ -6899,7 +6775,7 @@ AsmWbinvd ( Executes a INVD instruction. Executes a INVD instruction. This function is only available on IA-32 and - X64. + x64. **/ VOID @@ -6914,7 +6790,7 @@ AsmInvd ( coherency domain of the CPU. Flushed the cache line specified by LinearAddress, and returns LinearAddress. - This function is only available on IA-32 and X64. + This function is only available on IA-32 and x64. @param LinearAddress The address of the cache line to flush. If the CPU is in a physical addressing mode, then LinearAddress is a @@ -7070,7 +6946,7 @@ AsmEnablePaging64 ( Disables the 64-bit paging mode on the CPU and returns to 32-bit protected mode. This function assumes the current execution mode is 64-paging mode. - This function is only available on X64. After the 64-bit paging mode is + This function is only available on x64. After the 64-bit paging mode is disabled, control is transferred to the function specified by EntryPoint using the new stack specified by NewStack and passing in the parameters specified by Context1 and Context2. Context1 and Context2 are optional and