X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FLibrary%2FBaseCacheMaintenanceLib%2FIpfCache.c;h=0c6f0e4dc8b195e6ab19a339af8ddfd84a45cfdd;hp=7e96d9b76a5d5559e66a8a57dd7d2d41259c8f21;hb=cd4903c497c9ace4016efb340d6e9cfd561a9833;hpb=91621725935f62c2c50be3695f7fee4966f08ab0

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index 7e96d9b76a..0c6f0e4dc8 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -12,21 +12,6 @@
 
 **/
 
-typedef struct {
-  UINT64                            Status;
-  UINT64                            r9;
-  UINT64                            r10;
-  UINT64                            r11;
-} PAL_PROC_RETURN;
-
-PAL_PROC_RETURN
-PalCallStatic (
-  IN      CONST VOID                *PalEntryPoint,
-  IN      UINT64                    Arg1,
-  IN      UINT64                    Arg2,
-  IN      UINT64                    Arg3,
-  IN      UINT64                    Arg4
-  );
 
 /**
   Invalidates the entire instruction cache in cache coherency domain of the
@@ -45,6 +30,41 @@ InvalidateInstructionCache (
   PalCallStatic (NULL, 1, 1, 1, 0);
 }
 
+/**
+  Invalidates a range of instruction cache lines in the cache coherency domain
+  of the calling CPU.
+
+  Invalidates the instruction cache lines specified by Address and Length. If
+  Address is not aligned on a cache line boundary, then entire instruction
+  cache line containing Address is invalidated. If Address + Length is not
+  aligned on a cache line boundary, then the entire instruction cache line
+  containing Address + Length -1 is invalidated. This function may choose to
+  invalidate the entire instruction cache if that is more efficient than
+  invalidating the specified range. If Length is 0, the no instruction cache
+  lines are invalidated. Address is returned.
+
+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+  @param  Address The base address of the instruction cache lines to
+                  invalidate. If the CPU is in a physical addressing mode, then
+                  Address is a physical address. If the CPU is in a virtual
+                  addressing mode, then Address is a virtual address.
+
+  @param  Length  The number of bytes to invalidate from the instruction cache.
+
+  @return Address
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+  IN      VOID                      *Address,
+  IN      UINTN                     Length
+  )
+{
+  return IpfInvalidateInstructionCacheRange (Address, Length);
+}
+
 /**
   Writes Back and Invalidates the entire data cache in cache coherency domain
   of the calling CPU.