X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FLibrary%2FBaseLib%2FIa32%2FGccInline.c;h=f52a1fe171f33c3fdd64a922dbca328771958c65;hp=02af3f66464c5dc0286a3e53c3e4dc0b8eff717f;hb=881813d7a93d9009c873515b043c41c4554779e4;hpb=d2660fe32d000765cc5d370bdc4452fec9389b2a
diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index 02af3f6646..f52a1fe171 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1,7 +1,7 @@
/** @file
GCC inline implementation of BaseLib processor specific functions.
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
IN VOID *LinearAddress
)
{
+ UINT32 RegEdx;
+
+ //
+ // If the CPU does not support CLFLUSH instruction,
+ // then promote flush range to flush entire cache.
+ //
+ AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
+ if ((RegEdx & BIT19) == 0) {
+ __asm__ __volatile__ ("wbinvd":::"memory");
+ return LinearAddress;
+ }
+
+
__asm__ __volatile__ (
"clflush (%0)"
: "+a" (LinearAddress)
@@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
: "memory"
);
- return LinearAddress;
+ return LinearAddress;
}