X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FLibrary%2FBaseLib%2FIa32%2FGccInline.c;h=f52a1fe171f33c3fdd64a922dbca328771958c65;hp=e0600e1a850f4c884a965e1e4abea1d2cbcba456;hb=881813d7a93d9009c873515b043c41c4554779e4;hpb=ebd04fc2e526ddc76f17e05cb50798fbf448e52e

diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseLib/Ia32/GccInline.c
index e0600e1a85..f52a1fe171 100644
--- a/MdePkg/Library/BaseLib/Ia32/GccInline.c
+++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c
@@ -1,12 +1,12 @@
 /** @file
   GCC inline implementation of BaseLib processor specific functions.
   
-  Copyright (c) 2006 - 2007, Intel Corporation<BR>
-  Portions copyright (c) 2008-2009 Apple Inc.<BR>
-  All rights reserved. This program and the accompanying materials
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  http://opensource.org/licenses/bsd-license.php.
 
   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@@ -32,8 +32,8 @@ MemoryFence (
   )
 {
   // This is a little bit of overkill and it is more about the compiler that it is
-  // actually processor syncronization. This is like the _ReadWriteBarrier 
-  // Microsft specific intrinsic
+  // actually processor synchronization. This is like the _ReadWriteBarrier 
+  // Microsoft specific intrinsic
   __asm__ __volatile__ ("":::"memory");
 }
 
@@ -1026,7 +1026,7 @@ AsmReadTr (
   Reads and returns the current GDTR descriptor and returns it in Gdtr. This
   function is only available on IA-32 and X64.
 
-  @param  Gdtr  Pointer to a GDTR descriptor.
+  @param  Gdtr  The pointer to a GDTR descriptor.
 
 **/
 VOID
@@ -1048,7 +1048,7 @@ InternalX86ReadGdtr (
   Writes and the current GDTR descriptor specified by Gdtr. This function is
   only available on IA-32 and X64.
 
-  @param  Gdtr  Pointer to a GDTR descriptor.
+  @param  Gdtr  The pointer to a GDTR descriptor.
 
 **/
 VOID
@@ -1072,18 +1072,18 @@ InternalX86WriteGdtr (
   Reads and returns the current IDTR descriptor and returns it in Idtr. This
   function is only available on IA-32 and X64.
 
-  @param  Idtr  Pointer to a IDTR descriptor.
+  @param  Idtr  The pointer to a IDTR descriptor.
 
 **/
 VOID
 EFIAPI
 InternalX86ReadIdtr (
-  OUT     IA32_DESCRIPTOR           *Ldtr
+  OUT     IA32_DESCRIPTOR           *Idtr
   )
 {
   __asm__ __volatile__ (
-    "sldt  %0"
-    : "=m" (*Ldtr)
+    "sidt  %0"
+    : "=m" (*Idtr)
     );
 }
 
@@ -1094,19 +1094,19 @@ InternalX86ReadIdtr (
   Writes the current IDTR descriptor and returns it in Idtr. This function is
   only available on IA-32 and X64.
 
-  @param  Idtr  Pointer to a IDTR descriptor.
+  @param  Idtr  The pointer to a IDTR descriptor.
 
 **/
 VOID
 EFIAPI
 InternalX86WriteIdtr (
-  IN      CONST IA32_DESCRIPTOR     *Ldtr
+  IN      CONST IA32_DESCRIPTOR     *Idtr
   )
 {
   __asm__ __volatile__ (
     "lidt %0"
     :
-    : "m" (*Ldtr)
+    : "m" (*Idtr)
     );
 }
 
@@ -1167,7 +1167,7 @@ AsmWriteLdtr (
   Buffer. Buffer must be aligned on a 16-byte boundary. This function is only
   available on IA-32 and X64.
 
-  @param  Buffer  Pointer to a buffer to save the floating point/SSE/SSE2 context.
+  @param  Buffer  The pointer to a buffer to save the floating point/SSE/SSE2 context.
 
 **/
 VOID
@@ -1191,7 +1191,7 @@ InternalX86FxSave (
   by Buffer. Buffer must be aligned on a 16-byte boundary. This function is
   only available on IA-32 and X64.
 
-  @param  Buffer  Pointer to a buffer to save the floating point/SSE/SSE2 context.
+  @param  Buffer  The pointer to a buffer to save the floating point/SSE/SSE2 context.
 
 **/
 VOID
@@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
   IN      VOID                      *LinearAddress
   )
 {
+  UINT32  RegEdx;
+
+  //
+  // If the CPU does not support CLFLUSH instruction, 
+  // then promote flush range to flush entire cache.
+  //
+  AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
+  if ((RegEdx & BIT19) == 0) {
+    __asm__ __volatile__ ("wbinvd":::"memory");
+    return LinearAddress;
+  }
+
+
   __asm__ __volatile__ (
     "clflush (%0)"
     : "+a" (LinearAddress) 
@@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
     : "memory"
     );
     
-    return LinearAddress;
+  return LinearAddress;
 }