X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=MdePkg%2FLibrary%2FUefiPciSegmentLibPciRootBridgeIo%2FPciSegmentLib.c;h=bffb52708e740783a8120d5eb4b606e75d2edafa;hp=cb8991e2da7dd1b56827b3d6337d9b521c25161f;hb=19388d2960b2fe0347da23799e93ccc52f540214;hpb=3e3ae6345709da38e9a26dffb83a47cc47d7b0e5 diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c index cb8991e2da..bffb52708e 100644 --- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c +++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c @@ -1,8 +1,8 @@ /** @file PCI Segment Library implementation using PCI Root Bridge I/O Protocol. - Copyright (c) 2007 - 2008, Intel Corporation All rights - reserved. This program and the accompanying materials are + Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -16,13 +16,13 @@ #include "PciSegmentLib.h" // -// Global varible to record data of PCI Root Bridge I/O Protcol instances +// Global variable to record data of PCI Root Bridge I/O Protocol instances // PCI_ROOT_BRIDGE_DATA *mPciRootBridgeData = NULL; UINTN mNumberOfPciRootBridges = 0; /** - The constructor function caches data of PCI Root Bridge I/O Protcol instances. + The constructor function caches data of PCI Root Bridge I/O Protocol instances. The constructor function locates PCI Root Bridge I/O protocol instances, and caches the protocol instances, together with their segment numbers and bus ranges. @@ -244,7 +244,7 @@ DxePciSegmentLibPciRootBridgeIoWriteWorker ( Register a PCI device so PCI configuration registers may be accessed after SetVirtualAddressMap(). - If Address > 0x0FFFFFFF, then ASSERT(). + If any reserved bits in Address are set, then ASSERT(). @param Address Address that encodes the PCI Bus, Device, Function and Register. @@ -264,6 +264,7 @@ PciSegmentRegisterForRuntimeAccess ( IN UINTN Address ) { + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); return RETURN_UNSUPPORTED; } @@ -271,21 +272,19 @@ PciSegmentRegisterForRuntimeAccess ( Reads an 8-bit PCI configuration register. Reads and returns the 8-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - - @return The value read from the PCI configuration register. + @return The 8-bit PCI configuration register specified by Address. **/ UINT8 EFIAPI PciSegmentRead8 ( - IN UINT64 Address + IN UINT64 Address ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); @@ -296,15 +295,13 @@ PciSegmentRead8 ( /** Writes an 8-bit PCI configuration register. - Writes the 8-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param Data The value to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. @return The value written to the PCI configuration register. @@ -312,103 +309,94 @@ PciSegmentRead8 ( UINT8 EFIAPI PciSegmentWrite8 ( - IN UINT64 Address, - IN UINT8 Data + IN UINT64 Address, + IN UINT8 Value ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); - return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data); + return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value); } /** - Performs a bitwise inclusive OR of an 8-bit PCI configuration register with - an 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise inclusive OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value. + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT8 EFIAPI PciSegmentOr8 ( - IN UINT64 Address, - IN UINT8 OrData + IN UINT64 Address, + IN UINT8 OrData ) { return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData)); } /** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit - value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value. + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT8 EFIAPI PciSegmentAnd8 ( - IN UINT64 Address, - IN UINT8 AndData + IN UINT64 Address, + IN UINT8 AndData ) { return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData)); } /** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit - value, followed a bitwise inclusive OR with another 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise inclusive OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT8 EFIAPI PciSegmentAndThenOr8 ( - IN UINT64 Address, - IN UINT8 AndData, - IN UINT8 OrData + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData ) { return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData)); @@ -438,9 +426,9 @@ PciSegmentAndThenOr8 ( UINT8 EFIAPI PciSegmentBitFieldRead8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit ) { return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); @@ -472,10 +460,10 @@ PciSegmentBitFieldRead8 ( UINT8 EFIAPI PciSegmentBitFieldWrite8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 Value + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value ) { return PciSegmentWrite8 ( @@ -489,7 +477,7 @@ PciSegmentBitFieldWrite8 ( writes the result back to the bit field in the 8-bit port. Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise inclusive OR between the read result and the value specified by + bitwise OR between the read result and the value specified by OrData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations @@ -513,10 +501,10 @@ PciSegmentBitFieldWrite8 ( UINT8 EFIAPI PciSegmentBitFieldOr8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData ) { return PciSegmentWrite8 ( @@ -554,10 +542,10 @@ PciSegmentBitFieldOr8 ( UINT8 EFIAPI PciSegmentBitFieldAnd8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData ) { return PciSegmentWrite8 ( @@ -568,11 +556,11 @@ PciSegmentBitFieldAnd8 ( /** Reads a bit field in an 8-bit port, performs a bitwise AND followed by a - bitwise inclusive OR, and writes the result back to the bit field in the + bitwise OR, and writes the result back to the bit field in the 8-bit port. Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise inclusive OR between the read result and + bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 8-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI @@ -598,11 +586,11 @@ PciSegmentBitFieldAnd8 ( UINT8 EFIAPI PciSegmentBitFieldAndThenOr8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData, - IN UINT8 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData ) { return PciSegmentWrite8 ( @@ -615,21 +603,20 @@ PciSegmentBitFieldAndThenOr8 ( Reads a 16-bit PCI configuration register. Reads and returns the 16-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - - @return The value read from the PCI configuration register. + @return The 16-bit PCI configuration register specified by Address. **/ UINT16 EFIAPI PciSegmentRead16 ( - IN UINT64 Address + IN UINT64 Address ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); @@ -640,43 +627,43 @@ PciSegmentRead16 ( /** Writes a 16-bit PCI configuration register. - Writes the 16-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param Data The value to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. - @return The value written to the PCI configuration register. + @return The parameter of Value. **/ UINT16 EFIAPI PciSegmentWrite16 ( - IN UINT64 Address, - IN UINT16 Data + IN UINT64 Address, + IN UINT16 Value ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); - return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data); + return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value); } /** - Performs a bitwise inclusive OR of a 16-bit PCI configuration register with + Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit value. Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise inclusive OR between the read result and the value specified by + bitwise OR between the read result and the value specified by OrData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register. @@ -688,71 +675,68 @@ PciSegmentWrite16 ( UINT16 EFIAPI PciSegmentOr16 ( - IN UINT64 Address, - IN UINT16 OrData + IN UINT64 Address, + IN UINT16 OrData ) { return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData)); } /** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit - value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value. + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT16 EFIAPI PciSegmentAnd16 ( - IN UINT64 Address, - IN UINT16 AndData + IN UINT64 Address, + IN UINT16 AndData ) { return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData)); } /** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit - value, followed a bitwise inclusive OR with another 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise inclusive OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT16 EFIAPI PciSegmentAndThenOr16 ( - IN UINT64 Address, - IN UINT16 AndData, - IN UINT16 OrData + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData ) { return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData)); @@ -766,6 +750,7 @@ PciSegmentAndThenOr16 ( returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -782,9 +767,9 @@ PciSegmentAndThenOr16 ( UINT16 EFIAPI PciSegmentBitFieldRead16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit ) { return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); @@ -799,6 +784,7 @@ PciSegmentBitFieldRead16 ( 16-bit register is returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -816,10 +802,10 @@ PciSegmentBitFieldRead16 ( UINT16 EFIAPI PciSegmentBitFieldWrite16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 Value + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value ) { return PciSegmentWrite16 ( @@ -829,17 +815,12 @@ PciSegmentBitFieldWrite16 ( } /** - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise inclusive OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -857,10 +838,10 @@ PciSegmentBitFieldWrite16 ( UINT16 EFIAPI PciSegmentBitFieldOr16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData ) { return PciSegmentWrite16 ( @@ -870,38 +851,39 @@ PciSegmentBitFieldOr16 ( } /** - Reads a bit field in a 16-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 16-bit register. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + Extra left bits in OrData are stripped. + If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). - @param Address PCI configuration register to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. + The ordinal of the least significant bit in a byte is bit 0. @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. + The ordinal of the most significant bit in a byte is bit 7. + @param AndData The value to AND with the read value from the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT16 EFIAPI PciSegmentBitFieldAnd16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData ) { return PciSegmentWrite16 ( @@ -912,11 +894,11 @@ PciSegmentBitFieldAnd16 ( /** Reads a bit field in a 16-bit port, performs a bitwise AND followed by a - bitwise inclusive OR, and writes the result back to the bit field in the + bitwise OR, and writes the result back to the bit field in the 16-bit port. Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise inclusive OR between the read result and + bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 16-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI @@ -942,11 +924,11 @@ PciSegmentBitFieldAnd16 ( UINT16 EFIAPI PciSegmentBitFieldAndThenOr16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData, - IN UINT16 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData ) { return PciSegmentWrite16 ( @@ -959,21 +941,20 @@ PciSegmentBitFieldAndThenOr16 ( Reads a 32-bit PCI configuration register. Reads and returns the 32-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. - @return The value read from the PCI configuration register. + @return The 32-bit PCI configuration register specified by Address. **/ UINT32 EFIAPI PciSegmentRead32 ( - IN UINT64 Address + IN UINT64 Address ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); @@ -984,119 +965,113 @@ PciSegmentRead32 ( /** Writes a 32-bit PCI configuration register. - Writes the 32-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param Data The value to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. - @return The value written to the PCI configuration register. + @return The parameter of Value. **/ UINT32 EFIAPI PciSegmentWrite32 ( - IN UINT64 Address, - IN UINT32 Data + IN UINT64 Address, + IN UINT32 Value ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); - return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data); + return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value); } /** - Performs a bitwise inclusive OR of a 32-bit PCI configuration register with - a 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise inclusive OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentOr32 ( - IN UINT64 Address, - IN UINT32 OrData + IN UINT64 Address, + IN UINT32 OrData ) { return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); } /** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit - value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentAnd32 ( - IN UINT64 Address, - IN UINT32 AndData + IN UINT64 Address, + IN UINT32 AndData ) { return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); } /** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit - value, followed a bitwise inclusive OR with another 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise inclusive OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentAndThenOr32 ( - IN UINT64 Address, - IN UINT32 AndData, - IN UINT32 OrData + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData ) { return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); @@ -1110,6 +1085,7 @@ PciSegmentAndThenOr32 ( returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -1126,9 +1102,9 @@ PciSegmentAndThenOr32 ( UINT32 EFIAPI PciSegmentBitFieldRead32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit ) { return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); @@ -1143,6 +1119,7 @@ PciSegmentBitFieldRead32 ( 32-bit register is returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -1160,10 +1137,10 @@ PciSegmentBitFieldRead32 ( UINT32 EFIAPI PciSegmentBitFieldWrite32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 Value + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value ) { return PciSegmentWrite32 ( @@ -1177,7 +1154,7 @@ PciSegmentBitFieldWrite32 ( writes the result back to the bit field in the 32-bit port. Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise inclusive OR between the read result and the value specified by + bitwise OR between the read result and the value specified by OrData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI read and write operations @@ -1201,10 +1178,10 @@ PciSegmentBitFieldWrite32 ( UINT32 EFIAPI PciSegmentBitFieldOr32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData ) { return PciSegmentWrite32 ( @@ -1217,17 +1194,18 @@ PciSegmentBitFieldOr32 ( Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register. - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - + + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise + AND between the read result and the value specified by AndData, and writes the result + to the 32-bit PCI configuration register specified by Address. The value written to + the PCI configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in AndData are stripped. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). + @param Address PCI configuration register to write. @param StartBit The ordinal of the least significant bit in the bit field. @@ -1242,10 +1220,10 @@ PciSegmentBitFieldOr32 ( UINT32 EFIAPI PciSegmentBitFieldAnd32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData ) { return PciSegmentWrite32 ( @@ -1256,11 +1234,11 @@ PciSegmentBitFieldAnd32 ( /** Reads a bit field in a 32-bit port, performs a bitwise AND followed by a - bitwise inclusive OR, and writes the result back to the bit field in the + bitwise OR, and writes the result back to the bit field in the 32-bit port. Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND followed by a bitwise inclusive OR between the read result and + bitwise AND followed by a bitwise OR between the read result and the value specified by AndData, and writes the result to the 32-bit PCI configuration register specified by Address. The value written to the PCI configuration register is returned. This function must guarantee that all PCI @@ -1286,11 +1264,11 @@ PciSegmentBitFieldAnd32 ( UINT32 EFIAPI PciSegmentBitFieldAndThenOr32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData, - IN UINT32 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData ) { return PciSegmentWrite32 ( @@ -1310,7 +1288,7 @@ PciSegmentBitFieldAndThenOr32 ( and 16-bit PCI configuration read cycles may be used at the beginning and the end of the range. - If StartAddress > 0x0FFFFFFF, then ASSERT(). + If any reserved bits in StartAddress are set, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT(). @@ -1325,9 +1303,9 @@ PciSegmentBitFieldAndThenOr32 ( UINTN EFIAPI PciSegmentReadBuffer ( - IN UINT64 StartAddress, - IN UINTN Size, - OUT VOID *Buffer + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer ) { UINTN ReturnValue; @@ -1360,7 +1338,7 @@ PciSegmentReadBuffer ( // // Read a word if StartAddress is word aligned // - *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress); + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); StartAddress += sizeof (UINT16); Size -= sizeof (UINT16); Buffer = (UINT16*)Buffer + 1; @@ -1370,7 +1348,7 @@ PciSegmentReadBuffer ( // // Read as many double words as possible // - *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress); + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); StartAddress += sizeof (UINT32); Size -= sizeof (UINT32); Buffer = (UINT32*)Buffer + 1; @@ -1380,7 +1358,7 @@ PciSegmentReadBuffer ( // // Read the last remaining word if exist // - *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress); + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); StartAddress += sizeof (UINT16); Size -= sizeof (UINT16); Buffer = (UINT16*)Buffer + 1; @@ -1408,7 +1386,7 @@ PciSegmentReadBuffer ( 8-bit and 16-bit PCI configuration write cycles may be used at the beginning and the end of the range. - If StartAddress > 0x0FFFFFFF, then ASSERT(). + If any reserved bits in StartAddress are set, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT(). @@ -1417,15 +1395,15 @@ PciSegmentReadBuffer ( @param Size Size in bytes of the transfer. @param Buffer Pointer to a buffer containing the data to write. - @return Size + @return The parameter of Size. **/ UINTN EFIAPI PciSegmentWriteBuffer ( - IN UINT64 StartAddress, - IN UINTN Size, - IN VOID *Buffer + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer ) { UINTN ReturnValue; @@ -1458,7 +1436,7 @@ PciSegmentWriteBuffer ( // // Write a word if StartAddress is word aligned // - PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer); + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); StartAddress += sizeof (UINT16); Size -= sizeof (UINT16); Buffer = (UINT16*)Buffer + 1; @@ -1468,7 +1446,7 @@ PciSegmentWriteBuffer ( // // Write as many double words as possible // - PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer); + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); StartAddress += sizeof (UINT32); Size -= sizeof (UINT32); Buffer = (UINT32*)Buffer + 1; @@ -1478,7 +1456,7 @@ PciSegmentWriteBuffer ( // // Write the last remaining word if exist // - PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer); + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); StartAddress += sizeof (UINT16); Size -= sizeof (UINT16); Buffer = (UINT16*)Buffer + 1;