X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=QuarkSocPkg%2FQuarkNorthCluster%2FInclude%2FLibrary%2FQNCAccessLib.h;fp=QuarkSocPkg%2FQuarkNorthCluster%2FInclude%2FLibrary%2FQNCAccessLib.h;h=0000000000000000000000000000000000000000;hp=290902c67feb8cbdfde0fb8cb64f88c646d6f4e3;hb=5347c48016f27061475fdb053e867a06ce73492f;hpb=96ef5a8e30a8da33eaab09f13cc8d752342717a5 diff --git a/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h b/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h deleted file mode 100644 index 290902c67f..0000000000 --- a/QuarkSocPkg/QuarkNorthCluster/Include/Library/QNCAccessLib.h +++ /dev/null @@ -1,161 +0,0 @@ -/** @file -Library functions for Setting QNC internal network port - -Copyright (c) 2013-2015 Intel Corporation. - -SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __QNC_ACCESS_LIB_H__ -#define __QNC_ACCESS_LIB_H__ - -#include - -#define MESSAGE_READ_DW(Port, Reg) \ - (UINT32)((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - -#define MESSAGE_WRITE_DW(Port, Reg) \ - (UINT32)((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - -#define ALT_MESSAGE_READ_DW(Port, Reg) \ - (UINT32)((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - -#define ALT_MESSAGE_WRITE_DW(Port, Reg) \ - (UINT32)((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - -#define MESSAGE_IO_READ_DW(Port, Reg) \ - (UINT32)((QUARK_OPCODE_IO_READ << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - -#define MESSAGE_IO_WRITE_DW(Port, Reg) \ - (UINT32)((QUARK_OPCODE_IO_WRITE << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - -#define MESSAGE_SHADOW_DW(Port, Reg) \ - (UINT32)((QUARK_DRAM_BASE_ADDR_READY << QNC_MCR_OP_OFFSET) | ((Port << QNC_MCR_PORT_OFFSET) & 0xFF0000) | ((Reg << QNC_MCR_REG_OFFSET) & 0xFF00) | 0xF0) - - -/** - Read required data from QNC internal message network -**/ -UINT32 -EFIAPI -QNCPortRead( - UINT8 Port, - UINT32 RegAddress - ); - -/** - Write prepared data into QNC internal message network. - -**/ -VOID -EFIAPI -QNCPortWrite ( - UINT8 Port, - UINT32 RegAddress, - UINT32 WriteValue - ); - -/** - Read required data from QNC internal message network -**/ -UINT32 -EFIAPI -QNCAltPortRead( - UINT8 Port, - UINT32 RegAddress - ); - -/** - Write prepared data into QNC internal message network. - -**/ -VOID -EFIAPI -QNCAltPortWrite ( - UINT8 Port, - UINT32 RegAddress, - UINT32 WriteValue - ); - -/** - Read required data from QNC internal message network -**/ -UINT32 -EFIAPI -QNCPortIORead( - UINT8 Port, - UINT32 RegAddress - ); - -/** - Write prepared data into QNC internal message network. - -**/ -VOID -EFIAPI -QNCPortIOWrite ( - UINT8 Port, - UINT32 RegAddress, - UINT32 WriteValue - ); - -/** - This is for the special consideration for QNC MMIO write, as required by FWG, - a reading must be performed after MMIO writing to ensure the expected write - is processed and data is flushed into chipset - -**/ -RETURN_STATUS -EFIAPI -QNCMmIoWrite ( - UINT32 MmIoAddress, - QNC_MEM_IO_WIDTH Width, - UINT32 DataNumber, - VOID *pData - ); - -UINT32 -EFIAPI -QncHsmmcRead ( - VOID - ); - -VOID -EFIAPI -QncHsmmcWrite ( - UINT32 WriteValue - ); - -VOID -EFIAPI -QncImrWrite ( - UINT32 ImrBaseOffset, - UINT32 ImrLow, - UINT32 ImrHigh, - UINT32 ImrReadMask, - UINT32 ImrWriteMask - ); - -VOID -EFIAPI -QncIClkAndThenOr ( - UINT32 RegAddress, - UINT32 AndValue, - UINT32 OrValue - ); - -VOID -EFIAPI -QncIClkOr ( - UINT32 RegAddress, - UINT32 OrValue - ); - -UINTN -EFIAPI -QncGetPciExpressBaseAddress ( - VOID - ); - -#endif