X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=SecurityPkg%2FTcg%2FTcg2Smm%2FTpm.asl;fp=SecurityPkg%2FTcg%2FTcg2Smm%2FTpm.asl;h=95f9d7eae8416ee60d86d3003f47198361d76d88;hp=7a91708a1a344016a763bb33581c737657beaea3;hb=6e3c834ae47d1201c4ddcc6a6adc5e44718c7617;hpb=cda6f9455c87fc8d69283ea83b6ce55a649b28d0

diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
index 7a91708a1a..95f9d7eae8 100644
--- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
+++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
@@ -4,7 +4,7 @@
 
 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
 (c)Copyright 2016 HP Development Company, L.P.<BR>
-Copyright (c) 2017, Microsoft Corporation.  All rights reserved. <BR>
+Copyright (c) Microsoft Corporation.<BR>
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -41,10 +41,10 @@ DefinitionBlock (
       //
       // Operational region for Smi port access
       //
-      OperationRegion (SMIP, SystemIO, 0xB2, 1)
+      OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)
       Field (SMIP, ByteAcc, NoLock, Preserve)
       {
-          IOB2, 8
+          IOPN, 8
       }
 
       //
@@ -258,7 +258,7 @@ DefinitionBlock (
             //
             // Trigger the SMI interrupt
             //
-            Store (MCIN, IOB2)
+            Store (MCIN, IOPN)
           }
         }
         Return (0)
@@ -359,7 +359,7 @@ DefinitionBlock (
             //
             // Trigger the SMI interrupt
             //
-            Store (PPIN, IOB2)
+            Store (PPIN, IOPN)
             Return (FRET)
 
 
@@ -390,7 +390,7 @@ DefinitionBlock (
             //
             // Trigger the SMI interrupt
             //
-            Store (PPIN, IOB2)
+            Store (PPIN, IOPN)
 
             Store (LPPR, Index (TPM3, 0x01))
             Store (PPRP, Index (TPM3, 0x02))
@@ -422,7 +422,7 @@ DefinitionBlock (
             //
             // Trigger the SMI interrupt
             //
-            Store (PPIN, IOB2)
+            Store (PPIN, IOPN)
             Return (FRET)
           }
           Case (8)
@@ -436,7 +436,7 @@ DefinitionBlock (
             //
             // Trigger the SMI interrupt
             //
-            Store (PPIN, IOB2)
+            Store (PPIN, IOPN)
 
             Return (FRET)
           }
@@ -475,7 +475,7 @@ DefinitionBlock (
             //
             // Trigger the SMI interrupt
             //
-            Store (MCIN, IOB2)
+            Store (MCIN, IOPN)
             Return (MRET)
           }
           Default {BreakPoint}