X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=ShellPkg%2FLibrary%2FUefiShellDebug1CommandsLib%2FPci.c;h=df45cd68aa22a190d27d67c3539257abe0f438d5;hp=a539bb568cadd96e79bb87a4a021cf3cea40022d;hb=c011b6c9e2baf57fc0557117e9875ceb3dca55a3;hpb=705bffb568b36813ff6eccbe5a93cffb0b143044
diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index a539bb568c..df45cd68aa 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -1,7 +1,7 @@
/** @file
Main file for Pci shell Debug1 function.
- Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
+ (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -20,7 +20,6 @@
#include
#include "Pci.h"
-#define PCI_CLASS_STRING_LIMIT 54
//
// Printable strings for Pci class code
//
@@ -63,9 +62,19 @@ PCI_CLASS_ENTRY PCISubClass_0e[];
PCI_CLASS_ENTRY PCISubClass_0f[];
PCI_CLASS_ENTRY PCISubClass_10[];
PCI_CLASS_ENTRY PCISubClass_11[];
+PCI_CLASS_ENTRY PCISubClass_12[];
+PCI_CLASS_ENTRY PCISubClass_13[];
+PCI_CLASS_ENTRY PCIPIFClass_0100[];
PCI_CLASS_ENTRY PCIPIFClass_0101[];
+PCI_CLASS_ENTRY PCIPIFClass_0105[];
+PCI_CLASS_ENTRY PCIPIFClass_0106[];
+PCI_CLASS_ENTRY PCIPIFClass_0107[];
+PCI_CLASS_ENTRY PCIPIFClass_0108[];
+PCI_CLASS_ENTRY PCIPIFClass_0109[];
PCI_CLASS_ENTRY PCIPIFClass_0300[];
PCI_CLASS_ENTRY PCIPIFClass_0604[];
+PCI_CLASS_ENTRY PCIPIFClass_0609[];
+PCI_CLASS_ENTRY PCIPIFClass_060b[];
PCI_CLASS_ENTRY PCIPIFClass_0700[];
PCI_CLASS_ENTRY PCIPIFClass_0701[];
PCI_CLASS_ENTRY PCIPIFClass_0703[];
@@ -76,6 +85,8 @@ PCI_CLASS_ENTRY PCIPIFClass_0803[];
PCI_CLASS_ENTRY PCIPIFClass_0904[];
PCI_CLASS_ENTRY PCIPIFClass_0c00[];
PCI_CLASS_ENTRY PCIPIFClass_0c03[];
+PCI_CLASS_ENTRY PCIPIFClass_0c07[];
+PCI_CLASS_ENTRY PCIPIFClass_0d01[];
PCI_CLASS_ENTRY PCIPIFClass_0e00[];
//
@@ -172,6 +183,16 @@ PCI_CLASS_ENTRY gClassStringList[] = {
L"Data Acquisition & Signal Processing Controllers",
PCISubClass_11
},
+ {
+ 0x12,
+ L"Processing Accelerators",
+ PCISubClass_12
+ },
+ {
+ 0x13,
+ L"Non-Essential Instrumentation",
+ PCISubClass_13
+ },
{
0xff,
L"Device does not fit in any defined classes",
@@ -221,8 +242,8 @@ PCI_CLASS_ENTRY PCISubClass_00[] = {
PCI_CLASS_ENTRY PCISubClass_01[] = {
{
0x00,
- L"SCSI controller",
- PCIBlankEntry
+ L"SCSI",
+ PCIPIFClass_0100
},
{
0x01,
@@ -244,6 +265,31 @@ PCI_CLASS_ENTRY PCISubClass_01[] = {
L"RAID controller",
PCIBlankEntry
},
+ {
+ 0x05,
+ L"ATA controller with ADMA interface",
+ PCIPIFClass_0105
+ },
+ {
+ 0x06,
+ L"Serial ATA controller",
+ PCIPIFClass_0106
+ },
+ {
+ 0x07,
+ L"Serial Attached SCSI (SAS) controller ",
+ PCIPIFClass_0107
+ },
+ {
+ 0x08,
+ L"Non-volatile memory subsystem",
+ PCIPIFClass_0108
+ },
+ {
+ 0x09,
+ L"Universal Flash Storage (UFS) controller ",
+ PCIPIFClass_0109
+ },
{
0x80,
L"Other mass storage controller",
@@ -282,6 +328,21 @@ PCI_CLASS_ENTRY PCISubClass_02[] = {
L"ISDN controller",
PCIBlankEntry
},
+ {
+ 0x05,
+ L"WorldFip controller",
+ PCIBlankEntry
+ },
+ {
+ 0x06,
+ L"PICMG 2.14 Multi Computing",
+ PCIBlankEntry
+ },
+ {
+ 0x07,
+ L"InfiniBand controller",
+ PCIBlankEntry
+ },
{
0x80,
L"Other network controller",
@@ -338,6 +399,11 @@ PCI_CLASS_ENTRY PCISubClass_04[] = {
L"Computer Telephony device",
PCIBlankEntry
},
+ {
+ 0x03,
+ L"Mixed mode device",
+ PCIBlankEntry
+ },
{
0x80,
L"Other multimedia device",
@@ -419,6 +485,21 @@ PCI_CLASS_ENTRY PCISubClass_06[] = {
L"RACEway bridge",
PCIBlankEntry
},
+ {
+ 0x09,
+ L"Semi-transparent PCI-to-PCI bridge",
+ PCIPIFClass_0609
+ },
+ {
+ 0x0A,
+ L"InfiniBand-to-PCI host bridge",
+ PCIBlankEntry
+ },
+ {
+ 0x0B,
+ L"Advanced Switching to PCI host bridge",
+ PCIPIFClass_060b
+ },
{
0x80,
L"Other bridge type",
@@ -452,6 +533,16 @@ PCI_CLASS_ENTRY PCISubClass_07[] = {
L"Modem",
PCIPIFClass_0703
},
+ {
+ 0x04,
+ L"GPIB (IEEE 488.1/2) controller",
+ PCIBlankEntry
+ },
+ {
+ 0x05,
+ L"Smart Card",
+ PCIBlankEntry
+ },
{
0x80,
L"Other communication device",
@@ -490,6 +581,21 @@ PCI_CLASS_ENTRY PCISubClass_08[] = {
L"Generic PCI Hot-Plug controller",
PCIBlankEntry
},
+ {
+ 0x05,
+ L"SD Host controller",
+ PCIBlankEntry
+ },
+ {
+ 0x06,
+ L"IOMMU",
+ PCIBlankEntry
+ },
+ {
+ 0x07,
+ L"Root Complex Event Collector",
+ PCIBlankEntry
+ },
{
0x80,
L"Other system peripheral",
@@ -609,8 +715,8 @@ PCI_CLASS_ENTRY PCISubClass_0b[] = {
PCI_CLASS_ENTRY PCISubClass_0c[] = {
{
0x00,
- L"Firewire(IEEE 1394)",
- PCIPIFClass_0c03
+ L"IEEE 1394",
+ PCIPIFClass_0c00
},
{
0x01,
@@ -625,7 +731,7 @@ PCI_CLASS_ENTRY PCISubClass_0c[] = {
{
0x03,
L"USB",
- PCIPIFClass_0c00
+ PCIPIFClass_0c03
},
{
0x04,
@@ -637,6 +743,26 @@ PCI_CLASS_ENTRY PCISubClass_0c[] = {
L"System Management Bus",
PCIBlankEntry
},
+ {
+ 0x06,
+ L"InfiniBand",
+ PCIBlankEntry
+ },
+ {
+ 0x07,
+ L"IPMI",
+ PCIPIFClass_0c07
+ },
+ {
+ 0x08,
+ L"SERCOS Interface Standard (IEC 61491)",
+ PCIBlankEntry
+ },
+ {
+ 0x09,
+ L"CANbus",
+ PCIBlankEntry
+ },
{
0x80,
L"Other bus type",
@@ -657,14 +783,34 @@ PCI_CLASS_ENTRY PCISubClass_0d[] = {
},
{
0x01,
- L"Consumer IR controller",
- PCIBlankEntry
+ L"",
+ PCIPIFClass_0d01
},
{
0x10,
L"RF controller",
PCIBlankEntry
},
+ {
+ 0x11,
+ L"Bluetooth",
+ PCIBlankEntry
+ },
+ {
+ 0x12,
+ L"Broadband",
+ PCIBlankEntry
+ },
+ {
+ 0x20,
+ L"Ethernet (802.11a - 5 GHz)",
+ PCIBlankEntry
+ },
+ {
+ 0x21,
+ L"Ethernet (802.11b - 2.4 GHz)",
+ PCIBlankEntry
+ },
{
0x80,
L"Other type of wireless controller",
@@ -692,25 +838,30 @@ PCI_CLASS_ENTRY PCISubClass_0e[] = {
PCI_CLASS_ENTRY PCISubClass_0f[] = {
{
- 0x00,
+ 0x01,
L"TV",
PCIBlankEntry
},
{
- 0x01,
+ 0x02,
L"Audio",
PCIBlankEntry
},
{
- 0x02,
+ 0x03,
L"Voice",
PCIBlankEntry
},
{
- 0x03,
+ 0x04,
L"Data",
PCIBlankEntry
},
+ {
+ 0x80,
+ L"Other satellite communication controller",
+ PCIBlankEntry
+ },
{
0x00,
NULL,
@@ -747,6 +898,21 @@ PCI_CLASS_ENTRY PCISubClass_11[] = {
L"DPIO modules",
PCIBlankEntry
},
+ {
+ 0x01,
+ L"Performance Counters",
+ PCIBlankEntry
+ },
+ {
+ 0x10,
+ L"Communications synchronization plus time and frequency test/measurement ",
+ PCIBlankEntry
+ },
+ {
+ 0x20,
+ L"Management card",
+ PCIBlankEntry
+ },
{
0x80,
L"Other DAQ & SP controllers",
@@ -759,9 +925,68 @@ PCI_CLASS_ENTRY PCISubClass_11[] = {
}
};
+PCI_CLASS_ENTRY PCISubClass_12[] = {
+ {
+ 0x00,
+ L"Processing Accelerator",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCISubClass_13[] = {
+ {
+ 0x00,
+ L"Non-Essential Instrumentation Function",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
//
// Programming Interface entries
//
+PCI_CLASS_ENTRY PCIPIFClass_0100[] = {
+ {
+ 0x00,
+ L"SCSI controller",
+ PCIBlankEntry
+ },
+ {
+ 0x11,
+ L"SCSI storage device SOP using PQI",
+ PCIBlankEntry
+ },
+ {
+ 0x12,
+ L"SCSI controller SOP using PQI",
+ PCIBlankEntry
+ },
+ {
+ 0x13,
+ L"SCSI storage device and controller SOP using PQI",
+ PCIBlankEntry
+ },
+ {
+ 0x21,
+ L"SCSI storage device SOP using NVMe",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
{
0x00,
@@ -930,6 +1155,106 @@ PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
}
};
+PCI_CLASS_ENTRY PCIPIFClass_0105[] = {
+ {
+ 0x20,
+ L"Single stepping",
+ PCIBlankEntry
+ },
+ {
+ 0x30,
+ L"Continuous operation",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0106[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"AHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x02,
+ L"Serial Storage Bus",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0107[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"Obsolete",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0108[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"NVMHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x02,
+ L"NVM Express",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0109[] = {
+ {
+ 0x00,
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"UFSHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
PCI_CLASS_ENTRY PCIPIFClass_0300[] = {
{
0x00,
@@ -966,6 +1291,42 @@ PCI_CLASS_ENTRY PCIPIFClass_0604[] = {
}
};
+PCI_CLASS_ENTRY PCIPIFClass_0609[] = {
+ {
+ 0x40,
+ L"Primary PCI bus side facing the system host processor",
+ PCIBlankEntry
+ },
+ {
+ 0x80,
+ L"Secondary PCI bus side facing the system host processor",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_060b[] = {
+ {
+ 0x00,
+ L"Custom",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"ASI-SIG Defined Portal",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
PCI_CLASS_ENTRY PCIPIFClass_0700[] = {
{
0x00,
@@ -1198,12 +1559,40 @@ PCI_CLASS_ENTRY PCIPIFClass_0904[] = {
PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
{
0x00,
- L"Universal Host Controller spec",
+ L"",
+ PCIBlankEntry
+ },
+ {
+ 0x10,
+ L"Using 1394 OpenHCI spec",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
+ {
+ 0x00,
+ L"UHCI",
PCIBlankEntry
},
{
0x10,
- L"Open Host Controller spec",
+ L"OHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x20,
+ L"EHCI",
+ PCIBlankEntry
+ },
+ {
+ 0x30,
+ L"xHCI",
PCIBlankEntry
},
{
@@ -1223,15 +1612,38 @@ PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
}
};
-PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
+PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {
{
0x00,
- L"",
+ L"SMIC",
+ PCIBlankEntry
+ },
+ {
+ 0x01,
+ L"Keyboard Controller Style",
+ PCIBlankEntry
+ },
+ {
+ 0x02,
+ L"Block Transfer",
+ PCIBlankEntry
+ },
+ {
+ 0x00,
+ NULL,
+ /* null string ends the list */NULL
+ }
+};
+
+PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {
+ {
+ 0x00,
+ L"Consumer IR controller",
PCIBlankEntry
},
{
0x10,
- L"Using 1394 OpenHCI spec",
+ L"UWB Radio controller",
PCIBlankEntry
},
{
@@ -1378,7 +1790,7 @@ PciGetClassStrings (
Print strings that represent PCI device class, subclass and programmed I/F.
@param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
- configuation space.
+ configuration space.
@param[in] IncludePIF If the printed string should include the programming I/F part
**/
VOID
@@ -1391,9 +1803,9 @@ PciPrintClassCode (
PCI_CLASS_STRINGS ClassStrings;
ClassCode = 0;
- ClassCode |= ClassCodePtr[0];
- ClassCode |= (ClassCodePtr[1] << 8);
- ClassCode |= (ClassCodePtr[2] << 16);
+ ClassCode |= (UINT32)ClassCodePtr[0];
+ ClassCode |= (UINT32)(ClassCodePtr[1] << 8);
+ ClassCode |= (UINT32)(ClassCodePtr[2] << 16);
//
// Get name from class code
@@ -1492,6 +1904,7 @@ PciGetNextBusRange (
@param[in] ConfigSpace Data in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
+ @param[in] EnhancedDump The print format for the dump data.
@retval EFI_SUCCESS The command completed successfully.
**/
@@ -1618,11 +2031,12 @@ PciExplainBridgeControl (
/**
Print each capability structure.
- @param[in] IoDev The pointer to the deivce.
- @param[in] Address The address to start at.
- @param[in] CapPtr The offset from the address.
+ @param[in] IoDev The pointer to the deivce.
+ @param[in] Address The address to start at.
+ @param[in] CapPtr The offset from the address.
+ @param[in] EnhancedDump The print format for the dump data.
- @retval EFI_SUCCESS The operation was successful.
+ @retval EFI_SUCCESS The operation was successful.
**/
EFI_STATUS
PciExplainCapabilityStruct (
@@ -1635,9 +2049,13 @@ PciExplainCapabilityStruct (
/**
Display Pcie device structure.
- @param[in] IoDev The pointer to the root pci protocol.
- @param[in] Address The Address to start at.
- @param[in] CapabilityPtr The offset from the address to start.
+ @param[in] IoDev The pointer to the root pci protocol.
+ @param[in] Address The Address to start at.
+ @param[in] CapabilityPtr The offset from the address to start.
+ @param[in] EnhancedDump The print format for the dump data.
+
+ @retval EFI_SUCCESS The command completed successfully.
+ @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted.
**/
EFI_STATUS
PciExplainPciExpress (
@@ -1656,7 +2074,7 @@ PciExplainPciExpress (
**/
EFI_STATUS
ExplainPcieCapReg (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1668,7 +2086,7 @@ ExplainPcieCapReg (
**/
EFI_STATUS
ExplainPcieDeviceCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1680,7 +2098,7 @@ ExplainPcieDeviceCap (
**/
EFI_STATUS
ExplainPcieDeviceControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1692,7 +2110,7 @@ ExplainPcieDeviceControl (
**/
EFI_STATUS
ExplainPcieDeviceStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1704,7 +2122,7 @@ ExplainPcieDeviceStatus (
**/
EFI_STATUS
ExplainPcieLinkCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1716,7 +2134,7 @@ ExplainPcieLinkCap (
**/
EFI_STATUS
ExplainPcieLinkControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1728,7 +2146,7 @@ ExplainPcieLinkControl (
**/
EFI_STATUS
ExplainPcieLinkStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1740,7 +2158,7 @@ ExplainPcieLinkStatus (
**/
EFI_STATUS
ExplainPcieSlotCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1752,7 +2170,7 @@ ExplainPcieSlotCap (
**/
EFI_STATUS
ExplainPcieSlotControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1764,7 +2182,7 @@ ExplainPcieSlotControl (
**/
EFI_STATUS
ExplainPcieSlotStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1776,7 +2194,7 @@ ExplainPcieSlotStatus (
**/
EFI_STATUS
ExplainPcieRootControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1788,7 +2206,7 @@ ExplainPcieRootControl (
**/
EFI_STATUS
ExplainPcieRootCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
/**
@@ -1800,10 +2218,10 @@ ExplainPcieRootCap (
**/
EFI_STATUS
ExplainPcieRootStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
);
-typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);
+typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);
typedef enum {
FieldWidthUINT8,
@@ -2077,7 +2495,7 @@ ShellCommandRunPci (
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
if (EFI_ERROR(Status)) {
if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);
FreePool(ProblemParam);
ShellStatus = SHELL_INVALID_PARAMETER;
} else {
@@ -2086,18 +2504,18 @@ ShellCommandRunPci (
} else {
if (ShellCommandLineGetCount(Package) == 2) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
if (ShellCommandLineGetCount(Package) > 4) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s");
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
@@ -2109,7 +2527,7 @@ ShellCommandRunPci (
HandleBufSize = sizeof (EFI_HANDLE);
HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);
if (HandleBuf == NULL) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_OUT_OF_RESOURCES;
goto Done;
}
@@ -2125,7 +2543,7 @@ ShellCommandRunPci (
if (Status == EFI_BUFFER_TOO_SMALL) {
HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);
if (HandleBuf == NULL) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_OUT_OF_RESOURCES;
goto Done;
}
@@ -2140,7 +2558,7 @@ ShellCommandRunPci (
}
if (EFI_ERROR (Status)) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_NOT_FOUND;
goto Done;
}
@@ -2176,7 +2594,7 @@ ShellCommandRunPci (
&Descriptors
);
if (EFI_ERROR (Status)) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_NOT_FOUND;
goto Done;
}
@@ -2189,7 +2607,7 @@ ShellCommandRunPci (
Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
if (EFI_ERROR (Status)) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_NOT_FOUND;
goto Done;
}
@@ -2313,7 +2731,7 @@ ShellCommandRunPci (
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
Segment = (UINT16) RetVal;
} else {
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
@@ -2331,13 +2749,13 @@ ShellCommandRunPci (
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
Bus = (UINT16) RetVal;
} else {
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
if (Bus > MAX_BUS_NUMBER) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
@@ -2350,13 +2768,13 @@ ShellCommandRunPci (
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
Device = (UINT16) RetVal;
} else {
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
if (Device > MAX_DEVICE_NUMBER){
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
@@ -2370,13 +2788,13 @@ ShellCommandRunPci (
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {
Func = (UINT16) RetVal;
} else {
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
if (Func > MAX_FUNCTION_NUMBER){
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);
ShellStatus = SHELL_INVALID_PARAMETER;
goto Done;
}
@@ -2396,7 +2814,7 @@ ShellCommandRunPci (
if (EFI_ERROR (Status)) {
ShellPrintHiiEx(
- -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,
+ -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci",
Segment,
Bus
);
@@ -2414,7 +2832,7 @@ ShellCommandRunPci (
);
if (EFI_ERROR (Status)) {
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");
ShellStatus = SHELL_ACCESS_DENIED;
goto Done;
}
@@ -2660,6 +3078,7 @@ PciGetNextBusRange (
@param[in] ConfigSpace Data in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
+ @param[in] EnhancedDump The print format for the dump data.
@retval EFI_SUCCESS The command completed successfully.
**/
@@ -3790,9 +4209,10 @@ PciExplainBridgeControl (
/**
Print each capability structure.
- @param[in] IoDev The pointer to the deivce.
- @param[in] Address The address to start at.
- @param[in] CapPtr The offset from the address.
+ @param[in] IoDev The pointer to the deivce.
+ @param[in] Address The address to start at.
+ @param[in] CapPtr The offset from the address.
+ @param[in] EnhancedDump The print format for the dump data.
@retval EFI_SUCCESS The operation was successful.
**/
@@ -3845,7 +4265,7 @@ PciExplainCapabilityStruct (
**/
EFI_STATUS
ExplainPcieCapReg (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieCapReg;
@@ -3893,7 +4313,7 @@ ExplainPcieCapReg (
**/
EFI_STATUS
ExplainPcieDeviceCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieCapReg;
@@ -3982,7 +4402,7 @@ ExplainPcieDeviceCap (
**/
EFI_STATUS
ExplainPcieDeviceControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieCapReg;
@@ -4059,7 +4479,7 @@ ExplainPcieDeviceControl (
**/
EFI_STATUS
ExplainPcieDeviceStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieDeviceStatus;
@@ -4101,7 +4521,7 @@ ExplainPcieDeviceStatus (
**/
EFI_STATUS
ExplainPcieLinkCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT32 PcieLinkCap;
@@ -4192,7 +4612,7 @@ ExplainPcieLinkCap (
**/
EFI_STATUS
ExplainPcieLinkControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieLinkControl;
@@ -4263,7 +4683,7 @@ ExplainPcieLinkControl (
**/
EFI_STATUS
ExplainPcieLinkStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieLinkStatus;
@@ -4324,7 +4744,7 @@ ExplainPcieLinkStatus (
**/
EFI_STATUS
ExplainPcieSlotCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT32 PcieSlotCap;
@@ -4392,7 +4812,7 @@ ExplainPcieSlotCap (
**/
EFI_STATUS
ExplainPcieSlotControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieSlotControl;
@@ -4456,7 +4876,7 @@ ExplainPcieSlotControl (
**/
EFI_STATUS
ExplainPcieSlotStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieSlotStatus;
@@ -4517,7 +4937,7 @@ ExplainPcieSlotStatus (
**/
EFI_STATUS
ExplainPcieRootControl (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieRootControl;
@@ -4557,7 +4977,7 @@ ExplainPcieRootControl (
**/
EFI_STATUS
ExplainPcieRootCap (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT16 PcieRootCap;
@@ -4581,7 +5001,7 @@ ExplainPcieRootCap (
**/
EFI_STATUS
ExplainPcieRootStatus (
- IN PCIE_CAP_STURCTURE *PciExpressCap
+ IN PCIE_CAP_STRUCTURE *PciExpressCap
)
{
UINT32 PcieRootStatus;
@@ -5042,6 +5462,220 @@ PrintInterpretedExtendedCompatibilityAer (
return (EFI_SUCCESS);
}
+/**
+ Function to interpret and print out the multicast structure
+
+ @param[in] HeaderAddress The Address of this capability header.
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
+**/
+EFI_STATUS
+EFIAPI
+PrintInterpretedExtendedCompatibilityMulticast (
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
+ IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr
+ )
+{
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;
+
+ ShellPrintHiiEx(
+ -1, -1, NULL,
+ STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST),
+ gShellDebug1HiiHandle,
+ Header->MultiCastCapability,
+ Header->MulticastControl,
+ Header->McBaseAddress,
+ Header->McReceiveAddress,
+ Header->McBlockAll,
+ Header->McBlockUntranslated,
+ Header->McOverlayBar
+ );
+
+ DumpHex (
+ 4,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),
+ (VOID *) (HeaderAddress)
+ );
+
+ return (EFI_SUCCESS);
+}
+
+/**
+ Function to interpret and print out the virtual channel and multi virtual channel structure
+
+ @param[in] HeaderAddress The Address of this capability header.
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.
+**/
+EFI_STATUS
+EFIAPI
+PrintInterpretedExtendedCompatibilityVirtualChannel (
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
+ )
+{
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;
+ UINT32 ItemCount;
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;
+
+ ShellPrintHiiEx(
+ -1, -1, NULL,
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE),
+ gShellDebug1HiiHandle,
+ Header->ExtendedVcCount,
+ Header->PortVcCapability1,
+ Header->PortVcCapability2,
+ Header->VcArbTableOffset,
+ Header->PortVcControl,
+ Header->PortVcStatus
+ );
+ for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {
+ CapabilityItem = &Header->Capability[ItemCount];
+ ShellPrintHiiEx(
+ -1, -1, NULL,
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM),
+ gShellDebug1HiiHandle,
+ ItemCount+1,
+ CapabilityItem->VcResourceCapability,
+ CapabilityItem->PortArbTableOffset,
+ CapabilityItem->VcResourceControl,
+ CapabilityItem->VcResourceStatus
+ );
+ }
+
+ DumpHex (
+ 4,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),
+ (VOID *) (HeaderAddress)
+ );
+
+ return (EFI_SUCCESS);
+}
+
+/**
+ Function to interpret and print out the resizeable bar structure
+
+ @param[in] HeaderAddress The Address of this capability header.
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.
+**/
+EFI_STATUS
+EFIAPI
+PrintInterpretedExtendedCompatibilityResizeableBar (
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
+ )
+{
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;
+ UINT32 ItemCount;
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;
+
+ for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {
+ ShellPrintHiiEx(
+ -1, -1, NULL,
+ STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR),
+ gShellDebug1HiiHandle,
+ ItemCount+1,
+ Header->Capability[ItemCount].ResizableBarCapability,
+ Header->Capability[ItemCount].ResizableBarControl
+ );
+ }
+
+ DumpHex (
+ 4,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
+ (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),
+ (VOID *) (HeaderAddress)
+ );
+
+ return (EFI_SUCCESS);
+}
+
+/**
+ Function to interpret and print out the TPH structure
+
+ @param[in] HeaderAddress The Address of this capability header.
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.
+**/
+EFI_STATUS
+EFIAPI
+PrintInterpretedExtendedCompatibilityTph (
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress
+ )
+{
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;
+
+ ShellPrintHiiEx(
+ -1, -1, NULL,
+ STRING_TOKEN (STR_PCI_EXT_CAP_TPH),
+ gShellDebug1HiiHandle,
+ Header->TphRequesterCapability,
+ Header->TphRequesterControl
+ );
+ DumpHex (
+ 8,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),
+ GET_TPH_TABLE_SIZE(Header),
+ (VOID *)Header->TphStTable
+ );
+
+ DumpHex (
+ 4,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),
+ (VOID *) (HeaderAddress)
+ );
+
+ return (EFI_SUCCESS);
+}
+
+/**
+ Function to interpret and print out the secondary PCIe capability structure
+
+ @param[in] HeaderAddress The Address of this capability header.
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
+**/
+EFI_STATUS
+EFIAPI
+PrintInterpretedExtendedCompatibilitySecondary (
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
+ IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr
+ )
+{
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;
+
+ ShellPrintHiiEx(
+ -1, -1, NULL,
+ STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY),
+ gShellDebug1HiiHandle,
+ Header->LinkControl3,
+ Header->LaneErrorStatus
+ );
+ DumpHex (
+ 8,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),
+ PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),
+ (VOID *)Header->EqualizationControl
+ );
+
+ DumpHex (
+ 4,
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),
+ (VOID *) (HeaderAddress)
+ );
+
+ return (EFI_SUCCESS);
+}
+
/**
Display Pcie extended capability details
@@ -5054,73 +5688,54 @@ EFIAPI
PrintPciExtendedCapabilityDetails(
IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,
IN CONST PCI_EXP_EXT_HDR *HeaderAddress,
- IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr
+ IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr
)
{
switch (HeaderAddress->CapabilityId){
case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:
return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:
return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:
return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:
return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:
return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:
return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:
return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:
return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:
return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:
return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:
return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);
- break;
case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:
return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);
- break;
-/**
case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:
case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:
- ASSERT(FALSE);
- break;
+ return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);
case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID:
-// use PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
- ASSERT(FALSE);
- break;
+ //
+ // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
+ //
+ return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:
- ASSERT(FALSE);
- break;
+ return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);
case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:
- ASSERT(FALSE);
- break;
+ return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);
case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:
- // use PciExpressCapPtr link capabilities register
- ASSERT(FALSE);
- break;
-//**/
+ return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);
default:
ShellPrintEx (-1, -1,
L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
HeaderAddress->CapabilityId
);
return EFI_SUCCESS;
- break;
};
}
@@ -5131,6 +5746,8 @@ PrintPciExtendedCapabilityDetails(
@param[in] IoDev The pointer to the root pci protocol.
@param[in] Address The Address to start at.
@param[in] CapabilityPtr The offset from the address to start.
+ @param[in] EnhancedDump The print format for the dump data.
+
**/
EFI_STATUS
PciExplainPciExpress (
@@ -5141,7 +5758,7 @@ PciExplainPciExpress (
)
{
- PCIE_CAP_STURCTURE PciExpressCap;
+ PCIE_CAP_STRUCTURE PciExpressCap;
EFI_STATUS Status;
UINT64 CapRegAddress;
UINT8 Bus;