X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FInclude%2FLibrary%2FLocalApicLib.h;h=fae780d5832a6f8fd01ad576b02ca31011cf2936;hp=d565dad96c48bf2d26c3ecfaf9fa30db813f4e03;hb=73152f19c0be7f31ee05f32878b515a296c487fa;hpb=ae40aef1fb4f5f34e5273b6fd5d4103bf6c7dd2d;ds=sidebyside

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index d565dad96c..fae780d583 100644
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -4,7 +4,7 @@
   Local APIC library assumes local APIC is enabled. It does not
   handles cases where local APIC is disabled.
 
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -21,6 +21,32 @@
 #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.
 #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.
 
+/**
+  Retrieve the base address of local APIC.
+
+  @return The base address of local APIC.
+
+**/
+UINTN
+EFIAPI
+GetLocalApicBaseAddress (
+  VOID
+  );
+
+/**
+  Set the base address of local APIC.
+
+  If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
+
+  @param[in] BaseAddress   Local APIC base address to be set.
+
+**/
+VOID
+EFIAPI
+SetLocalApicBaseAddress (
+  IN UINTN                BaseAddress
+  );
+
 /**
   Get the current local APIC mode.
 
@@ -42,6 +68,9 @@ GetApicMode (
   If the specified local APIC mode can't be set as current, then ASSERT.
 
   @param ApicMode APIC mode to be set.
+
+  @note  This API must not be called from an interrupt handler or SMI handler.
+         It may result in unpredictable behavior.
 **/
 VOID
 EFIAPI
@@ -52,7 +81,7 @@ SetApicMode (
 /**
   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
 
-  In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
+  In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, 
   the 32-bit local APIC ID is returned as initial APIC ID.
 
@@ -198,6 +227,20 @@ SendInitSipiSipiAllExcludingSelf (
   IN UINT32          StartupRoutine
   );
 
+/**
+  Initialize the state of the SoftwareEnable bit in the Local APIC
+  Spurious Interrupt Vector register.
+
+  @param  Enable  If TRUE, then set SoftwareEnable to 1
+                  If FALSE, then set SoftwareEnable to 0.
+
+**/
+VOID
+EFIAPI
+InitializeLocalApicSoftwareEnable (
+  IN BOOLEAN  Enable
+  );
+
 /**
   Programming Virtual Wire Mode.
 
@@ -212,6 +255,17 @@ ProgramVirtualWireMode (
   VOID
   );
 
+/**
+  Disable LINT0 & LINT1 interrupts.
+
+  This function sets the mask flag in the LVT LINT0 & LINT1 registers.
+**/
+VOID
+EFIAPI
+DisableLvtInterrupts (
+  VOID
+  );
+
 /**
   Read the initial count value from the init-count register.
 
@@ -308,5 +362,74 @@ SendApicEoi (
   VOID
   );
 
+/**
+  Get the 32-bit address that a device should use to send a Message Signaled 
+  Interrupt (MSI) to the Local APIC of the currently executing processor.
+
+  @return 32-bit address used to send an MSI to the Local APIC.
+**/
+UINT32
+EFIAPI    
+GetApicMsiAddress (
+  VOID
+  );
+    
+/**
+  Get the 64-bit data value that a device should use to send a Message Signaled 
+  Interrupt (MSI) to the Local APIC of the currently executing processor.
+
+  If Vector is not in range 0x10..0xFE, then ASSERT().
+  If DeliveryMode is not supported, then ASSERT().
+  
+  @param  Vector          The 8-bit interrupt vector associated with the MSI.  
+                          Must be in the range 0x10..0xFE
+  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI 
+                          is handled.  The only supported values are:
+                            0: LOCAL_APIC_DELIVERY_MODE_FIXED
+                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
+                            2: LOCAL_APIC_DELIVERY_MODE_SMI
+                            4: LOCAL_APIC_DELIVERY_MODE_NMI
+                            5: LOCAL_APIC_DELIVERY_MODE_INIT
+                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT
+                          
+  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  
+                          FALSE specifies an edge triggered interrupt.
+  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
+                          TRUE specifies a level triggered interrupt that active 
+                          when the interrupt line is asserted.
+                          FALSE specifies a level triggered interrupt that active 
+                          when the interrupt line is deasserted.
+
+  @return 64-bit data value used to send an MSI to the Local APIC.
+**/
+UINT64
+EFIAPI    
+GetApicMsiValue (
+  IN UINT8    Vector,
+  IN UINTN    DeliveryMode,
+  IN BOOLEAN  LevelTriggered,
+  IN BOOLEAN  AssertionLevel
+  );
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical
+  package  boundaries with respect to the number of logical processors
+  per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  );
+  
 #endif