X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FInclude%2FRegister%2FCpuid.h;h=5eb96505532d7ba0b9b62a5a782091495c375c29;hp=6730551ff8cd30bd6bbbb69443c44748308788b8;hb=14806d7b7dda38ddf7ff51e91cf412f1c6e10b58;hpb=28a7ddf0311f8557360b4f8d042e558b938f6e8c
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h
index 6730551ff8..5eb9650553 100644
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -1,51 +1,3536 @@
/** @file
-CPUID Definitions.
+ CPUID leaf definitions.
-CPUID definitions based on contents of the Intel(R) 64 and IA-32 Architectures
-Software Developer's Manual, Volume 2A, CPUID instruction.
+ Provides defines for CPUID leaf indexes. Data structures are provided for
+ registers returned by a CPUID leaf that contain one or more bit fields.
+ If a register returned is a single 32-bit value, then a data structure is
+ not provided for that register.
-Copyright (c) 2015, Intel Corporation. All rights reserved.
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License which accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
+ September 2016, CPUID instruction.
**/
#ifndef __CPUID_H__
#define __CPUID_H__
-//
-// Definitions for CPUID instruction
-//
-#define CPUID_SIGNATURE 0x0
+/**
+ CPUID Signature Information
+
+ @param EAX CPUID_SIGNATURE (0x00)
+
+ @retval EAX Returns the highest value the CPUID instruction recognizes for
+ returning basic processor information. The value is returned is
+ processor specific.
+ @retval EBX First 4 characters of a vendor identification string.
+ @retval ECX Last 4 characters of a vendor identification string.
+ @retval EDX Middle 4 characters of a vendor identification string.
+
+ Example usage
+ @code
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+
+ AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
+ @endcode
+**/
+#define CPUID_SIGNATURE 0x00
+
+///
+/// @{ CPUID signature values returned by Intel processors
+///
+#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
+#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
+#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
+///
+/// @}
+///
+
+
+/**
+ CPUID Version Information
+
+ @param EAX CPUID_VERSION_INFO (0x01)
+
+ @retval EAX Returns Model, Family, Stepping Information described by the
+ type CPUID_VERSION_INFO_EAX.
+ @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
+ the type CPUID_VERSION_INFO_EBX.
+ @retval ECX CPU Feature Information described by the type
+ CPUID_VERSION_INFO_ECX.
+ @retval EDX CPU Feature Information described by the type
+ CPUID_VERSION_INFO_EDX.
+
+ Example usage
+ @code
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_EBX Ebx;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+
+ AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+ @endcode
+**/
+#define CPUID_VERSION_INFO 0x01
+
+/**
+ CPUID Version Information returned in EAX for CPUID leaf
+ #CPUID_VERSION_INFO.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
+ UINT32 Model:4; ///< [Bits 7:4] Model
+ UINT32 FamilyId:4; ///< [Bits 11:8] Family
+ UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
+ UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
+ UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
+ UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
+ UINT32 Reserved2:4; ///< Reserved
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_VERSION_INFO_EAX;
+
+///
+/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
+///
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
+///
+/// @}
+///
+
+/**
+ CPUID Version Information returned in EBX for CPUID leaf
+ #CPUID_VERSION_INFO.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Provides an entry into a brand string table that contains
+ /// brand strings for IA-32 processors.
+ ///
+ UINT32 BrandIndex:8;
+ ///
+ /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
+ /// and CLFLUSHOPT instructions in 8-byte increments. This field was
+ /// introduced in the Pentium 4 processor.
+ ///
+ UINT32 CacheLineSize:8;
+ ///
+ /// [Bits 23:16] Maximum number of addressable IDs for logical processors
+ /// in this physical package.
+ ///
+ /// @note
+ /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
+ /// the number of unique initial APICIDs reserved for addressing different
+ /// logical processors in a physical package. This field is only valid if
+ /// CPUID.1.EDX.HTT[bit 28]= 1.
+ ///
+ UINT32 MaximumAddressableIdsForLogicalProcessors:8;
+ ///
+ /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
+ /// processor during power up. This field was introduced in the Pentium 4
+ /// processor.
+ ///
+ UINT32 InitialLocalApicId:8;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_VERSION_INFO_EBX;
+
+/**
+ CPUID Version Information returned in ECX for CPUID leaf
+ #CPUID_VERSION_INFO.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
+ /// processor supports this technology
+ ///
+ UINT32 SSE3:1;
+ ///
+ /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
+ /// instruction. Carryless Multiplication
+ ///
+ UINT32 PCLMULQDQ:1;
+ ///
+ /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
+ /// DS area using 64-bit layout.
+ ///
+ UINT32 DTES64:1;
+ ///
+ /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
+ /// this feature.
+ ///
+ UINT32 MONITOR:1;
+ ///
+ /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
+ /// supports the extensions to the Debug Store feature to allow for branch
+ /// message storage qualified by CPL
+ ///
+ UINT32 DS_CPL:1;
+ ///
+ /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
+ /// processor supports this technology.
+ ///
+ UINT32 VMX:1;
+ ///
+ /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
+ /// supports this technology
+ ///
+ UINT32 SMX:1;
+ ///
+ /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
+ /// that the processor supports this technology
+ ///
+ UINT32 EIST:1;
+ ///
+ /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
+ /// supports this technology
+ ///
+ UINT32 TM2:1;
+ ///
+ /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
+ /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
+ /// extensions are not present in the processor.
+ ///
+ UINT32 SSSE3:1;
+ ///
+ /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
+ /// can be set to either adaptive mode or shared mode. A value of 0 indicates
+ /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
+ /// Bit 24 (L1 Data Cache Context Mode) for details
+ ///
+ UINT32 CNXT_ID:1;
+ ///
+ /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
+ /// MSR for silicon debug
+ ///
+ UINT32 SDBG:1;
+ ///
+ /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
+ /// Add) extensions using YMM state.
+ ///
+ UINT32 FMA:1;
+ ///
+ /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
+ /// is available.
+ ///
+ UINT32 CMPXCHG16B:1;
+ ///
+ /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
+ /// supports changing IA32_MISC_ENABLE[Bit 23].
+ ///
+ UINT32 xTPR_Update_Control:1;
+ ///
+ /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
+ /// processor supports the performance and debug feature indication MSR
+ /// IA32_PERF_CAPABILITIES.
+ ///
+ UINT32 PDCM:1;
+ UINT32 Reserved:1;
+ ///
+ /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
+ /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
+ ///
+ UINT32 PCID:1;
+ ///
+ /// [Bit 18] A value of 1 indicates the processor supports the ability to
+ /// prefetch data from a memory mapped device. Direct Cache Access.
+ ///
+ UINT32 DCA:1;
+ ///
+ /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
+ ///
+ UINT32 SSE4_1:1;
+ ///
+ /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
+ ///
+ UINT32 SSE4_2:1;
+ ///
+ /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
+ /// feature.
+ ///
+ UINT32 x2APIC:1;
+ ///
+ /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
+ /// instruction.
+ ///
+ UINT32 MOVBE:1;
+ ///
+ /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
+ /// instruction.
+ ///
+ UINT32 POPCNT:1;
+ ///
+ /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
+ /// supports one-shot operation using a TSC deadline value.
+ ///
+ UINT32 TSC_Deadline:1;
+ ///
+ /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
+ /// instruction extensions.
+ ///
+ UINT32 AESNI:1;
+ ///
+ /// [Bit 26] A value of 1 indicates that the processor supports the
+ /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
+ /// instructions, and XCR0.
+ ///
+ UINT32 XSAVE:1;
+ ///
+ /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
+ /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
+ /// processor extended state management using XSAVE/XRSTOR.
+ ///
+ UINT32 OSXSAVE:1;
+ ///
+ /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
+ /// extensions.
+ ///
+ UINT32 AVX:1;
+ ///
+ /// [Bit 29] A value of 1 indicates that processor supports 16-bit
+ /// floating-point conversion instructions.
+ ///
+ UINT32 F16C:1;
+ ///
+ /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
+ ///
+ UINT32 RDRAND:1;
+ ///
+ /// [Bit 31] Always returns 0.
+ ///
+ UINT32 NotUsed:1;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_VERSION_INFO_ECX;
+
+/**
+ CPUID Version Information returned in EDX for CPUID leaf
+ #CPUID_VERSION_INFO.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
+ ///
+ UINT32 FPU:1;
+ ///
+ /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
+ /// including CR4.VME for controlling the feature, CR4.PVI for protected
+ /// mode virtual interrupts, software interrupt indirection, expansion of
+ /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
+ /// EFLAGS.VIP flags.
+ ///
+ UINT32 VME:1;
+ ///
+ /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
+ /// CR4.DE for controlling the feature, and optional trapping of accesses to
+ /// DR4 and DR5.
+ ///
+ UINT32 DE:1;
+ ///
+ /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
+ /// including CR4.PSE for controlling the feature, the defined dirty bit in
+ /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
+ /// PDEs, and PTEs.
+ ///
+ UINT32 PSE:1;
+ ///
+ /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
+ /// including CR4.TSD for controlling privilege.
+ ///
+ UINT32 TSC:1;
+ ///
+ /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
+ /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
+ /// implementation dependent.
+ ///
+ UINT32 MSR:1;
+ ///
+ /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
+ /// bits are supported: extended page table entry formats, an extra level in
+ /// the page translation tables is defined, 2-MByte pages are supported
+ /// instead of 4 Mbyte pages if PAE bit is 1.
+ ///
+ UINT32 PAE:1;
+ ///
+ /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
+ /// Checks, including CR4.MCE for controlling the feature. This feature does
+ /// not define the model-specific implementations of machine-check error
+ /// logging, reporting, and processor shutdowns. Machine Check exception
+ /// handlers may have to depend on processor version to do model specific
+ /// processing of the exception, or test for the presence of the Machine
+ /// Check feature.
+ ///
+ UINT32 MCE:1;
+ ///
+ /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
+ /// instruction is supported (implicitly locked and atomic).
+ ///
+ UINT32 CX8:1;
+ ///
+ /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
+ /// Interrupt Controller (APIC), responding to memory mapped commands in the
+ /// physical address range FFFE0000H to FFFE0FFFH (by default - some
+ /// processors permit the APIC to be relocated).
+ ///
+ UINT32 APIC:1;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
+ /// and associated MSRs are supported.
+ ///
+ UINT32 SEP:1;
+ ///
+ /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
+ /// MSR contains feature bits that describe what memory types are supported,
+ /// how many variable MTRRs are supported, and whether fixed MTRRs are
+ /// supported.
+ ///
+ UINT32 MTRR:1;
+ ///
+ /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
+ /// entries that map a page, indicating TLB entries that are common to
+ /// different processes and need not be flushed. The CR4.PGE bit controls
+ /// this feature.
+ ///
+ UINT32 PGE:1;
+ ///
+ /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
+ /// Check Architecture of reporting machine errors is supported. The MCG_CAP
+ /// MSR contains feature bits describing how many banks of error reporting
+ /// MSRs are supported.
+ ///
+ UINT32 MCA:1;
+ ///
+ /// [Bit 15] Conditional Move Instructions. The conditional move instruction
+ /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
+ /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
+ ///
+ UINT32 CMOV:1;
+ ///
+ /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
+ /// feature augments the Memory Type Range Registers (MTRRs), allowing an
+ /// operating system to specify attributes of memory accessed through a
+ /// linear address on a 4KB granularity.
+ ///
+ UINT32 PAT:1;
+ ///
+ /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
+ /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
+ /// indicates that upper bits of the physical address of a 4-MByte page are
+ /// encoded in bits 20:13 of the page-directory entry. Such physical
+ /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
+ ///
+ UINT32 PSE_36:1;
+ ///
+ /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
+ /// processor identification number feature and the feature is enabled.
+ ///
+ UINT32 PSN:1;
+ ///
+ /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
+ ///
+ UINT32 CLFSH:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 21] Debug Store. The processor supports the ability to write debug
+ /// information into a memory resident buffer. This feature is used by the
+ /// branch trace store (BTS) and precise event-based sampling (PEBS)
+ /// facilities.
+ ///
+ UINT32 DS:1;
+ ///
+ /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
+ /// processor implements internal MSRs that allow processor temperature to
+ /// be monitored and processor performance to be modulated in predefined
+ /// duty cycles under software control.
+ ///
+ UINT32 ACPI:1;
+ ///
+ /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
+ /// technology.
+ ///
+ UINT32 MMX:1;
+ ///
+ /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
+ /// instructions are supported for fast save and restore of the floating
+ /// point context. Presence of this bit also indicates that CR4.OSFXSR is
+ /// available for an operating system to indicate that it supports the
+ /// FXSAVE and FXRSTOR instructions.
+ ///
+ UINT32 FXSR:1;
+ ///
+ /// [Bit 25] SSE. The processor supports the SSE extensions.
+ ///
+ UINT32 SSE:1;
+ ///
+ /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
+ ///
+ UINT32 SSE2:1;
+ ///
+ /// [Bit 27] Self Snoop. The processor supports the management of
+ /// conflicting memory types by performing a snoop of its own cache
+ /// structure for transactions issued to the bus.
+ ///
+ UINT32 SS:1;
+ ///
+ /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
+ /// indicates there is only a single logical processor in the package and
+ /// software should assume only a single APIC ID is reserved. A value of 1
+ /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
+ /// addressable IDs for logical processors in this package) is valid for the
+ /// package.
+ ///
+ UINT32 HTT:1;
+ ///
+ /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
+ /// automatic thermal control circuitry (TCC).
+ ///
+ UINT32 TM:1;
+ UINT32 Reserved3:1;
+ ///
+ /// [Bit 31] Pending Break Enable. The processor supports the use of the
+ /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
+ /// asserted) to signal the processor that an interrupt is pending and that
+ /// the processor should return to normal operation to handle the interrupt.
+ /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
+ ///
+ UINT32 PBE:1;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_VERSION_INFO_EDX;
+
+
+/**
+ CPUID Cache and TLB Information
+
+ @param EAX CPUID_CACHE_INFO (0x02)
+
+ @retval EAX Cache and TLB Information described by the type
+ CPUID_CACHE_INFO_CACHE_TLB.
+ CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
+ 0x01 and must be ignored. Only valid if
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+ @retval EBX Cache and TLB Information described by the type
+ CPUID_CACHE_INFO_CACHE_TLB. Only valid if
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+ @retval ECX Cache and TLB Information described by the type
+ CPUID_CACHE_INFO_CACHE_TLB. Only valid if
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+ @retval EDX Cache and TLB Information described by the type
+ CPUID_CACHE_INFO_CACHE_TLB. Only valid if
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+
+ Example usage
+ @code
+ CPUID_CACHE_INFO_CACHE_TLB Eax;
+ CPUID_CACHE_INFO_CACHE_TLB Ebx;
+ CPUID_CACHE_INFO_CACHE_TLB Ecx;
+ CPUID_CACHE_INFO_CACHE_TLB Edx;
+
+ AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+ @endcode
+
+ Cache Descriptor values
+
Value | Type | Description |
---|---|---|
0x00 | General | Null descriptor, this byte contains no information |
0x01 | TLB | Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries |
0x02 | TLB | Instruction TLB: 4 MByte pages, fully associative, 2 entries |
0x03 | TLB | Data TLB: 4 KByte pages, 4-way set associative, 64 entries |
0x04 | TLB | Data TLB: 4 MByte pages, 4-way set associative, 8 entries |
0x05 | TLB | Data TLB1: 4 MByte pages, 4-way set associative, 32 entries |
0x06 | Cache | 1st-level instruction cache: 8 KBytes, 4-way set associative, + 32 byte line size |
0x08 | Cache | 1st-level instruction cache: 16 KBytes, 4-way set associative, + 32 byte line size |
0x09 | Cache | 1st-level instruction cache: 32KBytes, 4-way set associative, + 64 byte line size |
0x0A | Cache | 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size |
0x0B | TLB | Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries |
0x0C | Cache | 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size |
0x0D | Cache | 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size |
0x0E | Cache | 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size |
0x1D | Cache | 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size |
0x21 | Cache | 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size |
0x22 | Cache | 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, + 2 lines per sector |
0x23 | Cache | 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x24 | Cache | 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size |
0x25 | Cache | 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x29 | Cache | 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x2C | Cache | 1st-level data cache: 32 KBytes, 8-way set associative, + 64 byte line size |
0x30 | Cache | 1st-level instruction cache: 32 KBytes, 8-way set associative, + 64 byte line size |
0x40 | Cache | No 2nd-level cache or, if processor contains a valid 2nd-level cache, + no 3rd-level cache |
0x41 | Cache | 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size |
0x42 | Cache | 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size |
0x43 | Cache | 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size |
0x44 | Cache | 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size |
0x45 | Cache | 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size |
0x46 | Cache | 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size |
0x47 | Cache | 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size |
0x48 | Cache | 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size |
0x49 | Cache | 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
+ (Intel Xeon processor MP, Family 0FH, Model 06H) + 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size |
0x4A | Cache | 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size |
0x4B | Cache | 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size |
0x4C | Cache | 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size |
0x4D | Cache | 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size |
0x4E | Cache | 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size |
0x4F | TLB | Instruction TLB: 4 KByte pages, 32 entries |
0x50 | TLB | Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries |
0x51 | TLB | Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries |
0x52 | TLB | Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries |
0x55 | TLB | Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries |
0x56 | TLB | Data TLB0: 4 MByte pages, 4-way set associative, 16 entries |
0x57 | TLB | Data TLB0: 4 KByte pages, 4-way associative, 16 entries |
0x59 | TLB | Data TLB0: 4 KByte pages, fully associative, 16 entries |
0x5A | TLB | Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries |
0x5B | TLB | Data TLB: 4 KByte and 4 MByte pages, 64 entries |
0x5C | TLB | Data TLB: 4 KByte and 4 MByte pages,128 entries |
0x5D | TLB | Data TLB: 4 KByte and 4 MByte pages,256 entries |
0x60 | Cache | 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size |
0x61 | TLB | Instruction TLB: 4 KByte pages, fully associative, 48 entries |
0x63 | TLB | Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, + 32 entries and a separate array with 1 GByte pages, 4-way set associative, + 4 entries |
0x64 | TLB | Data TLB: 4 KByte pages, 4-way set associative, 512 entries |
0x66 | Cache | 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size |
0x67 | Cache | 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size |
0x68 | Cache | 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size |
0x6A | Cache | uTLB: 4 KByte pages, 8-way set associative, 64 entries |
0x6B | Cache | DTLB: 4 KByte pages, 8-way set associative, 256 entries |
0x6C | Cache | DTLB: 2M/4M pages, 8-way set associative, 128 entries |
0x6D | Cache | DTLB: 1 GByte pages, fully associative, 16 entries |
0x70 | Cache | Trace cache: 12 K-uop, 8-way set associative |
0x71 | Cache | Trace cache: 16 K-uop, 8-way set associative |
0x72 | Cache | Trace cache: 32 K-uop, 8-way set associative |
0x76 | TLB | Instruction TLB: 2M/4M pages, fully associative, 8 entries |
0x78 | Cache | 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size |
0x79 | Cache | 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x7A | Cache | 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x7B | Cache | 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x7C | Cache | 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, + 2 lines per sector |
0x7D | Cache | 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size |
0x7F | Cache | 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size |
0x80 | Cache | 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size |
0x82 | Cache | 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size |
0x83 | Cache | 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size |
0x84 | Cache | 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size |
0x85 | Cache | 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size |
0x86 | Cache | 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size |
0x87 | Cache | 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size |
0xA0 | DTLB | DTLB: 4k pages, fully associative, 32 entries |
0xB0 | TLB | Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries |
0xB1 | TLB | Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries |
0xB2 | TLB | Instruction TLB: 4KByte pages, 4-way set associative, 64 entries |
0xB3 | TLB | Data TLB: 4 KByte pages, 4-way set associative, 128 entries |
0xB4 | TLB | Data TLB1: 4 KByte pages, 4-way associative, 256 entries |
0xB5 | TLB | Instruction TLB: 4KByte pages, 8-way set associative, 64 entries |
0xB6 | TLB | Instruction TLB: 4KByte pages, 8-way set associative, + 128 entries |
0xBA | TLB | Data TLB1: 4 KByte pages, 4-way associative, 64 entries |
0xC0 | TLB | Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries |
0xC1 | STLB | Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, + 1024 entries |
0xC2 | DTLB | DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries |
0xC3 | STLB | Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, + 1536 entries. Also 1GBbyte pages, 4-way, 16 entries. |
0xC4 | DTLB | DTLB: 2M/4M Byte pages, 4-way associative, 32 entries |
0xCA | STLB | Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries |
0xD0 | Cache | 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size |
0xD1 | Cache | 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size |
0xD2 | Cache | 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size |
0xD6 | Cache | 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size |
0xD7 | Cache | 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size |
0xD8 | Cache | 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size |
0xDC | Cache | 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size |
0xDD | Cache | 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size |
0xDE | Cache | 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size |
0xE2 | Cache | 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size |
0xE3 | Cache | 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size |
0xE4 | Cache | 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size |
0xEA | Cache | 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size |
0xEB | Cache | 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size |
0xEC | Cache | 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size |
0xF0 | Prefetch | 64-Byte prefetching |
0xF1 | Prefetch | 128-Byte prefetching |
0xFF | General | CPUID leaf 2 does not report cache descriptor information, + use CPUID leaf 4 to query cache parameters |