X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FLibrary%2FBaseXApicLib%2FBaseXApicLib.c;h=5976403456f6d91d335321b58d44ac0821aa4529;hp=16dbd4be6ed47a4154e635d0734d74ee9e768c0e;hb=73152f19c0be7f31ee05f32878b515a296c487fa;hpb=bf73cc4bbcdaa76bad31875bce6ff9dd0d91eb09
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 16dbd4be6e..5976403456 100644
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
This local APIC library instance supports xAPIC mode only.
- Copyright (c) 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -14,6 +14,8 @@
**/
+#include
+#include
#include
#include
@@ -27,6 +29,94 @@
// Library internal functions
//
+/**
+ Determine if the CPU supports the Local APIC Base Address MSR.
+
+ @retval TRUE The CPU supports the Local APIC Base Address MSR.
+ @retval FALSE The CPU does not support the Local APIC Base Address MSR.
+
+**/
+BOOLEAN
+LocalApicBaseAddressMsrSupported (
+ VOID
+ )
+{
+ UINT32 RegEax;
+ UINTN FamilyId;
+
+ AsmCpuid (1, &RegEax, NULL, NULL, NULL);
+ FamilyId = BitFieldRead32 (RegEax, 8, 11);
+ if (FamilyId == 0x04 || FamilyId == 0x05) {
+ //
+ // CPUs with a FamilyId of 0x04 or 0x05 do not support the
+ // Local APIC Base Address MSR
+ //
+ return FALSE;
+ }
+ return TRUE;
+}
+
+/**
+ Retrieve the base address of local APIC.
+
+ @return The base address of local APIC.
+
+**/
+UINTN
+EFIAPI
+GetLocalApicBaseAddress (
+ VOID
+ )
+{
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
+
+ if (!LocalApicBaseAddressMsrSupported ()) {
+ //
+ // If CPU does not support Local APIC Base Address MSR, then retrieve
+ // Local APIC Base Address from PCD
+ //
+ return PcdGet32 (PcdCpuLocalApicBaseAddress);
+ }
+
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
+}
+
+/**
+ Set the base address of local APIC.
+
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
+
+ @param[in] BaseAddress Local APIC base address to be set.
+
+**/
+VOID
+EFIAPI
+SetLocalApicBaseAddress (
+ IN UINTN BaseAddress
+ )
+{
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
+
+ ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
+
+ if (!LocalApicBaseAddressMsrSupported ()) {
+ //
+ // Ignore set request if the CPU does not support APIC Base Address MSR
+ //
+ return;
+ }
+
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+
+ ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
+}
+
/**
Read from a local APIC register.
@@ -49,7 +139,7 @@ ReadLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
- return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
+ return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
}
/**
@@ -76,7 +166,7 @@ WriteLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
+ MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
}
/**
@@ -94,18 +184,47 @@ SendIpi (
)
{
LOCAL_APIC_ICR_LOW IcrLowReg;
+ UINT32 IcrHigh;
+ BOOLEAN InterruptState;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
ASSERT (ApicId <= 0xff);
+ InterruptState = SaveAndDisableInterrupts ();
+
+ //
+ // Save existing contents of ICR high 32 bits
+ //
+ IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);
+
+ //
+ // Wait for DeliveryStatus clear in case a previous IPI
+ // is still being sent
+ //
+ do {
+ IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
+ } while (IcrLowReg.Bits.DeliveryStatus != 0);
+
//
// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
//
WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
+
+ //
+ // Wait for DeliveryStatus clear again
+ //
do {
IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
} while (IcrLowReg.Bits.DeliveryStatus != 0);
+
+ //
+ // And restore old contents of ICR high
+ //
+ WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
+
+ SetInterruptState (InterruptState);
+
}
//
@@ -128,14 +247,19 @@ GetApicMode (
{
DEBUG_CODE (
{
- MSR_IA32_APIC_BASE ApicBaseMsr;
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
//
- // Local APIC should have been enabled
+ // Check to see if the CPU supports the APIC Base Address MSR
//
- ASSERT (ApicBaseMsr.Bits.En != 0);
- ASSERT (ApicBaseMsr.Bits.Extd == 0);
+ if (LocalApicBaseAddressMsrSupported ()) {
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ //
+ // Local APIC should have been enabled
+ //
+ ASSERT (ApicBaseMsr.Bits.EN != 0);
+ ASSERT (ApicBaseMsr.Bits.EXTD == 0);
+ }
}
);
return LOCAL_APIC_MODE_XAPIC;
@@ -148,6 +272,9 @@ GetApicMode (
If the specified local APIC mode can't be set as current, then ASSERT.
@param ApicMode APIC mode to be set.
+
+ @note This API must not be called from an interrupt handler or SMI handler.
+ It may result in unpredictable behavior.
**/
VOID
EFIAPI
@@ -162,7 +289,7 @@ SetApicMode (
/**
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
- In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
+ In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
the 32-bit local APIC ID is returned as initial APIC ID.
@@ -174,10 +301,27 @@ GetInitialApicId (
VOID
)
{
+ UINT32 ApicId;
+ UINT32 MaxCpuIdIndex;
UINT32 RegEbx;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
+ //
+ // Get the max index of basic CPUID
+ //
+ AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+ //
+ // If CPUID Leaf B is supported,
+ // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
+ // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
+ //
+ if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
+ return ApicId;
+ }
+
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
return RegEbx >> 24;
}
@@ -196,12 +340,79 @@ GetApicId (
UINT32 ApicId;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
-
- ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
- ApicId >>= 24;
+
+ if ((ApicId = GetInitialApicId ()) < 0x100) {
+ //
+ // If the initial local APIC ID is less 0x100, read APIC ID from
+ // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
+ //
+ ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
+ ApicId >>= 24;
+ }
return ApicId;
}
+/**
+ Get the value of the local APIC version register.
+
+ @return the value of the local APIC version register.
+**/
+UINT32
+EFIAPI
+GetApicVersion (
+ VOID
+ )
+{
+ return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
+}
+
+/**
+ Send a Fixed IPI to a specified target processor.
+
+ This function returns after the IPI has been accepted by the target processor.
+
+ @param ApicId The local APIC ID of the target processor.
+ @param Vector The vector number of the interrupt being sent.
+**/
+VOID
+EFIAPI
+SendFixedIpi (
+ IN UINT32 ApicId,
+ IN UINT8 Vector
+ )
+{
+ LOCAL_APIC_ICR_LOW IcrLow;
+
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
+ IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Vector = Vector;
+ SendIpi (IcrLow.Uint32, ApicId);
+}
+
+/**
+ Send a Fixed IPI to all processors excluding self.
+
+ This function returns after the IPI has been accepted by the target processors.
+
+ @param Vector The vector number of the interrupt being sent.
+**/
+VOID
+EFIAPI
+SendFixedIpiAllExcludingSelf (
+ IN UINT8 Vector
+ )
+{
+ LOCAL_APIC_ICR_LOW IcrLow;
+
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
+ IcrLow.Bits.Level = 1;
+ IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
+ IcrLow.Bits.Vector = Vector;
+ SendIpi (IcrLow.Uint32, 0);
+}
+
/**
Send a SMI IPI to a specified target processor.
@@ -309,7 +520,7 @@ SendInitSipiSipi (
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId);
- MicroSecondDelay (10);
+ MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
@@ -342,7 +553,7 @@ SendInitSipiSipiAllExcludingSelf (
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf ();
- MicroSecondDelay (10);
+ MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
@@ -353,6 +564,39 @@ SendInitSipiSipiAllExcludingSelf (
SendIpi (IcrLow.Uint32, 0);
}
+/**
+ Initialize the state of the SoftwareEnable bit in the Local APIC
+ Spurious Interrupt Vector register.
+
+ @param Enable If TRUE, then set SoftwareEnable to 1
+ If FALSE, then set SoftwareEnable to 0.
+
+**/
+VOID
+EFIAPI
+InitializeLocalApicSoftwareEnable (
+ IN BOOLEAN Enable
+ )
+{
+ LOCAL_APIC_SVR Svr;
+
+ //
+ // Set local APIC software-enabled bit.
+ //
+ Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
+ if (Enable) {
+ if (Svr.Bits.SoftwareEnable == 0) {
+ Svr.Bits.SoftwareEnable = 1;
+ WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
+ }
+ } else {
+ if (Svr.Bits.SoftwareEnable == 1) {
+ Svr.Bits.SoftwareEnable = 0;
+ WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
+ }
+ }
+}
+
/**
Programming Virtual Wire Mode.
@@ -381,43 +625,44 @@ ProgramVirtualWireMode (
//
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
//
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LINT0_VECTOR_OFFSET);
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
- WriteLocalApicReg (XAPIC_LINT0_VECTOR_OFFSET, Lint.Uint32);
+ WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
//
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
//
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LINT1_VECTOR_OFFSET);
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
- WriteLocalApicReg (XAPIC_LINT1_VECTOR_OFFSET, Lint.Uint32);
+ WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
}
/**
- Get the divide value from the DCR (Divide Configuration Register) by which
- the processor's bus clock is divided to form the time base for the APIC timer.
+ Disable LINT0 & LINT1 interrupts.
- @return The divide value is one of 1,2,4,8,16,32,64,128.
+ This function sets the mask flag in the LVT LINT0 & LINT1 registers.
**/
-UINTN
+VOID
EFIAPI
-GetApicTimerDivisor (
+DisableLvtInterrupts (
VOID
)
{
- UINT32 DivideValue;
- LOCAL_APIC_DCR Dcr;
+ LOCAL_APIC_LVT_LINT LvtLint;
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
- DivideValue = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
- DivideValue = (DivideValue + 1) & 0x7;
- return ((UINTN)1) << DivideValue;
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
+ LvtLint.Bits.Mask = 1;
+ WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
+
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
+ LvtLint.Bits.Mask = 1;
+ WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
}
/**
@@ -468,7 +713,6 @@ InitializeApicTimer (
IN UINT8 Vector
)
{
- LOCAL_APIC_SVR Svr;
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor;
@@ -476,9 +720,7 @@ InitializeApicTimer (
//
// Ensure local APIC is in software-enabled state.
//
- Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
- Svr.Bits.SoftwareEnable = 1;
- WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
+ InitializeLocalApicSoftwareEnable (TRUE);
//
// Program init-count register.
@@ -510,6 +752,56 @@ InitializeApicTimer (
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
+/**
+ Get the state of the local APIC timer.
+
+ This function will ASSERT if the local APIC is not software enabled.
+
+ @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
+ @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
+ @param Vector Return the timer interrupt vector number.
+**/
+VOID
+EFIAPI
+GetApicTimerState (
+ OUT UINTN *DivideValue OPTIONAL,
+ OUT BOOLEAN *PeriodicMode OPTIONAL,
+ OUT UINT8 *Vector OPTIONAL
+ )
+{
+ UINT32 Divisor;
+ LOCAL_APIC_DCR Dcr;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
+
+ //
+ // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
+ // Vector Register.
+ // This bit will be 1, if local APIC is software enabled.
+ //
+ ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
+
+ if (DivideValue != NULL) {
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
+ Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
+ Divisor = (Divisor + 1) & 0x7;
+ *DivideValue = ((UINTN)1) << Divisor;
+ }
+
+ if (PeriodicMode != NULL || Vector != NULL) {
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
+ if (PeriodicMode != NULL) {
+ if (LvtTimer.Bits.TimerMode == 1) {
+ *PeriodicMode = TRUE;
+ } else {
+ *PeriodicMode = FALSE;
+ }
+ }
+ if (Vector != NULL) {
+ *Vector = (UINT8) LvtTimer.Bits.Vector;
+ }
+ }
+}
+
/**
Enable the local APIC timer interrupt.
**/
@@ -572,3 +864,226 @@ SendApicEoi (
WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
}
+/**
+ Get the 32-bit address that a device should use to send a Message Signaled
+ Interrupt (MSI) to the Local APIC of the currently executing processor.
+
+ @return 32-bit address used to send an MSI to the Local APIC.
+**/
+UINT32
+EFIAPI
+GetApicMsiAddress (
+ VOID
+ )
+{
+ LOCAL_APIC_MSI_ADDRESS MsiAddress;
+
+ //
+ // Return address for an MSI interrupt to be delivered only to the APIC ID
+ // of the currently executing processor.
+ //
+ MsiAddress.Uint32 = 0;
+ MsiAddress.Bits.BaseAddress = 0xFEE;
+ MsiAddress.Bits.DestinationId = GetApicId ();
+ return MsiAddress.Uint32;
+}
+
+/**
+ Get the 64-bit data value that a device should use to send a Message Signaled
+ Interrupt (MSI) to the Local APIC of the currently executing processor.
+
+ If Vector is not in range 0x10..0xFE, then ASSERT().
+ If DeliveryMode is not supported, then ASSERT().
+
+ @param Vector The 8-bit interrupt vector associated with the MSI.
+ Must be in the range 0x10..0xFE
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
+ is handled. The only supported values are:
+ 0: LOCAL_APIC_DELIVERY_MODE_FIXED
+ 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
+ 2: LOCAL_APIC_DELIVERY_MODE_SMI
+ 4: LOCAL_APIC_DELIVERY_MODE_NMI
+ 5: LOCAL_APIC_DELIVERY_MODE_INIT
+ 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
+
+ @param LevelTriggered TRUE specifies a level triggered interrupt.
+ FALSE specifies an edge triggered interrupt.
+ @param AssertionLevel Ignored if LevelTriggered is FALSE.
+ TRUE specifies a level triggered interrupt that active
+ when the interrupt line is asserted.
+ FALSE specifies a level triggered interrupt that active
+ when the interrupt line is deasserted.
+
+ @return 64-bit data value used to send an MSI to the Local APIC.
+**/
+UINT64
+EFIAPI
+GetApicMsiValue (
+ IN UINT8 Vector,
+ IN UINTN DeliveryMode,
+ IN BOOLEAN LevelTriggered,
+ IN BOOLEAN AssertionLevel
+ )
+{
+ LOCAL_APIC_MSI_DATA MsiData;
+
+ ASSERT (Vector >= 0x10 && Vector <= 0xFE);
+ ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
+
+ MsiData.Uint64 = 0;
+ MsiData.Bits.Vector = Vector;
+ MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
+ if (LevelTriggered) {
+ MsiData.Bits.TriggerMode = 1;
+ if (AssertionLevel) {
+ MsiData.Bits.Level = 1;
+ }
+ }
+ return MsiData.Uint64;
+}
+
+/**
+ Get Package ID/Core ID/Thread ID of a processor.
+
+ The algorithm assumes the target system has symmetry across physical
+ package boundaries with respect to the number of logical processors
+ per package, number of cores per package.
+
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.
+ @param[out] Package Returns the processor package ID.
+ @param[out] Core Returns the processor core ID.
+ @param[out] Thread Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+ IN UINT32 InitialApicId,
+ OUT UINT32 *Package OPTIONAL,
+ OUT UINT32 *Core OPTIONAL,
+ OUT UINT32 *Thread OPTIONAL
+ )
+{
+ BOOLEAN TopologyLeafSupported;
+ UINTN ThreadBits;
+ UINTN CoreBits;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ UINT32 MaxCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+
+ //
+ // Check if the processor is capable of supporting more than one logical processor.
+ //
+ AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+ if (VersionInfoEdx.Bits.HTT == 0) {
+ if (Thread != NULL) {
+ *Thread = 0;
+ }
+ if (Core != NULL) {
+ *Core = 0;
+ }
+ if (Package != NULL) {
+ *Package = 0;
+ }
+ return;
+ }
+
+ ThreadBits = 0;
+ CoreBits = 0;
+
+ //
+ // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ //
+ TopologyLeafSupported = FALSE;
+
+ //
+ // Get the max index of basic CPUID
+ //
+ AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+ //
+ // If the extended topology enumeration leaf is available, it
+ // is the preferred mechanism for enumerating topology.
+ //
+ if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ AsmCpuidEx(
+ CPUID_EXTENDED_TOPOLOGY,
+ 0,
+ &ExtendedTopologyEax.Uint32,
+ &ExtendedTopologyEbx.Uint32,
+ &ExtendedTopologyEcx.Uint32,
+ NULL
+ );
+ //
+ // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+ // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+ // supported on that processor.
+ //
+ if (ExtendedTopologyEbx.Uint32 != 0) {
+ TopologyLeafSupported = TRUE;
+
+ //
+ // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+ // the SMT sub-field of x2APIC ID.
+ //
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;
+ ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+ ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+ //
+ // Software must not assume any "level type" encoding
+ // value to be related to any sub-leaf index, except sub-leaf 0.
+ //
+ SubIndex = 1;
+ do {
+ AsmCpuidEx(
+ CPUID_EXTENDED_TOPOLOGY,
+ SubIndex,
+ &ExtendedTopologyEax.Uint32,
+ NULL,
+ &ExtendedTopologyEcx.Uint32,
+ NULL
+ );
+ LevelType = ExtendedTopologyEcx.Bits.LevelType;
+ if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+ CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+ break;
+ }
+ SubIndex++;
+ } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ }
+ }
+
+ if (!TopologyLeafSupported) {
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+ if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ }
+ else {
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
+ }
+
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+
+ if (Thread != NULL) {
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ }
+ if (Core != NULL) {
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ }
+ if (Package != NULL) {
+ *Package = (InitialApicId >> (ThreadBits + CoreBits));
+ }
+}