X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FLibrary%2FBaseXApicX2ApicLib%2FBaseXApicX2ApicLib.c;fp=UefiCpuPkg%2FLibrary%2FBaseXApicX2ApicLib%2FBaseXApicX2ApicLib.c;h=aaa42ff8450b575e541a30ed373007aae9169196;hp=cdcbca04619119a2b0012e347647acd1ec65f6cd;hb=053e878bfb5c9d5eca779789b62891add30b14ba;hpb=91415a36ae7aaeabb2bbab3762f39544f9aed683 diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index cdcbca0461..aaa42ff845 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported ( AsmCpuid (1, &RegEax, NULL, NULL, NULL); FamilyId = BitFieldRead32 (RegEax, 8, 11); - if (FamilyId == 0x04 || FamilyId == 0x05) { + if ((FamilyId == 0x04) || (FamilyId == 0x05)) { // // CPUs with a FamilyId of 0x04 or 0x05 do not support the // Local APIC Base Address MSR // return FALSE; } + return TRUE; } @@ -79,8 +80,8 @@ GetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + - (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) + + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); } /** @@ -94,7 +95,7 @@ GetLocalApicBaseAddress ( VOID EFIAPI SetLocalApicBaseAddress ( - IN UINTN BaseAddress + IN UINTN BaseAddress ) { MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; @@ -110,8 +111,8 @@ SetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); - ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); - ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); + ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12); + ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32)); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); } @@ -135,12 +136,12 @@ ReadLocalApicReg ( IN UINTN MmioOffset ) { - UINT32 MsrIndex; + UINT32 MsrIndex; ASSERT ((MmioOffset & 0xf) == 0); if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { - return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); + return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset); } else { // // DFR is not supported in x2APIC mode. @@ -174,16 +175,16 @@ ReadLocalApicReg ( VOID EFIAPI WriteLocalApicReg ( - IN UINTN MmioOffset, - IN UINT32 Value + IN UINTN MmioOffset, + IN UINT32 Value ) { - UINT32 MsrIndex; + UINT32 MsrIndex; ASSERT ((MmioOffset & 0xf) == 0); if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { - MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); + MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value); } else { // // DFR is not supported in x2APIC mode. @@ -216,15 +217,15 @@ WriteLocalApicReg ( **/ VOID SendIpi ( - IN UINT32 IcrLow, - IN UINT32 ApicId + IN UINT32 IcrLow, + IN UINT32 ApicId ) { - UINT64 MsrValue; - LOCAL_APIC_ICR_LOW IcrLowReg; - UINTN LocalApciBaseAddress; - UINT32 IcrHigh; - BOOLEAN InterruptState; + UINT64 MsrValue; + LOCAL_APIC_ICR_LOW IcrLowReg; + UINTN LocalApciBaseAddress; + UINT32 IcrHigh; + BOOLEAN InterruptState; // // Legacy APIC or X2APIC? @@ -237,7 +238,7 @@ SendIpi ( // // Get base address of this LAPIC // - LocalApciBaseAddress = GetLocalApicBaseAddress(); + LocalApciBaseAddress = GetLocalApicBaseAddress (); // // Save existing contents of ICR high 32 bits @@ -271,13 +272,12 @@ SendIpi ( MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh); SetInterruptState (InterruptState); - } else { // // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an // interrupt in x2APIC mode. // - MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow; + MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow; AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue); } } @@ -354,7 +354,7 @@ SetApicMode ( case LOCAL_APIC_MODE_XAPIC: break; case LOCAL_APIC_MODE_X2APIC: - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.EXTD = 1; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); break; @@ -368,9 +368,9 @@ SetApicMode ( // Transition from x2APIC mode to xAPIC mode is a two-step process: // x2APIC -> Local APIC disabled -> xAPIC // - ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.EXTD = 0; - ApicBaseMsr.Bits.EN = 0; + ApicBaseMsr.Bits.EN = 0; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); ApicBaseMsr.Bits.EN = 1; AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); @@ -398,9 +398,9 @@ GetInitialApicId ( VOID ) { - UINT32 ApicId; - UINT32 MaxCpuIdIndex; - UINT32 RegEbx; + UINT32 ApicId; + UINT32 MaxCpuIdIndex; + UINT32 RegEbx; if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { // @@ -419,6 +419,7 @@ GetInitialApicId ( return ApicId; } } + AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); return RegEbx >> 24; } else { @@ -437,8 +438,8 @@ GetApicId ( VOID ) { - UINT32 ApicId; - UINT32 InitApicId; + UINT32 ApicId; + UINT32 InitApicId; ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { @@ -473,16 +474,16 @@ GetApicVersion ( VOID EFIAPI SendFixedIpi ( - IN UINT32 ApicId, - IN UINT8 Vector + IN UINT32 ApicId, + IN UINT8 Vector ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; - IcrLow.Bits.Level = 1; - IcrLow.Bits.Vector = Vector; + IcrLow.Bits.Level = 1; + IcrLow.Bits.Vector = Vector; SendIpi (IcrLow.Uint32, ApicId); } @@ -496,16 +497,16 @@ SendFixedIpi ( VOID EFIAPI SendFixedIpiAllExcludingSelf ( - IN UINT8 Vector + IN UINT8 Vector ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; - IcrLow.Bits.Vector = Vector; + IcrLow.Bits.Vector = Vector; SendIpi (IcrLow.Uint32, 0); } @@ -519,14 +520,14 @@ SendFixedIpiAllExcludingSelf ( VOID EFIAPI SendSmiIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); } @@ -541,11 +542,11 @@ SendSmiIpiAllExcludingSelf ( VOID ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); } @@ -560,14 +561,14 @@ SendSmiIpiAllExcludingSelf ( VOID EFIAPI SendInitIpi ( - IN UINT32 ApicId + IN UINT32 ApicId ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; + IcrLow.Uint32 = 0; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); } @@ -582,11 +583,11 @@ SendInitIpiAllExcludingSelf ( VOID ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; - IcrLow.Uint32 = 0; - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; - IcrLow.Bits.Level = 1; + IcrLow.Uint32 = 0; + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); } @@ -606,21 +607,21 @@ SendInitIpiAllExcludingSelf ( VOID EFIAPI SendInitSipiSipi ( - IN UINT32 ApicId, - IN UINT32 StartupRoutine + IN UINT32 ApicId, + IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; ASSERT (StartupRoutine < 0x100000); ASSERT ((StartupRoutine & 0xfff) == 0); SendInitIpi (ApicId); - MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); + MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; + IcrLow.Bits.Level = 1; SendIpi (IcrLow.Uint32, ApicId); if (!StandardSignatureIsAuthenticAMD ()) { MicroSecondDelay (200); @@ -642,20 +643,20 @@ SendInitSipiSipi ( VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( - IN UINT32 StartupRoutine + IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; + LOCAL_APIC_ICR_LOW IcrLow; ASSERT (StartupRoutine < 0x100000); ASSERT ((StartupRoutine & 0xfff) == 0); SendInitIpiAllExcludingSelf (); - MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; + MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; + IcrLow.Bits.Level = 1; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; SendIpi (IcrLow.Uint32, 0); if (!StandardSignatureIsAuthenticAMD ()) { @@ -711,13 +712,13 @@ ProgramVirtualWireMode ( VOID ) { - LOCAL_APIC_SVR Svr; - LOCAL_APIC_LVT_LINT Lint; + LOCAL_APIC_SVR Svr; + LOCAL_APIC_LVT_LINT Lint; // // Enable the APIC via SVR and set the spurious interrupt to use Int 00F. // - Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); + Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); Svr.Bits.SpuriousVector = 0xf; Svr.Bits.SoftwareEnable = 1; WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32); @@ -725,21 +726,21 @@ ProgramVirtualWireMode ( // // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high. // - Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); - Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; + Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); + Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; Lint.Bits.InputPinPolarity = 0; - Lint.Bits.TriggerMode = 0; - Lint.Bits.Mask = 0; + Lint.Bits.TriggerMode = 0; + Lint.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32); // // Program the LINT0 vector entry as NMI. Not masked, edge, active high. // - Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); - Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; + Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); + Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; Lint.Bits.InputPinPolarity = 0; - Lint.Bits.TriggerMode = 0; - Lint.Bits.Mask = 0; + Lint.Bits.TriggerMode = 0; + Lint.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32); } @@ -754,13 +755,13 @@ DisableLvtInterrupts ( VOID ) { - LOCAL_APIC_LVT_LINT LvtLint; + LOCAL_APIC_LVT_LINT LvtLint; - LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); + LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); LvtLint.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32); - LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); + LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); LvtLint.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32); } @@ -807,15 +808,15 @@ GetApicTimerCurrentCount ( VOID EFIAPI InitializeApicTimer ( - IN UINTN DivideValue, - IN UINT32 InitCount, - IN BOOLEAN PeriodicMode, - IN UINT8 Vector + IN UINTN DivideValue, + IN UINT32 InitCount, + IN BOOLEAN PeriodicMode, + IN UINT8 Vector ) { - LOCAL_APIC_DCR Dcr; - LOCAL_APIC_LVT_TIMER LvtTimer; - UINT32 Divisor; + LOCAL_APIC_DCR Dcr; + LOCAL_APIC_LVT_TIMER LvtTimer; + UINT32 Divisor; // // Ensure local APIC is in software-enabled state. @@ -829,10 +830,10 @@ InitializeApicTimer ( if (DivideValue != 0) { ASSERT (DivideValue <= 128); - ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); + ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue)); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); - Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); + Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Bits.DivideValue1 = (Divisor & 0x3); Dcr.Bits.DivideValue2 = (Divisor >> 2); WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); @@ -847,7 +848,8 @@ InitializeApicTimer ( } else { LvtTimer.Bits.TimerMode = 0; } - LvtTimer.Bits.Mask = 0; + + LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Vector = Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -869,25 +871,25 @@ GetApicTimerState ( OUT UINT8 *Vector OPTIONAL ) { - UINT32 Divisor; - LOCAL_APIC_DCR Dcr; - LOCAL_APIC_LVT_TIMER LvtTimer; + UINT32 Divisor; + LOCAL_APIC_DCR Dcr; + LOCAL_APIC_LVT_TIMER LvtTimer; // // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt // Vector Register. // This bit will be 1, if local APIC is software enabled. // - ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); + ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); if (DivideValue != NULL) { - Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); - Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); - Divisor = (Divisor + 1) & 0x7; + Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); + Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); + Divisor = (Divisor + 1) & 0x7; *DivideValue = ((UINTN)1) << Divisor; } - if (PeriodicMode != NULL || Vector != NULL) { + if ((PeriodicMode != NULL) || (Vector != NULL)) { LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); if (PeriodicMode != NULL) { if (LvtTimer.Bits.TimerMode == 1) { @@ -896,8 +898,9 @@ GetApicTimerState ( *PeriodicMode = FALSE; } } + if (Vector != NULL) { - *Vector = (UINT8) LvtTimer.Bits.Vector; + *Vector = (UINT8)LvtTimer.Bits.Vector; } } } @@ -911,9 +914,9 @@ EnableApicTimerInterrupt ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; - LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); + LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Bits.Mask = 0; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -927,9 +930,9 @@ DisableApicTimerInterrupt ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; - LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); + LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Bits.Mask = 1; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); } @@ -946,7 +949,7 @@ GetApicTimerInterruptState ( VOID ) { - LOCAL_APIC_LVT_TIMER LvtTimer; + LOCAL_APIC_LVT_TIMER LvtTimer; LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); return (BOOLEAN)(LvtTimer.Bits.Mask == 0); @@ -1039,6 +1042,7 @@ GetApicMsiValue ( MsiData.Bits.Level = 1; } } + return MsiData.Uint64; } @@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId ( if (Thread != NULL) { *Thread = 0; } + if (Core != NULL) { *Core = 0; } + if (Package != NULL) { *Package = 0; } + return; } @@ -1103,7 +1110,7 @@ GetProcessorLocationByApicId ( // Assume three-level mapping of APIC ID: Package|Core|Thread. // ThreadBits = 0; - CoreBits = 0; + CoreBits = 0; // // Get max index of CPUID @@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId ( // TopologyLeafSupported = FALSE; if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_EXTENDED_TOPOLOGY, 0, &ExtendedTopologyEax.Uint32, @@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId ( CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; break; } + SubIndex++; } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } @@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId ( // // Check for topology extensions on AMD processor // - if (StandardSignatureIsAuthenticAMD()) { + if (StandardSignatureIsAuthenticAMD ()) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { @@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId ( MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); } } - } - else { + } else { // // Extract core count based on CACHE information // @@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId ( } } - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); + CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1); } if (Thread != NULL) { *Thread = InitialApicId & ((1 << ThreadBits) - 1); } + if (Core != NULL) { *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } + if (Package != NULL) { *Package = (InitialApicId >> (ThreadBits + CoreBits)); } @@ -1253,13 +1262,13 @@ GetProcessorLocation2ByApicId ( OUT UINT32 *Thread OPTIONAL ) { - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxStandardCpuIdIndex; - UINT32 Index; - UINTN LevelType; - UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; - UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxStandardCpuIdIndex; + UINT32 Index; + UINTN LevelType; + UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; + UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] = 0; @@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId ( if (Die != NULL) { *Die = 0; } + if (Tile != NULL) { *Tile = 0; } + if (Module != NULL) { *Module = 0; } + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); return; } @@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId ( // is the preferred mechanism for enumerating topology. // for (Index = 0; ; Index++) { - AsmCpuidEx( + AsmCpuidEx ( CPUID_V2_EXTENDED_TOPOLOGY, Index, &ExtendedTopologyEax.Uint32, @@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId ( if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { break; } + ASSERT (LevelType < ARRAY_SIZE (Bits)); Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; } @@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId ( } Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; - Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; - Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; - Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile; + Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module; + Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core; + Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT - ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 - ; LevelType ++ - ) { + ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 + ; LevelType++ + ) + { if (Location[LevelType] != NULL) { // // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique