X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FLibrary%2FBaseXApicX2ApicLib%2FBaseXApicX2ApicLib.c;h=9f08f5d188c14d9ec5313275b0ce0b67aa16c9e0;hp=1cba34cd598e605d3840d24e2f1ba22c5bdc3edc;hb=23394428fdfe351ae9382576cdeee2834a2c637d;hpb=c52acd89e872e32eae7ae6265b86b1670cd9cac1

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 1cba34cd59..9f08f5d188 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -151,7 +151,7 @@ SendIpi (
     // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an 
     // interrupt in x2APIC mode.
     //
-    MsrValue = (((UINT64)ApicId) << 32) | IcrLow;
+    MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
     AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
   }
 }