X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FLibrary%2FMpInitLib%2FMpLib.h;h=a8ca03efb8e3d8e75363dd66ad77fcb740b1c8ed;hp=84ae24f88d774537b930a5e54dcaa6e1decbdf67;hb=8dd962a657b28d9db65ed7a35817a4b82f06301a;hpb=1e3f7a3782f1928a19bba81d9d0dba28d15fdae5
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index 84ae24f88d..a8ca03efb8 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -1,14 +1,10 @@
/** @file
Common header file for MP Initialize Library.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -17,10 +13,11 @@
#include
-#include
-#include
-#include
-#include
+#include
+#include
+#include
+#include
+#include
#include
#include
@@ -34,6 +31,9 @@
#include
#include
#include
+#include
+
+#include
#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')
@@ -49,6 +49,19 @@
#define CPU_SWITCH_STATE_STORED 1
#define CPU_SWITCH_STATE_LOADED 2
+//
+// Default maximum number of entries to store the microcode patches information
+//
+#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8
+
+//
+// Data structure for microcode patch information
+//
+typedef struct {
+ UINTN Address;
+ UINTN Size;
+} MICROCODE_PATCH_INFO;
+
//
// CPU exchange information for switch BSP
//
@@ -81,6 +94,10 @@ typedef enum {
//
// AP state
//
+// The state transitions for an AP when it process a procedure are:
+// Idle ----> Ready ----> Busy ----> Idle
+// [BSP] [AP] [AP]
+//
typedef enum {
CpuStateIdle,
CpuStateReady,
@@ -102,6 +119,9 @@ typedef struct {
UINTN Dr3;
UINTN Dr6;
UINTN Dr7;
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ UINT16 Tr;
} CPU_VOLATILE_REGISTERS;
//
@@ -121,6 +141,9 @@ typedef struct {
UINT64 CurrentTime;
UINT64 TotalTime;
EFI_EVENT WaitEvent;
+ UINT32 ProcessorSignature;
+ UINT8 PlatformId;
+ UINT64 MicrocodeEntryAddr;
} CPU_AP_DATA;
//
@@ -149,6 +172,7 @@ typedef struct {
UINTN RendezvousFunnelSize;
UINT8 *RelocateApLoopFuncAddress;
UINTN RelocateApLoopFuncSize;
+ UINTN ModeTransitionOffset;
} MP_ASSEMBLY_ADDRESS_MAP;
typedef struct _CPU_MP_DATA CPU_MP_DATA;
@@ -169,15 +193,24 @@ typedef struct {
IA32_DESCRIPTOR IdtrProfile;
UINTN BufferStart;
UINTN ModeOffset;
- UINTN NumApsExecuting;
+ UINTN ApIndex;
UINTN CodeSegment;
UINTN DataSegment;
UINTN EnableExecuteDisable;
UINTN Cr3;
UINTN InitFlag;
CPU_INFO_IN_HOB *CpuInfo;
+ UINTN NumApsExecuting;
CPU_MP_DATA *CpuMpData;
UINTN InitializeFloatingPointUnitsAddress;
+ UINT32 ModeTransitionMemory;
+ UINT16 ModeTransitionSegment;
+ UINT32 ModeHighMemory;
+ UINT16 ModeHighSegment;
+ //
+ // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.
+ //
+ BOOLEAN Enable5LevelPaging;
} MP_CPU_EXCHANGE_INFO;
#pragma pack()
@@ -199,12 +232,12 @@ struct _CPU_MP_DATA {
UINTN CpuApStackSize;
MP_ASSEMBLY_ADDRESS_MAP AddressMap;
UINTN WakeupBuffer;
+ UINTN WakeupBufferHigh;
UINTN BackupBuffer;
UINTN BackupBufferSize;
- volatile UINT32 StartCount;
volatile UINT32 FinishedCount;
- volatile UINT32 RunningCount;
+ UINT32 RunningCount;
BOOLEAN SingleThread;
EFI_AP_PROCEDURE Procedure;
VOID *ProcArguments;
@@ -216,7 +249,6 @@ struct _CPU_MP_DATA {
UINTN **FailedCpuList;
AP_INIT_STATE InitFlag;
- BOOLEAN X2ApicEnable;
BOOLEAN SwitchBspFlag;
UINTN NewBspNumber;
CPU_EXCHANGE_ROLE_INFO BSPInfo;
@@ -235,6 +267,15 @@ struct _CPU_MP_DATA {
BOOLEAN TimerInterruptState;
UINT64 MicrocodePatchAddress;
UINT64 MicrocodePatchRegionSize;
+
+ //
+ // Whether need to use Init-Sipi-Sipi to wake up the APs.
+ // Two cases need to set this value to TRUE. One is in HLT
+ // loop mode, the other is resume from S3 which loop mode
+ // will be hardcode change to HLT mode by PiSmmCpuDxeSmm
+ // driver.
+ //
+ BOOLEAN WakeUpByInitSipiSipi;
};
extern EFI_GUID mCpuInitMpLibHobGuid;
@@ -325,6 +366,23 @@ GetWakeupBuffer (
IN UINTN WakeupBufferSize
);
+/**
+ Get available EfiBootServicesCode memory below 4GB by specified size.
+
+ This buffer is required to safely transfer AP from real address mode to
+ protected mode or long mode, due to the fact that the buffer returned by
+ GetWakeupBuffer() may be marked as non-executable.
+
+ @param[in] BufferSize Wakeup transition buffer size.
+
+ @retval other Return wakeup transition buffer address below 4GB.
+ @retval 0 Cannot find free memory below 4GB.
+**/
+UINTN
+GetModeTransitionBuffer (
+ IN UINTN BufferSize
+ );
+
/**
This function will be called by BSP to wakeup AP.
@@ -334,6 +392,7 @@ GetWakeupBuffer (
@param[in] ProcessorNumber The handle number of specified processor
@param[in] Procedure The function to be invoked by AP
@param[in] ProcedureArgument The argument to be passed into AP function
+ @param[in] WakeUpDisabledAps Whether need to wake up disabled APs in broadcast mode.
**/
VOID
WakeUpAP (
@@ -341,7 +400,8 @@ WakeUpAP (
IN BOOLEAN Broadcast,
IN UINTN ProcessorNumber,
IN EFI_AP_PROCEDURE Procedure, OPTIONAL
- IN VOID *ProcedureArgument OPTIONAL
+ IN VOID *ProcedureArgument, OPTIONAL
+ IN BOOLEAN WakeUpDisabledAps OPTIONAL
);
/**
@@ -365,6 +425,7 @@ InitMpGlobalData (
number. If FALSE, then all the enabled APs
execute the function specified by Procedure
simultaneously.
+ @param[in] ExcludeBsp Whether let BSP also trig this task.
@param[in] WaitEvent The event created by the caller with CreateEvent()
service.
@param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for
@@ -386,9 +447,10 @@ InitMpGlobalData (
**/
EFI_STATUS
-StartupAllAPsWorker (
+StartupAllCPUsWorker (
IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread,
+ IN BOOLEAN ExcludeBsp,
IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL,
@@ -436,7 +498,7 @@ StartupThisAPWorker (
enabled AP. Otherwise, it will be disabled.
@retval EFI_SUCCESS BSP successfully switched.
- @retval others Failed to switch BSP.
+ @retval others Failed to switch BSP.
**/
EFI_STATUS
@@ -519,11 +581,46 @@ CheckAndUpdateApsStatus (
/**
Detect whether specified processor can find matching microcode patch and load it.
- @param[in] CpuMpData The pointer to CPU MP Data structure.
+ @param[in] CpuMpData The pointer to CPU MP Data structure.
+ @param[in] ProcessorNumber The handle number of the processor. The range is
+ from 0 to the total number of logical processors
+ minus 1.
**/
VOID
MicrocodeDetect (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData,
+ IN UINTN ProcessorNumber
+ );
+
+/**
+ Shadow the required microcode patches data into memory.
+
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.
+**/
+VOID
+ShadowMicrocodeUpdatePatch (
+ IN OUT CPU_MP_DATA *CpuMpData
+ );
+
+/**
+ Get the cached microcode patch base address and size from the microcode patch
+ information cache HOB.
+
+ @param[out] Address Base address of the microcode patches data.
+ It will be updated if the microcode patch
+ information cache HOB is found.
+ @param[out] RegionSize Size of the microcode patches data.
+ It will be updated if the microcode patch
+ information cache HOB is found.
+
+ @retval TRUE The microcode patch information cache HOB is found.
+ @retval FALSE The microcode patch information cache HOB is not found.
+
+**/
+BOOLEAN
+GetMicrocodePatchInfoFromHob (
+ UINT64 *Address,
+ UINT64 *RegionSize
);
/**
@@ -546,5 +643,36 @@ EnableDebugAgent (
VOID
);
+/**
+ Find the current Processor number by APIC ID.
+
+ @param[in] CpuMpData Pointer to PEI CPU MP Data
+ @param[out] ProcessorNumber Return the pocessor number found
+
+ @retval EFI_SUCCESS ProcessorNumber is found and returned.
+ @retval EFI_NOT_FOUND ProcessorNumber is not found.
+**/
+EFI_STATUS
+GetProcessorNumber (
+ IN CPU_MP_DATA *CpuMpData,
+ OUT UINTN *ProcessorNumber
+ );
+
+/**
+ This funtion will try to invoke platform specific microcode shadow logic to
+ relocate microcode update patches into memory.
+
+ @param[in, out] CpuMpData The pointer to CPU MP Data structure.
+
+ @retval EFI_SUCCESS Shadow microcode success.
+ @retval EFI_OUT_OF_RESOURCES No enough resource to complete the operation.
+ @retval EFI_UNSUPPORTED Can't find platform specific microcode shadow
+ PPI/Protocol.
+**/
+EFI_STATUS
+PlatformShadowMicrocode (
+ IN OUT CPU_MP_DATA *CpuMpData
+ );
+
#endif