X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FPiSmmCpuDxeSmm%2FIa32%2FSmiEntry.S;h=3243a91a12052a2a970e1edbac4c3670e26788ff;hp=6fcf41a677d6adef13b4247179b663a4d3aac2a9;hb=8596c140907ebfeabf62427686280666a4e04893;hpb=7947da3cccb5dfc973fe9ad9d814477ed978aea1

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index 6fcf41a677..3243a91a12 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -1,6 +1,6 @@
 #------------------------------------------------------------------------------
 #
-# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
@@ -24,10 +24,17 @@ ASM_GLOBAL  ASM_PFX(gcSmiHandlerSize)
 ASM_GLOBAL  ASM_PFX(gSmiCr3)
 ASM_GLOBAL  ASM_PFX(gSmiStack)
 ASM_GLOBAL  ASM_PFX(gSmbase)
-ASM_GLOBAL  ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug))
+ASM_GLOBAL  ASM_PFX(mXdSupported)
 ASM_GLOBAL  ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
 ASM_GLOBAL  ASM_PFX(gSmiHandlerIdtr)
 
+.equ            MSR_IA32_MISC_ENABLE, 0x1A0
+.equ            MSR_EFER, 0xc0000080
+.equ            MSR_EFER_XD, 0x800
+
+#
+# Constants relating to PROCESSOR_SMM_DESCRIPTOR
+#
 .equ            DSC_OFFSET, 0xfb00
 .equ            DSC_GDTPTR, 0x30
 .equ            DSC_GDTSIZ, 0x38
@@ -123,8 +130,42 @@ L11:
     orl     $BIT10, %eax
 L12:                                       # as cr4.PGE is not set here, refresh cr3
     movl    %eax, %cr4                     # in PreModifyMtrrs() to flush TLB.
+
+    cmpb    $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
+    jz      L5
+# Load TSS
+    movb    $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
+    movl    $TSS_SEGMENT, %eax
+    ltrw    %ax
+L5:
+
+# enable NXE if supported
+    .byte   0xb0                           # mov al, imm8
+ASM_PFX(mXdSupported): .byte 1
+    cmpb    $0, %al
+    jz      SkipNxe
+#
+# Check XD disable bit
+#
+    movl    $MSR_IA32_MISC_ENABLE, %ecx
+    rdmsr
+    pushl   %edx                           # save MSR_IA32_MISC_ENABLE[63-32]
+    testl   $BIT2, %edx                    # MSR_IA32_MISC_ENABLE[34]
+    jz      L13
+    andw    $0x0FFFB, %dx                  # clear XD Disable bit if it is set
+    wrmsr
+L13:
+    movl    $MSR_EFER, %ecx
+    rdmsr
+    orw     $MSR_EFER_XD,%ax               # enable NXE
+    wrmsr
+    jmp     NxeDone
+SkipNxe:
+    subl    $4, %esp
+NxeDone:
+
     movl    %cr0, %ebx
-    orl     $0x080000000, %ebx             # enable paging
+    orl     $0x080010023, %ebx             # enable paging + WP + NE + MP + PE
     movl    %ebx, %cr0
     leal    DSC_OFFSET(%edi),%ebx
     movw    DSC_DS(%ebx),%ax
@@ -136,56 +177,39 @@ L12:                                       # as cr4.PGE is not set here, refresh
     movw    DSC_SS(%ebx),%ax
     movl    %eax, %ss
 
-    cmpb    $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
-    jz      L5
-
-# Load TSS
-    movb    $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
-    movl    $TSS_SEGMENT, %eax
-    ltrw    %ax
-L5:
-
 #   jmp     _SmiHandler                 # instruction is not needed
 
 _SmiHandler:
-    cmpb    $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug))
-    jz      L3
-
-L6:
-    call    L1
-L1:
-    popl    %ebp
-    movl    $0x80000001, %eax
-    cpuid
-    btl     $29, %edx                   # check cpuid to identify X64 or IA32
-    leal    (0x7fc8 - (L1 - _SmiEntryPoint))(%ebp), %edi
-    leal    4(%edi), %esi
-    jnc     L2
-    addl    $4, %esi
-L2:
-    movl    (%esi), %ecx
-    movl    (%edi), %edx
-L7:
-    movl    %ecx, %dr6
-    movl    %edx, %dr7                  # restore DR6 & DR7 before running C code
-L3:
-
-    pushl   (%esp)
+    movl    4(%esp), %ebx
 
-    movl    $ASM_PFX(SmiRendezvous), %eax
+    pushl   %ebx
+    movl    $ASM_PFX(CpuSmmDebugEntry), %eax
     call    *%eax
-    popl    %ecx
-
-
-    cmpb    $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmDebug))
-    jz      L4
+    addl    $4, %esp
 
-    movl    %dr6, %ecx
-    movl    %dr7, %edx
-    movl    %ecx, (%esi)
-    movl    %edx, (%edi)
-L4:
+    pushl   %ebx
+    movl    $ASM_PFX(SmiRendezvous), %eax
+    call    *%eax
+    addl    $4, %esp
 
+    pushl   %ebx
+    movl    $ASM_PFX(CpuSmmDebugExit), %eax
+    call    *%eax
+    addl    $4, %esp
+
+    movl    $ASM_PFX(mXdSupported), %eax
+    movb    (%eax), %al
+    cmpb    $0, %al
+    jz      L16
+    popl    %edx                        # get saved MSR_IA32_MISC_ENABLE[63-32]
+    testl   $BIT2, %edx
+    jz      L16
+    movl    $MSR_IA32_MISC_ENABLE, %ecx
+    rdmsr
+    orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM
+    wrmsr
+
+L16:
     rsm
 
 ASM_PFX(gcSmiHandlerSize):    .word      . - _SmiEntryPoint