X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FPiSmmCpuDxeSmm%2FMpService.c;h=185cb3d5935fe92ebf79a785487c392e080a0d69;hp=06ffc6dd86a830963eb9a431af1087d8bbd3acd1;hb=e1695f8dcf18f612d34f6da0a4579a5b7c49ef9b;hpb=9daa916dd1efe6443f9a66dfa882f3185d33ad28

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 06ffc6dd86..185cb3d593 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1,7 +1,7 @@
 /** @file
 SMM MP service implementation
 
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -732,12 +732,14 @@ APHandler (
   Create 4G PageTable in SMRAM.
 
   @param          ExtraPages       Additional page numbers besides for 4G memory
+  @param          Is32BitPageTable Whether the page table is 32-bit PAE
   @return         PageTable Address
 
 **/
 UINT32
 Gen4GPageTable (
-  IN      UINTN                     ExtraPages
+  IN      UINTN                     ExtraPages,
+  IN      BOOLEAN                   Is32BitPageTable
   )
 {
   VOID    *PageTable;
@@ -785,7 +787,7 @@ Gen4GPageTable (
   // Set Page Directory Pointers
   //
   for (Index = 0; Index < 4; Index++) {
-    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + IA32_PG_P;
+    Pte[Index] = (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
   }
   Pte += EFI_PAGE_SIZE / sizeof (*Pte);
 
@@ -793,7 +795,7 @@ Gen4GPageTable (
   // Fill in Page Directory Entries
   //
   for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {
-    Pte[Index] = (Index << 21) + IA32_PG_PS + IA32_PG_RW + IA32_PG_P;
+    Pte[Index] = (Index << 21) | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;
   }
 
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
@@ -802,7 +804,7 @@ Gen4GPageTable (
     Pdpte = (UINT64*)PageTable;
     for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {
       Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~(EFI_PAGE_SIZE - 1));
-      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages + IA32_PG_RW + IA32_PG_P;
+      Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | PAGE_ATTRIBUTE_BITS;
       //
       // Fill in Page Table Entries
       //
@@ -819,7 +821,7 @@ Gen4GPageTable (
             GuardPage = 0;
           }
         } else {
-          Pte[Index] = PageAddress + IA32_PG_RW + IA32_PG_P;
+          Pte[Index] = PageAddress | PAGE_ATTRIBUTE_BITS;
         }
         PageAddress+= EFI_PAGE_SIZE;
       }
@@ -886,7 +888,7 @@ SetCacheability (
       NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT);
     }
 
-    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | IA32_PG_P;
+    PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS;
   }
 
   ASSERT (PageTable[PTIndex] & IA32_PG_P);
@@ -941,7 +943,7 @@ SmmStartupThisAp (
 }
 
 /**
-  This funciton sets DR6 & DR7 according to SMM save state, before running SMM C code.
+  This function sets DR6 & DR7 according to SMM save state, before running SMM C code.
   They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.
 
   NOTE: It might not be appreciated in runtime since it might
@@ -959,7 +961,7 @@ CpuSmmDebugEntry (
   SMRAM_SAVE_STATE_MAP *CpuSaveState;
   
   if (FeaturePcdGet (PcdCpuSmmDebug)) {
-    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
       AsmWriteDr6 (CpuSaveState->x86._DR6);
       AsmWriteDr7 (CpuSaveState->x86._DR7);
@@ -971,7 +973,7 @@ CpuSmmDebugEntry (
 }
 
 /**
-  This funciton restores DR6 & DR7 to SMM save state.
+  This function restores DR6 & DR7 to SMM save state.
 
   NOTE: It might not be appreciated in runtime since it might
         conflict with OS debugging facilities. Turn them off in RELEASE.
@@ -988,7 +990,7 @@ CpuSmmDebugExit (
   SMRAM_SAVE_STATE_MAP *CpuSaveState;
 
   if (FeaturePcdGet (PcdCpuSmmDebug)) {
-    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
       CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();
       CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();
@@ -1017,6 +1019,7 @@ SmiRendezvous (
   BOOLEAN           BspInProgress;
   UINTN             Index;
   UINTN             Cr2;
+  BOOLEAN           XdDisableFlag;
 
   //
   // Save Cr2 because Page Fault exception in SMM may override its value
@@ -1076,9 +1079,14 @@ SmiRendezvous (
     }
 
     //
-    // Try to enable NX
+    // Try to enable XD
     //
+    XdDisableFlag = FALSE;
     if (mXdSupported) {
+      if ((AsmReadMsr64 (MSR_IA32_MISC_ENABLE) & B_XD_DISABLE_BIT) != 0) {
+        XdDisableFlag = TRUE;
+        AsmMsrAnd64 (MSR_IA32_MISC_ENABLE, ~B_XD_DISABLE_BIT);
+      }
       ActivateXd ();
     }
 
@@ -1150,7 +1158,6 @@ SmiRendezvous (
         // BSP Handler is always called with a ValidSmi == TRUE
         //
         BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);
-
       } else {
         APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);
       }
@@ -1163,6 +1170,13 @@ SmiRendezvous (
     //
     while (mSmmMpSyncData->AllCpusInSync) {
       CpuPause ();
+     }
+
+    //
+    // Restore XD
+    //
+    if (XdDisableFlag) {
+      AsmMsrOr64 (MSR_IA32_MISC_ENABLE, B_XD_DISABLE_BIT);
     }
   }