X-Git-Url: https://git.proxmox.com/?p=mirror_edk2.git;a=blobdiff_plain;f=UefiCpuPkg%2FPiSmmCpuDxeSmm%2FPiSmmCpuDxeSmm.c;h=4bef60a1ac512426c5e2072df7572343b26476c7;hp=f957de1f47640bfe5ac0330f878984345ecd7725;hb=f12367a0b1de7838f1cb8e0839e168ed7b862333;hpb=26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index f957de1f47..4bef60a1ac 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -711,22 +711,23 @@ PiCpuSmmEntry (
 
   //
   // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
-  // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point.  This size
-  // is rounded up to nearest power of 2.
+  // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
+  // This size is rounded up to nearest power of 2.
   //
   TileCodeSize = GetSmiHandlerSize ();
   TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
-  TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);
+  TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
   TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
   TileSize = TileDataSize + TileCodeSize - 1;
   TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
   DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
 
   //
-  // If the TileSize is larger than space available for the SMI Handler of CPU[i],
-  // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
-  // the ASSERT().  If this ASSERT() is triggered, then the SMI Handler size must be
-  // reduced.
+  // If the TileSize is larger than space available for the SMI Handler of
+  // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
+  // State Map of CPU[i+1], then ASSERT().  If this ASSERT() is triggered, then
+  // the SMI Handler size must be reduced or the size of the extra CPU specific
+  // context must be reduced.
   //
   ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));