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(parent: c7981a1) | patch
Correct TSS segment.
authorYao, Jiewen <jiewen.yao@intel.com>
Wed, 25 Nov 2015 04:01:00 +0000 (04:01 +0000)
committerjyao1 <jyao1@Edk2>
Wed, 25 Nov 2015 04:01:00 +0000 (04:01 +0000)
commit20ab326972339d16d7e95d94f9d7710cae1ae75f
treead65cc087e312329dd7daf55aea521905d3f2689tree
parentc7981a11840714975a7dc029366931ddec64b2a6commit | diff
Correct TSS segment.

TSS segment should use (SIZE - 1) as limit, and do not set G bit (highest bit of LimitHigh) because limit means byte count.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Fan, Jeff" <jeff.fan@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18935 6f19259b-4bc3-4df7-8a09-765794883524
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S diff | blob | blame | history
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm diff | blob | blame | history
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