CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue
authorMaurice Ma <maurice.ma@intel.com>
Thu, 26 May 2016 22:13:23 +0000 (15:13 -0700)
committerMaurice Ma <maurice.ma@intel.com>
Fri, 27 May 2016 21:28:37 +0000 (14:28 -0700)
commit8a3a97814e5402840164cb53ad6bb12ed851c54e
tree5fc73e06d9e218cd3cff50bd72d7f8b6b052ca98
parentee70e58bd28a1bd6decf173a98b85c6e7066b486
CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue

The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation.  Instead, the lowest non-zero bit should be used for BAR
size calculation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c