MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode
authorLeo Duran <leo.duran@amd.com>
Thu, 24 May 2018 19:07:30 +0000 (03:07 +0800)
committerStar Zeng <star.zeng@intel.com>
Mon, 11 Jun 2018 02:40:20 +0000 (10:40 +0800)
commita05a8a5aa17da4bc7144706a9931d68beec1a61f
treed2f86f2f51f3b86627264e7aa2580a7645f21abd
parenteb5943134630292db2c14346b5d94eab0b72314f
MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode

Put the UART in FIFO Polled Mode by clearing IER after setting FCR.
Also, add comments to show DLAB state for registers 0 and 1.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran <leo.duran@amd.com>
Cc: Star Zeng <star.zeng@intel.com>
CC: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c