]> git.proxmox.com Git - mirror_edk2.git/commit
MdeModulePkg/Xhci: Fix TRT when data length is 0
authorWenyi Xie <xiewenyi2@huawei.com>
Thu, 27 May 2021 12:04:26 +0000 (20:04 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Wed, 2 Jun 2021 07:55:57 +0000 (07:55 +0000)
commitb5379899b38ed84561db6dc07dc4641a049ae238
treee41a7bb9fa9cdb31916a3ef1052b906acf2897e3
parentb233eb1849ac01bdd5b24ea84460a2e481a4c5a9
MdeModulePkg/Xhci: Fix TRT when data length is 0

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3418

According to xhci spec, at USB packet level, a Control Transfer
consists of multiple transactions partitioned into stages: a
setup stage, an optional data stage, and a terminating status
stage. If Data Stage does not exist, the Transfer Type flag(TRT)
should be No Data Stage.
So if data length equals to 0, TRT is set to 0.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Wenyi Xie <xiewenyi2@huawei.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c