]> git.proxmox.com Git - mirror_edk2.git/commit
Revert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly"
authorLaszlo Ersek <lersek@redhat.com>
Wed, 29 May 2019 09:52:03 +0000 (11:52 +0200)
committerLaszlo Ersek <lersek@redhat.com>
Mon, 3 Jun 2019 17:54:15 +0000 (19:54 +0200)
commitd4534984111328ff839fbf51be2779a98bfefa30
tree9195cdd19cd9f1023986ec55201fedcf9cca51c1
parent753d3d6f43b2c2bf2df67038608496663ff6e3aa
Revert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly"

This reverts commit 60e95bf5094fbb9b728729ccfaf32184b3662317.

The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.

QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.

Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
OvmfPkg/PlatformPei/Platform.c