//DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.\r
\r
// Enable PLL5 and set to 120 MHz as a reference clock.\r
- MmioWrite32(CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));\r
- MmioWrite32(CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));\r
- MmioWrite32(CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);\r
+ MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));\r
+ MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));\r
+ MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);\r
\r
// Turn on functional & interface clocks to the USBHOST power domain\r
MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE\r
| CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r
\r
// Set count & reload registers\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
\r
// Disable interrupts\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
\r
// Start Timer\r
- MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
\r
//Disable OMAP Watchdog timer (WDT2)\r
- MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA);\r
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r
- MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555);\r
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r
}\r
\r
VOID\r
UINT32 UartBaseAddress = UartBase(Uart);\r
\r
// Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.\r
- MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r
+ MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r
\r
// Put device in configuration mode.\r
- MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r
+ MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r
\r
// Programmable divisor N = 48Mhz/16/115200 = 26\r
- MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor\r
- MmioWrite32(UartBaseAddress + UART_DLH_REG, 0); // high divisor\r
+ MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor\r
+ MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor\r
\r
// Enter into UART operational mode.\r
- MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r
+ MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r
\r
// Force DTR and RTS output to active\r
- MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
+ MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
\r
// Clear & enable fifos\r
- MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r
+ MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r
\r
// Restore MODE_SELECT \r
- MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
+ MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
}\r
\r
VOID\r
VOID *HobBase;\r
\r
//Set up Pin muxing.\r
- PadConfiguration();\r
+ PadConfiguration ();\r
\r
// Set up system clocking\r
- ClockInit();\r
+ ClockInit ();\r
\r
// Build a basic HOB list\r
HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));\r
- CreateHobList(MemoryBase, MemorySize, HobBase, StackBase);\r
+ CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);\r
\r
// Enable program flow prediction, if supported.\r
- ArmEnableBranchPrediction();\r
+ ArmEnableBranchPrediction ();\r
\r
// Initialize CPU cache\r
- InitCache((UINT32)MemoryBase, (UINT32)MemorySize);\r
+ InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);\r
\r
// Add memory allocation hob for relocated FD\r
- BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
+ BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
\r
// Add the FVs to the hob list\r
- BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
+ BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
\r
// Start talking\r
- UartInit();\r
- DEBUG((EFI_D_ERROR, "UART Enabled\n"));\r
+ UartInit ();\r
+ DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r
\r
DEBUG_CODE_BEGIN ();\r
//\r
}\r
}
- DEBUG_CODE_END ();\r
+ \r
+ DEBUG_CODE_END ();\r
\r
\r
\r
// Start up a free running time so that the timer lib will work\r
- TimerInit();\r
+ TimerInit ();\r
\r
// SEC phase needs to run library constructors by hand.\r
- ExtractGuidedSectionLibConstructor();\r
- LzmaDecompressLibConstructor();\r
+ ExtractGuidedSectionLibConstructor ();\r
+ LzmaDecompressLibConstructor ();\r
\r
// Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
-#if 0\r
BuildPeCoffLoaderHob ();\r
BuildExtractSectionHob (\r
&gLzmaCustomDecompressGuid,\r
LzmaGuidedSectionGetInfo,\r
LzmaGuidedSectionExtraction\r
);\r
-#endif\r
\r
DecompressFirstFv ();\r
\r
// Load the DXE Core and transfer control to it\r
- LoadDxeCoreFromFv(NULL, 0);\r
+ LoadDxeCoreFromFv (NULL, 0);\r
\r
// DXE Core should always load and never return\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
#/** @file\r
# \r
-# Component discription file for Bds module\r
+# Convert SerialLib into SerialIo protocol\r
# \r
# Copyright (c) 2008, Intel Corporation. <BR>\r
# All rights reserved. This program and the accompanying materials\r
[Protocols]\r
gEfiSerialIoProtocolGuid \r
gEfiDevicePathProtocolGuid\r
- \r
\r
+[FixedPcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
+\r
+ \r
[Depex] \r
TRUE\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/SerialPortLib.h>\r
+#include <Library/PcdLib.h>\r
\r
#include <Protocol/SerialIo.h>\r
\r
{\r
UINTN Count;\r
\r
- Count = SerialPortWrite (Buffer, *BufferSize);\r
+ Count = SerialPortRead (Buffer, *BufferSize);\r
*BufferSize = Count;\r
return (Count == 0) ? EFI_DEVICE_ERROR : EFI_SUCCESS;\r
}\r
// Template used to initailize the GDB Serial IO protocols\r
//\r
EFI_SERIAL_IO_MODE gSerialIoMode = {\r
- 0, // ControlMask\r
- 0, // Timeout\r
- 0, // BaudRate\r
- 1, // RceiveFifoDepth\r
- 0, // DataBits\r
- 0, // Parity\r
- 0 // StopBits\r
+ 0, // ControlMask\r
+ 0, // Timeout\r
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate\r
+ 1, // RceiveFifoDepth\r
+ FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits\r
+ FixedPcdGet8 (PcdUartDefaultParity), // Parity\r
+ FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits\r
};\r
\r
\r
&gSerialIoMode\r
};\r
\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH Guid;\r
+ UART_DEVICE_PATH Uart;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} SIMPLE_TEXT_OUT_DEVICE_PATH;\r
+\r
+SIMPLE_TEXT_OUT_DEVICE_PATH mDevicePath = {\r
+ {\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0},\r
+ EFI_CALLER_ID_GUID // Use the drivers GUID\r
+ },\r
+ {\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (UART_DEVICE_PATH), 0},\r
+ 0, // Reserved\r
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate\r
+ FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits\r
+ FixedPcdGet8 (PcdUartDefaultParity), // Parity (N)\r
+ FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits\r
+ },\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}\r
+};\r
+\r
\r
/**\r
Initialize the state information for the Serial Io Protocol\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&gHandle, \r
&gEfiSerialIoProtocolGuid, &gSerialIoTemplate,\r
- &gEfiDevicePathProtocolGuid, NULL, // BugBug: Need a device path\r
+ &gEfiDevicePathProtocolGuid, &mDevicePath, \r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/SerialPortLib.h>\r
+#include <Library/PcdLib.h>\r
\r
#include <Protocol/SerialIo.h>\r
#include <Protocol/SimpleTextIn.h>\r
#include <Protocol/SimpleTextOut.h>\r
+#include <Protocol/DevicePath.h>\r
\r
\r
#define MODE0_COLUMN_COUNT 80\r
&mSimpleTextOutMode\r
};\r
\r
- EFI_HANDLE mInstallHandle = NULL;\r
+EFI_HANDLE mInstallHandle = NULL;\r
+\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH Guid;\r
+ UART_DEVICE_PATH Uart;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} SIMPLE_TEXT_OUT_DEVICE_PATH;\r
+\r
+SIMPLE_TEXT_OUT_DEVICE_PATH mDevicePath = {\r
+ {\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0},\r
+ EFI_CALLER_ID_GUID\r
+ },\r
+ {\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (UART_DEVICE_PATH), 0},\r
+ 0, // Reserved\r
+ FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate\r
+ FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits\r
+ FixedPcdGet8 (PcdUartDefaultParity), // Parity (N)\r
+ FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits\r
+ },\r
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}\r
+};\r
+\r
\r
\r
\r
{\r
CHAR8 Char;\r
\r
+ if (!SerialPortPoll ()) {\r
+ return EFI_NOT_READY;\r
+ }\r
+ \r
SerialPortRead ((UINT8 *)&Char, 1);\r
\r
//\r
&mInstallHandle,\r
&gEfiSimpleTextInProtocolGuid, &mSimpleTextIn,\r
&gEfiSimpleTextOutProtocolGuid, &mSimpleTextOut,\r
- NULL \r
+ &gEfiDevicePathProtocolGuid, &mDevicePath,\r
+ NULL\r
);\r
if (!EFI_ERROR (Status)) {\r
gST->ConOut = &mSimpleTextOut;\r
gEfiSerialIoProtocolGuid \r
gEfiDevicePathProtocolGuid\r
\r
+[FixedPcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
+\r
+\r
[depex]\r
TRUE\r
UINT8 *gEccCode;
UINTN gNum512BytesChunks = 0;
-//\r
-// Device path for SemiHosting. It contains our autogened Caller ID GUID.\r
-//\r
-typedef struct {\r
- VENDOR_DEVICE_PATH Guid;\r
- EFI_DEVICE_PATH_PROTOCOL End;\r
-} FLASH_DEVICE_PATH;\r
-\r
-FLASH_DEVICE_PATH gDevicePath = {\r
- {\r
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },\r
- EFI_CALLER_ID_GUID\r
- },\r
- { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}\r
-};\r
+//
+
+// Device path for SemiHosting. It contains our autogened Caller ID GUID.
+
+//
+
+typedef struct {
+
+ VENDOR_DEVICE_PATH Guid;
+
+ EFI_DEVICE_PATH_PROTOCOL End;
+
+} FLASH_DEVICE_PATH;
+
+
+
+FLASH_DEVICE_PATH gDevicePath = {
+
+ {
+
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
+
+ EFI_CALLER_ID_GUID
+
+ },
+
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
+
+};
+
//Actual page address = Column address + Page address + Block address.
)
{
//Enable Smart-idle mode.
- MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE);
+ MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
//Set IRQSTATUS and IRQENABLE to the reset value
- MmioWrite32(GPMC_IRQSTATUS, 0x0);
- MmioWrite32(GPMC_IRQENABLE, 0x0);
+ MmioWrite32 (GPMC_IRQSTATUS, 0x0);
+ MmioWrite32 (GPMC_IRQENABLE, 0x0);
//Disable GPMC timeout control.
- MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
+ MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
//Set WRITEPROTECT bit to enable write access.
- MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH);
+ MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
- MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
- MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
- MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
- MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
- MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
- MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
- MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
+ MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
+ MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
+ MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
+ MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
+ MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
+ MmioWrite32 (GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
+ MmioWrite32 (GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
}
EFI_STATUS
)
{
//Define ECC size 0 and size 1 to 512 bytes
- MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
+ MmioWrite32 (GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
}
VOID
)
{
//Clear all the ECC result registers and select ECC result register 1
- MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
+ MmioWrite32 (GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
//Enable ECC engine on CS0
- MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
+ MmioWrite32 (GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
}
VOID
)
{
//Turn off ECC engine.
- MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE);
+ MmioWrite32 (GPMC_ECC_CONFIG, ECCDISABLE);
}
VOID
break;
case GPIO_MODE_OUTPUT_0:
- MmioWrite32(ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
+ MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
case GPIO_MODE_OUTPUT_1:
- MmioWrite32(SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
+ MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break;
)\r
{\r
// Disable all interrupts\r
- MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
}\r
\r
/**\r
Bank = Source / 32;\r
Bit = 1UL << (Source % 32);\r
\r
- MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);\r
+ MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
\r
return EFI_SUCCESS;\r
}\r
Bank = Source / 32;\r
Bit = 1UL << (Source % 32);\r
\r
- MmioWrite32(INTCPS_MIR_SET(Bank), Bit);\r
+ MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
\r
return EFI_SUCCESS;\r
}\r
Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
\r
// Needed to prevent infinite nesting when Time Driver lowers TPL\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
\r
InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
if (InterruptHandler != NULL) {\r
}\r
\r
// Needed to clear after running the handler\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
}\r
\r
//\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
// Make sure all interrupts are disabled by default.\r
- MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);\r
- MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
+ MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
+ MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
\r
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
while ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
//Provide the block size.
- MmioWrite32(MMCHS_BLK, BLEN_512BYTES);
+ MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
//Setting Data timeout counter value to max value.
MmioAndThenOr32(MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
//Clear Status register.
- MmioWrite32(MMCHS_STAT, 0xFFFFFFFF);
+ MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
//Set command argument register
- MmioWrite32(MMCHS_ARG, CmdArgument);
+ MmioWrite32 (MMCHS_ARG, CmdArgument);
//Enable interrupt enable events to occur
- MmioWrite32(MMCHS_IE, CmdInterruptEnableVal);
+ MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
//Send a command
- MmioWrite32(MMCHS_CMD, Cmd);
+ MmioWrite32 (MMCHS_CMD, Cmd);
//Check for the command status.
while (RetryCount < MAX_RETRY_COUNT) {
//Check if command is completed.
if ((MmcStatus & CC) == CC) {
- MmioWrite32(MMCHS_STAT, CC);
+ MmioWrite32 (MMCHS_STAT, CC);
break;
}
MmioOr32(CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
//Software reset of the MMCHS host controller.
- MmioWrite32(MMCHS_SYSCONFIG, SOFTRESET);
+ MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
//Soft reset for all.
- MmioWrite32(MMCHS_SYSCTL, SRA);
+ MmioWrite32 (MMCHS_SYSCTL, SRA);
gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSCTL) & SRA) != 0x0);
//MMCHS Controller default initialization
MmioOr32(MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
- MmioWrite32(MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
+ MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
//Enable internal clock
MmioOr32(MMCHS_SYSCTL, ICE);
BOOLEAN SDCmd8Supported = FALSE;
//Enable interrupts.
- MmioWrite32(MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
+ MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
//Controller INIT procedure start.
MmioOr32(MMCHS_CON, INIT);
- MmioWrite32(MMCHS_CMD, 0x00000000);
+ MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC));
//Wait for 1 ms
MmioOr32(MMCHS_STAT, CC);
//Retry INIT procedure.
- MmioWrite32(MMCHS_CMD, 0x00000000);
+ MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC));
//End initialization sequence
//Write block worth of data.
for (Count = 0; Count < DataSize; Count++) {
- MmioWrite32(MMCHS_DATA, *DataBuffer++);
+ MmioWrite32 (MMCHS_DATA, *DataBuffer++);
}
break;
UINT8 Data = 0;
// Take USB host out of force-standby mode
- MmioWrite32(UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
+ MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
- MmioWrite32(UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
+ MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
// USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
- MmioWrite32(GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
+ MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
volatile UINTN gVector;
-/**\r
- C Interrupt Handler calledin the interrupt context when Source interrupt is active.\r
-\r
- @param Source Source of the interrupt. Hardware routing off a specific platform defines\r
- what source means.\r
- @param SystemContext Pointer to system register context. Mostly used by debuggers and will\r
- update the system context after the return from the interrupt if \r
- modified. Don't change these values unless you know what you are doing\r
-\r
+/**
+
+ C Interrupt Handler calledin the interrupt context when Source interrupt is active.
+
+
+
+ @param Source Source of the interrupt. Hardware routing off a specific platform defines
+
+ what source means.
+
+ @param SystemContext Pointer to system register context. Mostly used by debuggers and will
+
+ update the system context after the return from the interrupt if
+
+ modified. Don't change these values unless you know what you are doing
+
+
+
**/
VOID
EFIAPI
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
- EFI_TPL OriginalTPL;\r
-\r
- //\r
- // DXE core uses this callback for the EFI timer tick. The DXE core uses locks \r
- // that raise to TPL_HIGH and then restore back to current level. Thus we need\r
- // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick. \r
- //\r
- OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
+ EFI_TPL OriginalTPL;
+
+
+
+ //
+
+ // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
+
+ // that raise to TPL_HIGH and then restore back to current level. Thus we need
+
+ // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
+
+ //
+
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
if (mTimerPeriodicCallback) {
mTimerPeriodicCallback(SystemContext);
}
// Clear all timer interrupts
- MmioWrite32(TISR, TISR_CLEAR_ALL);
+ MmioWrite32 (TISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing
while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
gBS->RestoreTPL (OriginalTPL);
}
-/**\r
- This function registers the handler NotifyFunction so it is called every time \r
- the timer interrupt fires. It also passes the amount of time since the last \r
- handler call to the NotifyFunction. If NotifyFunction is NULL, then the \r
- handler is unregistered. If the handler is registered, then EFI_SUCCESS is \r
- returned. If the CPU does not support registering a timer interrupt handler, \r
- then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler \r
- when a handler is already registered, then EFI_ALREADY_STARTED is returned. \r
- If an attempt is made to unregister a handler when a handler is not registered, \r
- then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to \r
- register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR \r
- is returned.\r
-\r
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
- @param NotifyFunction The function to call when a timer interrupt fires. This\r
- function executes at TPL_HIGH_LEVEL. The DXE Core will\r
- register a handler for the timer interrupt, so it can know\r
- how much time has passed. This information is used to\r
- signal timer based events. NULL will unregister the handler.\r
-\r
- @retval EFI_SUCCESS The timer handler was registered.\r
- @retval EFI_UNSUPPORTED The platform does not support timer interrupts.\r
- @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already\r
- registered.\r
- @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not\r
- previously registered.\r
- @retval EFI_DEVICE_ERROR The timer handler could not be registered.\r
-\r
-**/\r
+/**
+
+ This function registers the handler NotifyFunction so it is called every time
+
+ the timer interrupt fires. It also passes the amount of time since the last
+
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+
+ returned. If the CPU does not support registering a timer interrupt handler,
+
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+
+ If an attempt is made to unregister a handler when a handler is not registered,
+
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+
+ is returned.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+
+ register a handler for the timer interrupt, so it can know
+
+ how much time has passed. This information is used to
+
+ signal timer based events. NULL will unregister the handler.
+
+
+
+ @retval EFI_SUCCESS The timer handler was registered.
+
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+
+ registered.
+
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+
+ previously registered.
+
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+
+
+**/
+
EFI_STATUS
EFIAPI
TimerDriverRegisterHandler (
return EFI_SUCCESS;
}
-/**\r
- This function adjusts the period of timer interrupts to the value specified \r
- by TimerPeriod. If the timer period is updated, then the selected timer \r
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If \r
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. \r
- If an error occurs while attempting to update the timer period, then the \r
- timer hardware will be put back in its state prior to this call, and \r
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt \r
- is disabled. This is not the same as disabling the CPU's interrupts. \r
- Instead, it must either turn off the timer hardware, or it must adjust the \r
- interrupt controller so that a CPU interrupt is not generated when the timer \r
- interrupt fires. \r
-\r
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
- @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If\r
- the timer hardware is not programmable, then EFI_UNSUPPORTED is\r
- returned. If the timer is programmable, then the timer period\r
- will be rounded up to the nearest timer period that is supported\r
- by the timer hardware. If TimerPeriod is set to 0, then the\r
- timer interrupts will be disabled.\r
-\r
- @retval EFI_SUCCESS The timer period was changed.\r
- @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.\r
- @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.\r
-\r
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+
+ by TimerPeriod. If the timer period is updated, then the selected timer
+
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+
+ If an error occurs while attempting to update the timer period, then the
+
+ timer hardware will be put back in its state prior to this call, and
+
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+
+ is disabled. This is not the same as disabling the CPU's interrupts.
+
+ Instead, it must either turn off the timer hardware, or it must adjust the
+
+ interrupt controller so that a CPU interrupt is not generated when the timer
+
+ interrupt fires.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+
+ returned. If the timer is programmable, then the timer period
+
+ will be rounded up to the nearest timer period that is supported
+
+ by the timer hardware. If TimerPeriod is set to 0, then the
+
+ timer interrupts will be disabled.
+
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+
+
**/
EFI_STATUS
EFIAPI
if (TimerPeriod == 0) {
// Turn off GPTIMER3
- MmioWrite32(TCLR, TCLR_ST_OFF);
+ MmioWrite32 (TCLR, TCLR_ST_OFF);
Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
} else {
// Set GPTIMER3 Load register
LoadValue = (INT32) -TimerCount;
- MmioWrite32(TLDR, LoadValue);
- MmioWrite32(TCRR, LoadValue);
+ MmioWrite32 (TLDR, LoadValue);
+ MmioWrite32 (TCRR, LoadValue);
// Enable Overflow interrupt
- MmioWrite32(TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
+ MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow
- MmioWrite32(TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
+ MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
}
}
-/**\r
- This function retrieves the period of timer interrupts in 100 ns units, \r
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod \r
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is \r
- returned, then the timer is currently disabled.\r
-\r
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
- @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If\r
- 0 is returned, then the timer is currently disabled.\r
-\r
- @retval EFI_SUCCESS The timer period was returned in TimerPeriod.\r
- @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.\r
-\r
+/**
+
+ This function retrieves the period of timer interrupts in 100 ns units,
+
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+
+ returned, then the timer is currently disabled.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+
+ 0 is returned, then the timer is currently disabled.
+
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+
+
**/
EFI_STATUS
EFIAPI
return EFI_SUCCESS;
}
-/**\r
- This function generates a soft timer interrupt. If the platform does not support soft \r
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. \r
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() \r
- service, then a soft timer interrupt will be generated. If the timer interrupt is \r
- enabled when this service is called, then the registered handler will be invoked. The \r
- registered handler should not be able to distinguish a hardware-generated timer \r
- interrupt from a software-generated timer interrupt.\r
-\r
- @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r
-\r
- @retval EFI_SUCCESS The soft timer interrupt was generated.\r
- @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.\r
-\r
+/**
+
+ This function generates a soft timer interrupt. If the platform does not support soft
+
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+
+ enabled when this service is called, then the registered handler will be invoked. The
+
+ registered handler should not be able to distinguish a hardware-generated timer
+
+ interrupt from a software-generated timer interrupt.
+
+
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+
+ @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
+
+
+
**/
EFI_STATUS
EFIAPI
}
-/**\r
- Interface stucture for the Timer Architectural Protocol.\r
-\r
- @par Protocol Description:\r
- This protocol provides the services to initialize a periodic timer \r
- interrupt, and to register a handler that is called each time the timer\r
- interrupt fires. It may also provide a service to adjust the rate of the\r
- periodic timer interrupt. When a timer interrupt occurs, the handler is \r
- passed the amount of time that has passed since the previous timer \r
- interrupt.\r
-\r
- @param RegisterHandler\r
- Registers a handler that will be called each time the \r
- timer interrupt fires. TimerPeriod defines the minimum \r
- time between timer interrupts, so TimerPeriod will also \r
- be the minimum time between calls to the registered \r
- handler.\r
-\r
- @param SetTimerPeriod\r
- Sets the period of the timer interrupt in 100 nS units. \r
- This function is optional, and may return EFI_UNSUPPORTED. \r
- If this function is supported, then the timer period will \r
- be rounded up to the nearest supported timer period.\r
-\r
- @param GetTimerPeriod\r
- Retrieves the period of the timer interrupt in 100 nS units.\r
-\r
- @param GenerateSoftInterrupt\r
- Generates a soft timer interrupt that simulates the firing of \r
- the timer interrupt. This service can be used to invoke the \r
- registered handler if the timer interrupt has been masked for \r
- a period of time.\r
-\r
+/**
+
+ Interface stucture for the Timer Architectural Protocol.
+
+
+
+ @par Protocol Description:
+
+ This protocol provides the services to initialize a periodic timer
+
+ interrupt, and to register a handler that is called each time the timer
+
+ interrupt fires. It may also provide a service to adjust the rate of the
+
+ periodic timer interrupt. When a timer interrupt occurs, the handler is
+
+ passed the amount of time that has passed since the previous timer
+
+ interrupt.
+
+
+
+ @param RegisterHandler
+
+ Registers a handler that will be called each time the
+
+ timer interrupt fires. TimerPeriod defines the minimum
+
+ time between timer interrupts, so TimerPeriod will also
+
+ be the minimum time between calls to the registered
+
+ handler.
+
+
+
+ @param SetTimerPeriod
+
+ Sets the period of the timer interrupt in 100 nS units.
+
+ This function is optional, and may return EFI_UNSUPPORTED.
+
+ If this function is supported, then the timer period will
+
+ be rounded up to the nearest supported timer period.
+
+
+
+ @param GetTimerPeriod
+
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+
+
+ @param GenerateSoftInterrupt
+
+ Generates a soft timer interrupt that simulates the firing of
+
+ the timer interrupt. This service can be used to invoke the
+
+ registered handler if the timer interrupt has been masked for
+
+ a period of time.
+
+
+
**/
EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
};
-/**\r
- Initialize the state information for the Timer Architectural Protocol and\r
- the Timer Debug support protocol that allows the debugger to break into a\r
- running program.\r
-\r
- @param ImageHandle of the loaded driver\r
- @param SystemTable Pointer to the System Table\r
-\r
- @retval EFI_SUCCESS Protocol registered\r
- @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
- @retval EFI_DEVICE_ERROR Hardware problems\r
-\r
+/**
+
+ Initialize the state information for the Timer Architectural Protocol and
+
+ the Timer Debug support protocol that allows the debugger to break into a
+
+ running program.
+
+
+
+ @param ImageHandle of the loaded driver
+
+ @param SystemTable Pointer to the System Table
+
+
+
+ @retval EFI_SUCCESS Protocol registered
+
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+
+
**/
EFI_STATUS
EFIAPI
projects / mirror_edk2.git / commitdiff