OvmfPkg: factor the MMIO aperture shared by all PCI root bridges into PCDs

Going forward, two modules will need to know about the aperture:
PlatformPei (as before), and OVMF's upcoming PciHostBridgeLib instance
(because the core PciHostBridgeDxe driver requires the library to state
the exact apertures for all root bridges).

On QEMU, all root bridges share the same MMIO aperture, hence one pair of
PCDs suffices.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec
index 77c1f568afb0a990ba285ccd4e7adcd0199a8249..784542f62368d59f99f127e4c192b0394a033958 100644 (file)
--- a/OvmfPkg/OvmfPkg.dec
+++ b/OvmfPkg/OvmfPkg.dec
@@ -125,6 +125,11 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r
 \r
+  ## The 32-bit MMIO aperture shared by all PCI root bridges.\r
+  #\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r
+\r
 [PcdsFeatureFlag]\r
   gUefiOvmfPkgTokenSpaceGuid.PcdSecureBootEnable|FALSE|BOOLEAN|3\r
   gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 83b44fb0dc759fc98f1144195d8d585fe3de6c5f..3a6c127d598f3ab9d7c7c5e90da2e4fcbf1e858f 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -428,6 +428,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0\r
 \r
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0\r
 \r

diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index af7b91f778086dc09b4363bc7df3511c9659836c..a8dd42ed61d763f15b9c223bc3d7a01be4590814 100644 (file)
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -434,6 +434,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0\r
 \r
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0\r
 \r

diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index 006d087455225908aa19657798642dd33b94249f..dc7a35ea46ef2517cb112b70f1b5731ece9fa575 100644 (file)
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -433,6 +433,8 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0\r
 \r
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0\r
 \r

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 1df0f383bca3272be9c0beaf85c3d1f05665cb06..7d0941209f252bb5db0c1e0341081f567f1cf9a5 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -213,6 +213,7 @@ MemMapInitialization (
   if (!mXen) {\r
     UINT32  TopOfLowRam;\r
     UINT32  PciBase;\r
+    UINT32  PciSize;\r
 \r
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
@@ -240,7 +241,10 @@ MemMapInitialization (
     // 0xFED20000    gap                          896 KB\r
     // 0xFEE00000    LAPIC                          1 MB\r
     //\r
-    AddIoMemoryRangeHob (PciBase, 0xFC000000);\r
+    PciSize = 0xFC000000 - PciBase;\r
+    AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
+    PcdSet64 (PcdPciMmio32Base, PciBase);\r
+    PcdSet64 (PcdPciMmio32Size, PciSize);\r
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r

diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf
index 22250c061c4730a64d5496baabbf23b4a008c76c..8480839efc8ec2d6016f019094b18c518551d601 100644 (file)
--- a/OvmfPkg/PlatformPei/PlatformPei.inf
+++ b/OvmfPkg/PlatformPei/PlatformPei.inf
@@ -77,6 +77,8 @@
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\r
   gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase\r
   gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size\r
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd\r
   gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize\r