CorebootModulePkg and CorebootPayloadPkg originally supports coreboot only.
In order to support other bootloaders, such as Slim Bootloader, they need
be updated to be more generic.
UEFI Payload (UefiPayloadPkg) a converged package from CorebootModulePkg
and CorebootPayloadPkg with following updates:
a. Support both coreboot and Slim Bootloader
b. Removed SataControllerDxe and BaseSerialPortLib16550 to use EDK2 modules
c. Support passing bootloader parameter to UEFI payload, e.g. coreboot
table from coreboot or HOB list from Slim Bootloader
d. Using GraphicsOutputDxe from EDK2 with minor change instead of FbGop
e. Remove the dependency to IntelFrameworkPkg and IntelFrameworkModulePkg
and QuarkSocPkg
f. Use BaseDebugLibSerialPort library as DebugLib
g. Use HPET timer, drop legacy 8254 timer support
h. Use BaseXApicX2ApicLib instead of BaseXApicLib
i. Remove HOB gUefiFrameBufferInfoGuid to use EDK2 graphics HOBs.
j. Other clean ups
On how UefiPayloadPkg could work with coreboot/Slim Bootloader, please
refer UefiPayloadPkg/BuildAndIntegrationInstructions.txt
Once UefiPayloadPkg is checked-in, CorebootModulePkg and CorebootPayloadPkg
could be retired.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
--- /dev/null
+/** @file\r
+ This driver will report some MMIO/IO resources to dxe core, extract smbios and acpi\r
+ tables from bootloader.\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+#include "BlSupportDxe.h"\r
+\r
+/**\r
+ Reserve MMIO/IO resource in GCD\r
+\r
+ @param IsMMIO Flag of whether it is mmio resource or io resource.\r
+ @param GcdType Type of the space.\r
+ @param BaseAddress Base address of the space.\r
+ @param Length Length of the space.\r
+ @param Alignment Align with 2^Alignment\r
+ @param ImageHandle Handle for the image of this driver.\r
+\r
+ @retval EFI_SUCCESS Reserve successful\r
+**/\r
+EFI_STATUS\r
+ReserveResourceInGcd (\r
+ IN BOOLEAN IsMMIO,\r
+ IN UINTN GcdType,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINTN Alignment,\r
+ IN EFI_HANDLE ImageHandle\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ if (IsMMIO) {\r
+ Status = gDS->AddMemorySpace (\r
+ GcdType,\r
+ BaseAddress,\r
+ Length,\r
+ EFI_MEMORY_UC\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "Failed to add memory space :0x%lx 0x%lx\n",\r
+ BaseAddress,\r
+ Length\r
+ ));\r
+ }\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = gDS->AllocateMemorySpace (\r
+ EfiGcdAllocateAddress,\r
+ GcdType,\r
+ Alignment,\r
+ Length,\r
+ &BaseAddress,\r
+ ImageHandle,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else {\r
+ Status = gDS->AddIoSpace (\r
+ GcdType,\r
+ BaseAddress,\r
+ Length\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = gDS->AllocateIoSpace (\r
+ EfiGcdAllocateAddress,\r
+ GcdType,\r
+ Alignment,\r
+ Length,\r
+ &BaseAddress,\r
+ ImageHandle,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Main entry for the bootloader support DXE module.\r
+\r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
+ @param[in] SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS The entry point is executed successfully.\r
+ @retval other Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BlDxeEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HOB_GUID_TYPE *GuidHob;\r
+ SYSTEM_TABLE_INFO *SystemTableInfo;\r
+ EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;\r
+\r
+ Status = EFI_SUCCESS;\r
+ //\r
+ // Report MMIO/IO Resources\r
+ //\r
+ Status = ReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFEC00000, SIZE_4KB, 0, SystemTable); // IOAPIC\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = ReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFED00000, SIZE_1KB, 0, SystemTable); // HPET\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Find the system table information guid hob\r
+ //\r
+ GuidHob = GetFirstGuidHob (&gUefiSystemTableInfoGuid);\r
+ ASSERT (GuidHob != NULL);\r
+ SystemTableInfo = (SYSTEM_TABLE_INFO *)GET_GUID_HOB_DATA (GuidHob);\r
+\r
+ //\r
+ // Install Acpi Table\r
+ //\r
+ if (SystemTableInfo->AcpiTableBase != 0 && SystemTableInfo->AcpiTableSize != 0) {\r
+ DEBUG ((DEBUG_ERROR, "Install Acpi Table at 0x%lx, length 0x%x\n", SystemTableInfo->AcpiTableBase, SystemTableInfo->AcpiTableSize));\r
+ Status = gBS->InstallConfigurationTable (&gEfiAcpiTableGuid, (VOID *)(UINTN)SystemTableInfo->AcpiTableBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Install Smbios Table\r
+ //\r
+ if (SystemTableInfo->SmbiosTableBase != 0 && SystemTableInfo->SmbiosTableSize != 0) {\r
+ DEBUG ((DEBUG_ERROR, "Install Smbios Table at 0x%lx, length 0x%x\n", SystemTableInfo->SmbiosTableBase, SystemTableInfo->SmbiosTableSize));\r
+ Status = gBS->InstallConfigurationTable (&gEfiSmbiosTableGuid, (VOID *)(UINTN)SystemTableInfo->SmbiosTableBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Find the frame buffer information and update PCDs\r
+ //\r
+ GuidHob = GetFirstGuidHob (&gEfiGraphicsInfoHobGuid);\r
+ if (GuidHob != NULL) {\r
+ GfxInfo = (EFI_PEI_GRAPHICS_INFO_HOB *)GET_GUID_HOB_DATA (GuidHob);\r
+ Status = PcdSet32S (PcdVideoHorizontalResolution, GfxInfo->GraphicsMode.HorizontalResolution);\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = PcdSet32S (PcdVideoVerticalResolution, GfxInfo->GraphicsMode.VerticalResolution);\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = PcdSet32S (PcdSetupVideoHorizontalResolution, GfxInfo->GraphicsMode.HorizontalResolution);\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = PcdSet32S (PcdSetupVideoVerticalResolution, GfxInfo->GraphicsMode.VerticalResolution);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ The header file of bootloader support DXE.\r
+\r
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+#ifndef __DXE_BOOTLOADER_SUPPORT_H__\r
+#define __DXE_BOOTLOADER_SUPPORT_H__\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+\r
+#include <Guid/Acpi.h>\r
+#include <Guid/SmBios.h>\r
+#include <Guid/SystemTableInfoGuid.h>\r
+#include <Guid/AcpiBoardInfoGuid.h>\r
+#include <Guid/GraphicsInfoHob.h>\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Bootloader Support DXE Module\r
+#\r
+# Report some MMIO/IO resources to dxe core, extract smbios and acpi tables\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BlSupportDxe\r
+ FILE_GUID = C68DAA4E-7AB5-41e8-A91D-5954421053F3\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = BlDxeEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ BlSupportDxe.c\r
+ BlSupportDxe.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ DxeServicesTableLib\r
+ DebugLib\r
+ BaseMemoryLib\r
+ UefiLib\r
+ HobLib\r
+\r
+[Guids]\r
+ gEfiAcpiTableGuid\r
+ gEfiSmbiosTableGuid\r
+ gUefiSystemTableInfoGuid\r
+ gUefiAcpiBoardInfoGuid\r
+ gEfiGraphicsInfoHobGuid\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+ This PEIM will parse bootloader information and report resource information into pei core.\r
+ This file contains the main entrypoint of the PEIM.\r
+\r
+Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+#include "BlSupportPei.h"\r
+\r
+#define LEGACY_8259_MASK_REGISTER_MASTER 0x21\r
+#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1\r
+\r
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
+ { EfiACPIReclaimMemory, FixedPcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory) },\r
+ { EfiACPIMemoryNVS, FixedPcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS) },\r
+ { EfiReservedMemoryType, FixedPcdGet32 (PcdMemoryTypeEfiReservedMemoryType) },\r
+ { EfiRuntimeServicesData, FixedPcdGet32 (PcdMemoryTypeEfiRuntimeServicesData) },\r
+ { EfiRuntimeServicesCode, FixedPcdGet32 (PcdMemoryTypeEfiRuntimeServicesCode) },\r
+ { EfiMaxMemoryType, 0 }\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
+ {\r
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+ &gEfiPeiMasterBootModePpiGuid,\r
+ NULL\r
+ }\r
+};\r
+\r
+EFI_PEI_GRAPHICS_DEVICE_INFO_HOB mDefaultGraphicsDeviceInfo = {\r
+ MAX_UINT16, MAX_UINT16, MAX_UINT16, MAX_UINT16, MAX_UINT8, MAX_UINT8\r
+};\r
+\r
+/**\r
+ Create memory mapped io resource hob.\r
+\r
+ @param MmioBase Base address of the memory mapped io range\r
+ @param MmioSize Length of the memory mapped io range\r
+\r
+**/\r
+VOID\r
+BuildMemoryMappedIoRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MmioBase,\r
+ UINT64 MmioSize\r
+ )\r
+{\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED),\r
+ MmioBase,\r
+ MmioSize\r
+ );\r
+\r
+ BuildMemoryAllocationHob (\r
+ MmioBase,\r
+ MmioSize,\r
+ EfiMemoryMappedIO\r
+ );\r
+}\r
+\r
+/**\r
+ Check the integrity of firmware volume header\r
+\r
+ @param[in] FwVolHeader A pointer to a firmware volume header\r
+\r
+ @retval TRUE The firmware volume is consistent\r
+ @retval FALSE The firmware volume has corrupted.\r
+\r
+**/\r
+STATIC\r
+BOOLEAN\r
+IsFvHeaderValid (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader\r
+ )\r
+{\r
+ UINT16 Checksum;\r
+\r
+ // Skip nv storage fv\r
+ if (CompareMem (&FwVolHeader->FileSystemGuid, &gEfiFirmwareFileSystem2Guid, sizeof(EFI_GUID)) != 0 ) {\r
+ return FALSE;\r
+ }\r
+\r
+ if ( (FwVolHeader->Revision != EFI_FVH_REVISION) ||\r
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
+ (FwVolHeader->FvLength == ((UINTN) -1)) ||\r
+ ((FwVolHeader->HeaderLength & 0x01 ) !=0) ) {\r
+ return FALSE;\r
+ }\r
+\r
+ Checksum = CalculateCheckSum16 ((UINT16 *) FwVolHeader, FwVolHeader->HeaderLength);\r
+ if (Checksum != 0) {\r
+ DEBUG (( DEBUG_ERROR,\r
+ "ERROR - Invalid Firmware Volume Header Checksum, change 0x%04x to 0x%04x\r\n",\r
+ FwVolHeader->Checksum,\r
+ (UINT16)( Checksum + FwVolHeader->Checksum )));\r
+ return TRUE; //FALSE; Need update UEFI build tool when patching entrypoin @start of fd.\r
+ }\r
+\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Install FvInfo PPI and create fv hobs for remained fvs\r
+\r
+**/\r
+VOID\r
+PeiReportRemainedFvs (\r
+ VOID\r
+ )\r
+{\r
+ UINT8* TempPtr;\r
+ UINT8* EndPtr;\r
+\r
+ TempPtr = (UINT8* )(UINTN) PcdGet32 (PcdPayloadFdMemBase);\r
+ EndPtr = (UINT8* )(UINTN) (PcdGet32 (PcdPayloadFdMemBase) + PcdGet32 (PcdPayloadFdMemSize));\r
+\r
+ for (;TempPtr < EndPtr;) {\r
+ if (IsFvHeaderValid ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)) {\r
+ if (TempPtr != (UINT8* )(UINTN) PcdGet32 (PcdPayloadFdMemBase)) {\r
+ // Skip the PEI FV\r
+ DEBUG((DEBUG_INFO, "Found one valid fv : 0x%lx.\n", TempPtr, ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength));\r
+\r
+ PeiServicesInstallFvInfoPpi (\r
+ NULL,\r
+ (VOID *) (UINTN) TempPtr,\r
+ (UINT32) (UINTN) ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength,\r
+ NULL,\r
+ NULL\r
+ );\r
+ BuildFvHob ((EFI_PHYSICAL_ADDRESS)(UINTN) TempPtr, ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength);\r
+ }\r
+ }\r
+ TempPtr += ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Find the board related info from ACPI table\r
+\r
+ @param AcpiTableBase ACPI table start address in memory\r
+ @param AcpiBoardInfo Pointer to the acpi board info strucutre\r
+\r
+ @retval RETURN_SUCCESS Successfully find out all the required information.\r
+ @retval RETURN_NOT_FOUND Failed to find the required info.\r
+\r
+**/\r
+RETURN_STATUS\r
+ParseAcpiInfo (\r
+ IN UINT64 AcpiTableBase,\r
+ OUT ACPI_BOARD_INFO *AcpiBoardInfo\r
+ )\r
+{\r
+ EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;\r
+ EFI_ACPI_DESCRIPTION_HEADER *Rsdt;\r
+ UINT32 *Entry32;\r
+ UINTN Entry32Num;\r
+ EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;\r
+ EFI_ACPI_DESCRIPTION_HEADER *Xsdt;\r
+ UINT64 *Entry64;\r
+ UINTN Entry64Num;\r
+ UINTN Idx;\r
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *MmCfgHdr;\r
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *MmCfgBase;\r
+\r
+ Rsdp = (EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *)(UINTN)AcpiTableBase;\r
+ DEBUG ((DEBUG_INFO, "Rsdp at 0x%p\n", Rsdp));\r
+ DEBUG ((DEBUG_INFO, "Rsdt at 0x%x, Xsdt at 0x%lx\n", Rsdp->RsdtAddress, Rsdp->XsdtAddress));\r
+\r
+ //\r
+ // Search Rsdt First\r
+ //\r
+ Fadt = NULL;\r
+ MmCfgHdr = NULL;\r
+ Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->RsdtAddress);\r
+ if (Rsdt != NULL) {\r
+ Entry32 = (UINT32 *)(Rsdt + 1);\r
+ Entry32Num = (Rsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 2;\r
+ for (Idx = 0; Idx < Entry32Num; Idx++) {\r
+ if (*(UINT32 *)(UINTN)(Entry32[Idx]) == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {\r
+ Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)(UINTN)(Entry32[Idx]);\r
+ DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));\r
+ }\r
+\r
+ if (*(UINT32 *)(UINTN)(Entry32[Idx]) == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {\r
+ MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)(UINTN)(Entry32[Idx]);\r
+ DEBUG ((DEBUG_INFO, "Found MM config address in Rsdt\n"));\r
+ }\r
+\r
+ if ((Fadt != NULL) && (MmCfgHdr != NULL)) {\r
+ goto Done;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Search Xsdt Second\r
+ //\r
+ Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->XsdtAddress);\r
+ if (Xsdt != NULL) {\r
+ Entry64 = (UINT64 *)(Xsdt + 1);\r
+ Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;\r
+ for (Idx = 0; Idx < Entry64Num; Idx++) {\r
+ if (*(UINT32 *)(UINTN)(Entry64[Idx]) == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {\r
+ Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)(UINTN)(Entry64[Idx]);\r
+ DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));\r
+ }\r
+\r
+ if (*(UINT32 *)(UINTN)(Entry64[Idx]) == EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE) {\r
+ MmCfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *)(UINTN)(Entry32[Idx]);\r
+ DEBUG ((DEBUG_INFO, "Found MM config address in Xsdt\n"));\r
+ }\r
+\r
+ if ((Fadt != NULL) && (MmCfgHdr != NULL)) {\r
+ goto Done;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (Fadt == NULL) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+Done:\r
+\r
+ AcpiBoardInfo->PmCtrlRegBase = Fadt->Pm1aCntBlk;\r
+ AcpiBoardInfo->PmTimerRegBase = Fadt->PmTmrBlk;\r
+ AcpiBoardInfo->ResetRegAddress = Fadt->ResetReg.Address;\r
+ AcpiBoardInfo->ResetValue = Fadt->ResetValue;\r
+ AcpiBoardInfo->PmEvtBase = Fadt->Pm1aEvtBlk;\r
+ AcpiBoardInfo->PmGpeEnBase = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
+\r
+ if (MmCfgHdr != NULL) {\r
+ MmCfgBase = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)((UINT8*) MmCfgHdr + sizeof (*MmCfgHdr));\r
+ AcpiBoardInfo->PcieBaseAddress = MmCfgBase->BaseAddress;\r
+ } else {\r
+ AcpiBoardInfo->PcieBaseAddress = 0;\r
+ }\r
+ DEBUG ((DEBUG_INFO, "PmCtrl Reg 0x%lx\n", AcpiBoardInfo->PmCtrlRegBase));\r
+ DEBUG ((DEBUG_INFO, "PmTimer Reg 0x%lx\n", AcpiBoardInfo->PmTimerRegBase));\r
+ DEBUG ((DEBUG_INFO, "Reset Reg 0x%lx\n", AcpiBoardInfo->ResetRegAddress));\r
+ DEBUG ((DEBUG_INFO, "Reset Value 0x%x\n", AcpiBoardInfo->ResetValue));\r
+ DEBUG ((DEBUG_INFO, "PmEvt Reg 0x%lx\n", AcpiBoardInfo->PmEvtBase));\r
+ DEBUG ((DEBUG_INFO, "PmGpeEn Reg 0x%lx\n", AcpiBoardInfo->PmGpeEnBase));\r
+ DEBUG ((DEBUG_INFO, "PcieBaseAddr 0x%lx\n", AcpiBoardInfo->PcieBaseAddress));\r
+\r
+ //\r
+ // Verify values for proper operation\r
+ //\r
+ ASSERT(Fadt->Pm1aCntBlk != 0);\r
+ ASSERT(Fadt->PmTmrBlk != 0);\r
+ ASSERT(Fadt->ResetReg.Address != 0);\r
+ ASSERT(Fadt->Pm1aEvtBlk != 0);\r
+ ASSERT(Fadt->Gpe0Blk != 0);\r
+\r
+ DEBUG_CODE_BEGIN ();\r
+ BOOLEAN SciEnabled;\r
+\r
+ //\r
+ // Check the consistency of SCI enabling\r
+ //\r
+\r
+ //\r
+ // Get SCI_EN value\r
+ //\r
+ if (Fadt->Pm1CntLen == 4) {\r
+ SciEnabled = (IoRead32 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;\r
+ } else {\r
+ //\r
+ // if (Pm1CntLen == 2), use 16 bit IO read;\r
+ // if (Pm1CntLen != 2 && Pm1CntLen != 4), use 16 bit IO read as a fallback\r
+ //\r
+ SciEnabled = (IoRead16 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;\r
+ }\r
+\r
+ if (!(Fadt->Flags & EFI_ACPI_5_0_HW_REDUCED_ACPI) &&\r
+ (Fadt->SmiCmd == 0) &&\r
+ !SciEnabled) {\r
+ //\r
+ // The ACPI enabling status is inconsistent: SCI is not enabled but ACPI\r
+ // table does not provide a means to enable it through FADT->SmiCmd\r
+ //\r
+ DEBUG ((DEBUG_ERROR, "ERROR: The ACPI enabling status is inconsistent: SCI is not"\r
+ " enabled but the ACPI table does not provide a means to enable it through FADT->SmiCmd."\r
+ " This may cause issues in OS.\n"));\r
+ }\r
+ DEBUG_CODE_END ();\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+MemInfoCallback (\r
+ IN MEMROY_MAP_ENTRY *MemoryMapEntry,\r
+ IN VOID *Params\r
+ )\r
+{\r
+ PAYLOAD_MEM_INFO *MemInfo;\r
+ UINTN Attribue;\r
+ EFI_PHYSICAL_ADDRESS Base;\r
+ EFI_RESOURCE_TYPE Type;\r
+ UINT64 Size;\r
+ UINT32 SystemLowMemTop;\r
+\r
+ Attribue = EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;\r
+\r
+ MemInfo = (PAYLOAD_MEM_INFO *)Params;\r
+ Type = (MemoryMapEntry->Type == 1) ? EFI_RESOURCE_SYSTEM_MEMORY : EFI_RESOURCE_MEMORY_RESERVED;\r
+ Base = MemoryMapEntry->Base;\r
+ Size = MemoryMapEntry->Size;\r
+\r
+ if ((Base < 0x100000) && ((Base + Size) > 0x100000)) {\r
+ Size -= (0x100000 - Base);\r
+ Base = 0x100000;\r
+ }\r
+\r
+ if (Base >= 0x100000) {\r
+ if (Type == EFI_RESOURCE_SYSTEM_MEMORY) {\r
+ if (Base < 0x100000000ULL) {\r
+ MemInfo->UsableLowMemTop = (UINT32)(Base + Size);\r
+ } else {\r
+ Attribue &= ~EFI_RESOURCE_ATTRIBUTE_TESTED;\r
+ }\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ Attribue,\r
+ (EFI_PHYSICAL_ADDRESS)Base,\r
+ Size\r
+ );\r
+ } else if (Type == EFI_RESOURCE_MEMORY_RESERVED) {\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_RESERVED,\r
+ Attribue,\r
+ (EFI_PHYSICAL_ADDRESS)Base,\r
+ Size\r
+ );\r
+ if (Base < 0x100000000ULL) {\r
+ SystemLowMemTop = ((UINT32)(Base + Size) + 0x0FFFFFFF) & 0xF0000000;\r
+ if (SystemLowMemTop > MemInfo->SystemLowMemTop) {\r
+ MemInfo->SystemLowMemTop = SystemLowMemTop;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ This is the entrypoint of PEIM\r
+\r
+ @param FileHandle Handle of the file being invoked.\r
+ @param PeiServices Describes the list of possible PEI Services.\r
+\r
+ @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BlPeiEntryPoint (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 LowMemorySize;\r
+ UINT64 PeiMemSize = SIZE_64MB;\r
+ EFI_PHYSICAL_ADDRESS PeiMemBase = 0;\r
+ UINT32 RegEax;\r
+ UINT8 PhysicalAddressBits;\r
+ PAYLOAD_MEM_INFO PldMemInfo;\r
+ SYSTEM_TABLE_INFO SysTableInfo;\r
+ SYSTEM_TABLE_INFO *NewSysTableInfo;\r
+ ACPI_BOARD_INFO AcpiBoardInfo;\r
+ ACPI_BOARD_INFO *NewAcpiBoardInfo;\r
+ EFI_PEI_GRAPHICS_INFO_HOB GfxInfo;\r
+ EFI_PEI_GRAPHICS_INFO_HOB *NewGfxInfo;\r
+ EFI_PEI_GRAPHICS_DEVICE_INFO_HOB GfxDeviceInfo;\r
+ EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *NewGfxDeviceInfo;\r
+\r
+\r
+ //\r
+ // Report lower 640KB of RAM. Attribute EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ // is intentionally omitted to prevent erasing of the coreboot header\r
+ // record before it is processed by ParseMemoryInfo.\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ (EFI_PHYSICAL_ADDRESS)(0),\r
+ (UINT64)(0xA0000)\r
+ );\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_RESERVED,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ (EFI_PHYSICAL_ADDRESS)(0xA0000),\r
+ (UINT64)(0x60000)\r
+ );\r
+\r
+\r
+ //\r
+ // Parse memory info\r
+ //\r
+ ZeroMem (&PldMemInfo, sizeof(PldMemInfo));\r
+ Status = ParseMemoryInfo (MemInfoCallback, &PldMemInfo);\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Install memory\r
+ //\r
+ LowMemorySize = PldMemInfo.UsableLowMemTop;\r
+ PeiMemBase = (LowMemorySize - PeiMemSize) & (~(BASE_64KB - 1));\r
+ DEBUG ((DEBUG_INFO, "Low memory 0x%lx\n", LowMemorySize));\r
+ DEBUG ((DEBUG_INFO, "SystemLowMemTop 0x%x\n", PldMemInfo.SystemLowMemTop));\r
+ DEBUG ((DEBUG_INFO, "PeiMemBase: 0x%lx.\n", PeiMemBase));\r
+ DEBUG ((DEBUG_INFO, "PeiMemSize: 0x%lx.\n", PeiMemSize));\r
+ Status = PeiServicesInstallPeiMemory (PeiMemBase, PeiMemSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Set cache on the physical memory\r
+ //\r
+ MtrrSetMemoryAttribute (BASE_1MB, LowMemorySize - BASE_1MB, CacheWriteBack);\r
+ MtrrSetMemoryAttribute (0, 0xA0000, CacheWriteBack);\r
+\r
+ //\r
+ // Create Memory Type Information HOB\r
+ //\r
+ BuildGuidDataHob (\r
+ &gEfiMemoryTypeInformationGuid,\r
+ mDefaultMemoryTypeInformation,\r
+ sizeof(mDefaultMemoryTypeInformation)\r
+ );\r
+\r
+ //\r
+ // Create Fv hob\r
+ //\r
+ PeiReportRemainedFvs ();\r
+\r
+ BuildMemoryAllocationHob (\r
+ PcdGet32 (PcdPayloadFdMemBase),\r
+ PcdGet32 (PcdPayloadFdMemSize),\r
+ EfiBootServicesData\r
+ );\r
+\r
+ //\r
+ // Build CPU memory space and IO space hob\r
+ //\r
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= 0x80000008) {\r
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
+ PhysicalAddressBits = (UINT8) RegEax;\r
+ } else {\r
+ PhysicalAddressBits = 36;\r
+ }\r
+\r
+ //\r
+ // Create a CPU hand-off information\r
+ //\r
+ BuildCpuHob (PhysicalAddressBits, 16);\r
+\r
+ //\r
+ // Report Local APIC range\r
+ //\r
+ BuildMemoryMappedIoRangeHob (0xFEC80000, SIZE_512KB);\r
+\r
+ //\r
+ // Boot mode\r
+ //\r
+ Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = PeiServicesInstallPpi (mPpiBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Create guid hob for frame buffer information\r
+ //\r
+ Status = ParseGfxInfo (&GfxInfo);\r
+ if (!EFI_ERROR (Status)) {\r
+ NewGfxInfo = BuildGuidHob (&gEfiGraphicsInfoHobGuid, sizeof (GfxInfo));\r
+ ASSERT (NewGfxInfo != NULL);\r
+ CopyMem (NewGfxInfo, &GfxInfo, sizeof (GfxInfo));\r
+ DEBUG ((DEBUG_INFO, "Created graphics info hob\n"));\r
+ }\r
+\r
+\r
+ Status = ParseGfxDeviceInfo (&GfxDeviceInfo);\r
+ if (!EFI_ERROR (Status)) {\r
+ NewGfxDeviceInfo = BuildGuidHob (&gEfiGraphicsDeviceInfoHobGuid, sizeof (GfxDeviceInfo));\r
+ ASSERT (NewGfxDeviceInfo != NULL);\r
+ CopyMem (NewGfxDeviceInfo, &GfxDeviceInfo, sizeof (GfxDeviceInfo));\r
+ DEBUG ((DEBUG_INFO, "Created graphics device info hob\n"));\r
+ }\r
+\r
+\r
+ //\r
+ // Create guid hob for system tables like acpi table and smbios table\r
+ //\r
+ Status = ParseSystemTable(&SysTableInfo);\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (!EFI_ERROR (Status)) {\r
+ NewSysTableInfo = BuildGuidHob (&gUefiSystemTableInfoGuid, sizeof (SYSTEM_TABLE_INFO));\r
+ ASSERT (NewSysTableInfo != NULL);\r
+ CopyMem (NewSysTableInfo, &SysTableInfo, sizeof (SYSTEM_TABLE_INFO));\r
+ DEBUG ((DEBUG_INFO, "Detected Acpi Table at 0x%lx, length 0x%x\n", SysTableInfo.AcpiTableBase, SysTableInfo.AcpiTableSize));\r
+ DEBUG ((DEBUG_INFO, "Detected Smbios Table at 0x%lx, length 0x%x\n", SysTableInfo.SmbiosTableBase, SysTableInfo.SmbiosTableSize));\r
+ }\r
+\r
+ //\r
+ // Create guid hob for acpi board information\r
+ //\r
+ Status = ParseAcpiInfo (SysTableInfo.AcpiTableBase, &AcpiBoardInfo);\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (!EFI_ERROR (Status)) {\r
+ NewAcpiBoardInfo = BuildGuidHob (&gUefiAcpiBoardInfoGuid, sizeof (ACPI_BOARD_INFO));\r
+ ASSERT (NewAcpiBoardInfo != NULL);\r
+ CopyMem (NewAcpiBoardInfo, &AcpiBoardInfo, sizeof (ACPI_BOARD_INFO));\r
+ DEBUG ((DEBUG_INFO, "Create acpi board info guid hob\n"));\r
+ }\r
+\r
+ //\r
+ // Parse platform specific information.\r
+ //\r
+ Status = ParsePlatformInfo ();\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Error when parsing platform info, Status = %r\n", Status));\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Mask off all legacy 8259 interrupt sources\r
+ //\r
+ IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);\r
+ IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ The header file of bootloader support PEIM.\r
+\r
+Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+\r
+#ifndef __PEI_BOOTLOADER_SUPPORT_H__\r
+#define __PEI_BOOTLOADER_SUPPORT_H__\r
+\r
+#include <PiPei.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BlParseLib.h>\r
+#include <Library/MtrrLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PlatformSupportLib.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Guid/SystemTableInfoGuid.h>\r
+#include <Guid/AcpiBoardInfoGuid.h>\r
+#include <Guid/GraphicsInfoHob.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r
+\r
+typedef struct {\r
+ UINT32 UsableLowMemTop;\r
+ UINT32 SystemLowMemTop;\r
+} PAYLOAD_MEM_INFO;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Bootloader Support PEI Module\r
+#\r
+# Parses bootloader information and report resource information into pei core. It will install\r
+# the memory as required.\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BlSupportPeim\r
+ FILE_GUID = 352C6AF8-315B-4bd6-B04F-31D4ED1EBE57\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = BlPeiEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ BlSupportPei.c\r
+ BlSupportPei.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFsp2Pkg/IntelFsp2Pkg.dec\r
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+\r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ PeiServicesLib\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ HobLib\r
+ PcdLib\r
+ BlParseLib\r
+ MtrrLib\r
+ IoLib\r
+ PlatformSupportLib\r
+\r
+[Guids]\r
+ gEfiMemoryTypeInformationGuid\r
+ gEfiFirmwareFileSystem2Guid\r
+ gUefiSystemTableInfoGuid\r
+ gEfiGraphicsInfoHobGuid\r
+ gEfiGraphicsDeviceInfoHobGuid\r
+ gUefiAcpiBoardInfoGuid\r
+\r
+[Ppis]\r
+ gEfiPeiMasterBootModePpiGuid\r
+\r
+[Pcd]\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemBase\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemSize\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+================================================================================\r
+Build And Integration Instructions\r
+2019 March 27th\r
+================================================================================\r
+\r
+================================================================================\r
+DISCLAIMER\r
+================================================================================\r
+This release note as well as the software described in it is furnished under license\r
+and may only be used or copied in accordance with the terms of the license. The\r
+information in this manual is furnished for informational use only, is subject to\r
+change without notice, and should not be construed as a commitment by Intel Corporation.\r
+Intel Corporation assumes no responsibility or liability for any errors or inaccuracies\r
+that may appear in this document or any software that may be provided in association\r
+with this document.\r
+Except as permitted by such license, no part of this document may be reproduced,\r
+stored in a retrieval system, or transmitted in any form or by any means without\r
+the express written consent of Intel Corporation.\r
+\r
+================================================================================\r
+ INDEX\r
+================================================================================\r
+A. INTRODUCTION\r
+B. HOW TO BUILD\r
+C. HOW TO INTEGRATE INTO COREBOOT\r
+D. HOW TO INTEGRATE INTO SLIM BOOTLOADER\r
+\r
+================================================================================\r
+A. INTRODUCTION\r
+================================================================================\r
+This document provides instructions on how to build UEFI Payload and how to\r
+integrate it into coreboot or Slim Bootloader firmware.\r
+\r
+================================================================================\r
+B. HOW TO BUILD\r
+================================================================================\r
+1. Run the below two commands in windows command prompt window:\r
+ edksetup.bat\r
+\r
+ For debug ia32 build:\r
+ build -a IA32 -p UefiPayloadPkg\UefiPayloadPkgIa32.dsc -b DEBUG -t <ToolChain> -D BOOTLOADER=<Bootloader>\r
+\r
+ For release ia32 build:\r
+ build -a IA32 -p UefiPayloadPkg\UefiPayloadPkgIa32.dsc -b RELEASE -t <ToolChain> -D BOOTLOADER=<Bootloader>\r
+\r
+ For debug X64 build:\r
+ build -a IA32 -a X64 -p UefiPayloadPkg\UefiPayloadPkgIa32X64.dsc -b DEBUG -t <ToolChain> -D BOOTLOADER=<Bootloader>\r
+\r
+ For release X64 build:\r
+ build -a IA32 -a X64 -p UefiPayloadPkg\UefiPayloadPkgIa32X64.dsc -b RELEASE -t <ToolChain> -D BOOTLOADER=<Bootloader>\r
+\r
+ <ToolChain> is the EDK II build environment on your host. Currently it was tested\r
+ with VS2015x86 toolchain.\r
+ <Bootloader> could be "SBL" for Slim Bootloader and "COREBOOT" for coreboot.\r
+\r
+ Refer to https://github.com/tianocore/tianocore.github.io/wiki/UDK2018-How-to-Build for\r
+ details about EDK II build steps.\r
+\r
+2. If build is successfully, the payload image (UEFIPAYLOAD.fd) will be generated inside the\r
+ folder of Build\UefiPayloadPkg.\r
+\r
+================================================================================\r
+C. HOW TO INTEGRATE INTO COREBOOT\r
+================================================================================\r
+1. Copy the payload image (UEFIPAYLOAD.fd) into the top-level directory of Coreboot source tree.\r
+2. Run "make menuconfig" in linux console to start Coreboot configuration surface.\r
+3. In the Payload section,\r
+ 1) Choose "An ELF executable payload" for the option of "Add a payload".\r
+ 2) Type the path of payload image for the option of "Payload path and filename".\r
+ 3) Select the option of "Use LZMA compression for payloads".\r
+4. If the graphics console is required in UEFI payload, enable framebuffer initialization in coreboot.\r
+ This could be done by enabling native graphics or using VGA BIOS option rom.\r
+5. Build the coreboot firmware image.\r
+\r
+================================================================================\r
+D. HOW TO INTEGRATE INTO SLIM BOOTLOADER\r
+================================================================================\r
+Please refer https://slimbootloader.github.io/how-tos/integrate-multiple-payloads.html for below steps.\r
+1. Copy the payload image (UEFIPAYLOAD.fd) into Slim Bootloader source at PayloadPkg\PayloadBins\UefiPld.fd\r
+2. Update config data to make UEFI payload as default payload if required.\r
+3. Build Slim Bootloader with UEFI payload:\r
+ BuildLoader.py build <Platform> -p "OsLoader.efi:LLDR:Lz4;UefiPld.fd:UEFI:Lzma"\r
--- /dev/null
+/** @file\r
+ UEFI Component Name(2) protocol implementation for the generic GOP driver.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/UefiLib.h>\r
+\r
+extern EFI_COMPONENT_NAME_PROTOCOL mGraphicsOutputComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL mGraphicsOutputComponentName2;\r
+\r
+//\r
+// Driver name table for GraphicsOutput module.\r
+// It is shared by the implementation of ComponentName & ComponentName2 Protocol.\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mGraphicsOutputDriverNameTable[] = {\r
+ {\r
+ "eng;en",\r
+ L"Generic Graphics Output Driver"\r
+ },\r
+ {\r
+ NULL,\r
+ NULL\r
+ }\r
+};\r
+\r
+/**\r
+ Retrieves a Unicode string that is the user readable name of the driver.\r
+\r
+ This function retrieves the user readable name of a driver in the form of a\r
+ Unicode string. If the driver specified by This has a user readable name in\r
+ the language specified by Language, then a pointer to the driver name is\r
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified\r
+ by This does not support the language specified by Language,\r
+ then EFI_UNSUPPORTED is returned.\r
+\r
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+ EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+ @param Language[in] A pointer to a Null-terminated ASCII string\r
+ array indicating the language. This is the\r
+ language of the driver name that the caller is\r
+ requesting, and it must match one of the\r
+ languages specified in SupportedLanguages. The\r
+ number of languages supported by a driver is up\r
+ to the driver writer. Language is specified\r
+ in RFC 4646 or ISO 639-2 language code format.\r
+\r
+ @param DriverName[out] A pointer to the Unicode string to return.\r
+ This Unicode string is the name of the\r
+ driver specified by This in the language\r
+ specified by Language.\r
+\r
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by\r
+ This and the language specified by Language was\r
+ returned in DriverName.\r
+\r
+ @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.\r
+\r
+ @retval EFI_UNSUPPORTED The driver specified by This does not support\r
+ the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputComponentNameGetDriverName (\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **DriverName\r
+ )\r
+{\r
+ return LookupUnicodeString2 (\r
+ Language,\r
+ This->SupportedLanguages,\r
+ mGraphicsOutputDriverNameTable,\r
+ DriverName,\r
+ (BOOLEAN) (This == &mGraphicsOutputComponentName)\r
+ );\r
+}\r
+\r
+/**\r
+ Retrieves a Unicode string that is the user readable name of the controller\r
+ that is being managed by a driver.\r
+\r
+ This function retrieves the user readable name of the controller specified by\r
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+ driver specified by This has a user readable name in the language specified by\r
+ Language, then a pointer to the controller name is returned in ControllerName,\r
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently\r
+ managing the controller specified by ControllerHandle and ChildHandle,\r
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not\r
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+ EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+ @param ControllerHandle[in] The handle of a controller that the driver\r
+ specified by This is managing. This handle\r
+ specifies the controller whose name is to be\r
+ returned.\r
+\r
+ @param ChildHandle[in] The handle of the child controller to retrieve\r
+ the name of. This is an optional parameter that\r
+ may be NULL. It will be NULL for device\r
+ drivers. It will also be NULL for a bus drivers\r
+ that wish to retrieve the name of the bus\r
+ controller. It will not be NULL for a bus\r
+ driver that wishes to retrieve the name of a\r
+ child controller.\r
+\r
+ @param Language[in] A pointer to a Null-terminated ASCII string\r
+ array indicating the language. This is the\r
+ language of the driver name that the caller is\r
+ requesting, and it must match one of the\r
+ languages specified in SupportedLanguages. The\r
+ number of languages supported by a driver is up\r
+ to the driver writer. Language is specified in\r
+ RFC 4646 or ISO 639-2 language code format.\r
+\r
+ @param ControllerName[out] A pointer to the Unicode string to return.\r
+ This Unicode string is the name of the\r
+ controller specified by ControllerHandle and\r
+ ChildHandle in the language specified by\r
+ Language from the point of view of the driver\r
+ specified by This.\r
+\r
+ @retval EFI_SUCCESS The Unicode string for the user readable name in\r
+ the language specified by Language for the\r
+ driver specified by This was returned in\r
+ DriverName.\r
+\r
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+ EFI_HANDLE.\r
+\r
+ @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently\r
+ managing the controller specified by\r
+ ControllerHandle and ChildHandle.\r
+\r
+ @retval EFI_UNSUPPORTED The driver specified by This does not support\r
+ the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputComponentNameGetControllerName (\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN EFI_HANDLE ChildHandle OPTIONAL,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **ControllerName\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+//\r
+// EFI Component Name Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL mGraphicsOutputComponentName = {\r
+ GraphicsOutputComponentNameGetDriverName,\r
+ GraphicsOutputComponentNameGetControllerName,\r
+ "eng"\r
+};\r
+\r
+//\r
+// EFI Component Name 2 Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL mGraphicsOutputComponentName2 = {\r
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) GraphicsOutputComponentNameGetDriverName,\r
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) GraphicsOutputComponentNameGetControllerName,\r
+ "en"\r
+};\r
--- /dev/null
+/** @file\r
+ Implementation for a generic GOP driver.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+\r
+**/\r
+\r
+#include "GraphicsOutput.h"\r
+CONST ACPI_ADR_DEVICE_PATH mGraphicsOutputAdrNode = {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_ADR_DP,\r
+ { sizeof (ACPI_ADR_DEVICE_PATH), 0 },\r
+ },\r
+ ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, 0, 0)\r
+};\r
+\r
+EFI_PEI_GRAPHICS_DEVICE_INFO_HOB mDefaultGraphicsDeviceInfo = {\r
+ MAX_UINT16, MAX_UINT16, MAX_UINT16, MAX_UINT16, MAX_UINT8, MAX_UINT8\r
+};\r
+\r
+//\r
+// The driver should only start on one graphics controller.\r
+// So a global flag is used to remember that the driver is already started.\r
+//\r
+BOOLEAN mDriverStarted = FALSE;\r
+\r
+/**\r
+ Returns information for an available graphics mode that the graphics device\r
+ and the set of active video output devices supports.\r
+\r
+ @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.\r
+ @param ModeNumber The mode number to return information on.\r
+ @param SizeOfInfo A pointer to the size, in bytes, of the Info buffer.\r
+ @param Info A pointer to callee allocated buffer that returns information about ModeNumber.\r
+\r
+ @retval EFI_SUCCESS Valid mode information was returned.\r
+ @retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the video mode.\r
+ @retval EFI_INVALID_PARAMETER ModeNumber is not valid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputQueryMode (\r
+ IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,\r
+ IN UINT32 ModeNumber,\r
+ OUT UINTN *SizeOfInfo,\r
+ OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info\r
+ )\r
+{\r
+ if (This == NULL || Info == NULL || SizeOfInfo == NULL || ModeNumber >= This->Mode->MaxMode) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ *SizeOfInfo = This->Mode->SizeOfInfo;\r
+ *Info = AllocateCopyPool (*SizeOfInfo, This->Mode->Info);\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Set the video device into the specified mode and clears the visible portions of\r
+ the output display to black.\r
+\r
+ @param This The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.\r
+ @param ModeNumber Abstraction that defines the current video mode.\r
+\r
+ @retval EFI_SUCCESS The graphics mode specified by ModeNumber was selected.\r
+ @retval EFI_DEVICE_ERROR The device had an error and could not complete the request.\r
+ @retval EFI_UNSUPPORTED ModeNumber is not supported by this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputSetMode (\r
+ IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,\r
+ IN UINT32 ModeNumber\r
+)\r
+{\r
+ RETURN_STATUS Status;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;\r
+ GRAPHICS_OUTPUT_PRIVATE_DATA *Private;\r
+\r
+ if (ModeNumber >= This->Mode->MaxMode) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ Private = GRAPHICS_OUTPUT_PRIVATE_FROM_THIS (This);\r
+\r
+ Black.Blue = 0;\r
+ Black.Green = 0;\r
+ Black.Red = 0;\r
+ Black.Reserved = 0;\r
+\r
+ Status = FrameBufferBlt (\r
+ Private->FrameBufferBltLibConfigure,\r
+ &Black,\r
+ EfiBltVideoFill,\r
+ 0, 0,\r
+ 0, 0,\r
+ This->Mode->Info->HorizontalResolution,\r
+ This->Mode->Info->VerticalResolution,\r
+ 0\r
+ );\r
+ return RETURN_ERROR (Status) ? EFI_DEVICE_ERROR : EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Blt a rectangle of pixels on the graphics screen. Blt stands for BLock Transfer.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param BltBuffer The data to transfer to the graphics screen.\r
+ Size is at least Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL).\r
+ @param BltOperation The operation to perform when copying BltBuffer on to the graphics screen.\r
+ @param SourceX The X coordinate of source for the BltOperation.\r
+ @param SourceY The Y coordinate of source for the BltOperation.\r
+ @param DestinationX The X coordinate of destination for the BltOperation.\r
+ @param DestinationY The Y coordinate of destination for the BltOperation.\r
+ @param Width The width of a rectangle in the blt rectangle in pixels.\r
+ @param Height The height of a rectangle in the blt rectangle in pixels.\r
+ @param Delta Not used for EfiBltVideoFill or the EfiBltVideoToVideo operation.\r
+ If a Delta of zero is used, the entire BltBuffer is being operated on.\r
+ If a subrectangle of the BltBuffer is being used then Delta\r
+ represents the number of bytes in a row of the BltBuffer.\r
+\r
+ @retval EFI_SUCCESS BltBuffer was drawn to the graphics screen.\r
+ @retval EFI_INVALID_PARAMETER BltOperation is not valid.\r
+ @retval EFI_DEVICE_ERROR The device had an error and could not complete the request.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputBlt (\r
+ IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,\r
+ IN UINTN SourceX,\r
+ IN UINTN SourceY,\r
+ IN UINTN DestinationX,\r
+ IN UINTN DestinationY,\r
+ IN UINTN Width,\r
+ IN UINTN Height,\r
+ IN UINTN Delta OPTIONAL\r
+ )\r
+{\r
+ RETURN_STATUS Status;\r
+ EFI_TPL Tpl;\r
+ GRAPHICS_OUTPUT_PRIVATE_DATA *Private;\r
+\r
+ Private = GRAPHICS_OUTPUT_PRIVATE_FROM_THIS (This);\r
+ //\r
+ // We have to raise to TPL_NOTIFY, so we make an atomic write to the frame buffer.\r
+ // We would not want a timer based event (Cursor, ...) to come in while we are\r
+ // doing this operation.\r
+ //\r
+ Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
+ Status = FrameBufferBlt (\r
+ Private->FrameBufferBltLibConfigure,\r
+ BltBuffer,\r
+ BltOperation,\r
+ SourceX, SourceY,\r
+ DestinationX, DestinationY, Width, Height,\r
+ Delta\r
+ );\r
+ gBS->RestoreTPL (Tpl);\r
+\r
+ return RETURN_ERROR (Status) ? EFI_INVALID_PARAMETER : EFI_SUCCESS;\r
+}\r
+\r
+CONST GRAPHICS_OUTPUT_PRIVATE_DATA mGraphicsOutputInstanceTemplate = {\r
+ GRAPHICS_OUTPUT_PRIVATE_DATA_SIGNATURE, // Signature\r
+ NULL, // GraphicsOutputHandle\r
+ {\r
+ GraphicsOutputQueryMode,\r
+ GraphicsOutputSetMode,\r
+ GraphicsOutputBlt,\r
+ NULL // Mode\r
+ },\r
+ {\r
+ 1, // MaxMode\r
+ 0, // Mode\r
+ NULL, // Info\r
+ sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), // SizeOfInfo\r
+ 0, // FrameBufferBase\r
+ 0 // FrameBufferSize\r
+ },\r
+ NULL, // DevicePath\r
+ NULL, // PciIo\r
+ 0, // PciAttributes\r
+ NULL, // FrameBufferBltLibConfigure\r
+ 0 // FrameBufferBltLibConfigureSize\r
+};\r
+\r
+/**\r
+ Test whether the Controller can be managed by the driver.\r
+\r
+ @param This Driver Binding protocol instance pointer.\r
+ @param Controller The PCI controller.\r
+ @param RemainingDevicePath Optional parameter use to pick a specific child\r
+ device to start.\r
+\r
+ @retval EFI_SUCCESS The driver can manage the video device.\r
+ @retval other The driver cannot manage the video device.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputDriverBindingSupported (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ //\r
+ // Since there is only one GraphicsInfo HOB, the driver only manages one video device.\r
+ //\r
+ if (mDriverStarted) {\r
+ return EFI_ALREADY_STARTED;\r
+ }\r
+\r
+ //\r
+ // Test the PCI I/O Protocol\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIo,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+ if (Status == EFI_ALREADY_STARTED) {\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ //\r
+ // Test the DevicePath protocol\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &DevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+ if (Status == EFI_ALREADY_STARTED) {\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ if ((RemainingDevicePath == NULL) ||\r
+ IsDevicePathEnd (RemainingDevicePath) ||\r
+ CompareMem (RemainingDevicePath, &mGraphicsOutputAdrNode, sizeof (mGraphicsOutputAdrNode)) == 0) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+}\r
+\r
+/**\r
+ Start the video controller.\r
+\r
+ @param This Driver Binding protocol instance pointer.\r
+ @param ControllerHandle The PCI controller.\r
+ @param RemainingDevicePath Optional parameter use to pick a specific child\r
+ device to start.\r
+\r
+ @retval EFI_SUCCESS The driver starts to manage the video device.\r
+ @retval other The driver cannot manage the video device.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputDriverBindingStart (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ RETURN_STATUS ReturnStatus;\r
+ GRAPHICS_OUTPUT_PRIVATE_DATA *Private;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ EFI_DEVICE_PATH *PciDevicePath;\r
+ PCI_TYPE00 Pci;\r
+ UINT8 Index;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Resources;\r
+ VOID *HobStart;\r
+ EFI_PEI_GRAPHICS_INFO_HOB *GraphicsInfo;\r
+ EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *DeviceInfo;\r
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;\r
+\r
+ FrameBufferBase = 0;\r
+\r
+ HobStart = GetFirstGuidHob (&gEfiGraphicsInfoHobGuid);\r
+ ASSERT ((HobStart != NULL) && (GET_GUID_HOB_DATA_SIZE (HobStart) == sizeof (EFI_PEI_GRAPHICS_INFO_HOB)));\r
+ GraphicsInfo = (EFI_PEI_GRAPHICS_INFO_HOB *) (GET_GUID_HOB_DATA (HobStart));\r
+\r
+ HobStart = GetFirstGuidHob (&gEfiGraphicsDeviceInfoHobGuid);\r
+ if ((HobStart == NULL) || (GET_GUID_HOB_DATA_SIZE (HobStart) < sizeof (*DeviceInfo))) {\r
+ //\r
+ // Use default device infomation when the device info HOB doesn't exist\r
+ //\r
+ DeviceInfo = &mDefaultGraphicsDeviceInfo;\r
+ DEBUG ((DEBUG_INFO, "[%a]: GraphicsDeviceInfo HOB doesn't exist!\n", gEfiCallerBaseName));\r
+ } else {\r
+ DeviceInfo = (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *) (GET_GUID_HOB_DATA (HobStart));\r
+ DEBUG ((DEBUG_INFO, "[%a]: GraphicsDeviceInfo HOB:\n"\r
+ " VendorId = %04x, DeviceId = %04x,\n"\r
+ " RevisionId = %02x, BarIndex = %x,\n"\r
+ " SubsystemVendorId = %04x, SubsystemId = %04x\n",\r
+ gEfiCallerBaseName,\r
+ DeviceInfo->VendorId, DeviceInfo->DeviceId,\r
+ DeviceInfo->RevisionId, DeviceInfo->BarIndex,\r
+ DeviceInfo->SubsystemVendorId, DeviceInfo->SubsystemId));\r
+ }\r
+\r
+ //\r
+ // Open the PCI I/O Protocol\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIo,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+ if (Status == EFI_ALREADY_STARTED) {\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &PciDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+ if (Status == EFI_ALREADY_STARTED) {\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Read the PCI Class Code from the PCI Device\r
+ //\r
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0, sizeof (Pci), &Pci);\r
+ if (!EFI_ERROR (Status)) {\r
+ if (!IS_PCI_DISPLAY (&Pci) || (\r
+ ((DeviceInfo->VendorId != MAX_UINT16) && (DeviceInfo->VendorId != Pci.Hdr.VendorId)) ||\r
+ ((DeviceInfo->DeviceId != MAX_UINT16) && (DeviceInfo->DeviceId != Pci.Hdr.DeviceId)) ||\r
+ ((DeviceInfo->RevisionId != MAX_UINT8) && (DeviceInfo->RevisionId != Pci.Hdr.RevisionID)) ||\r
+ ((DeviceInfo->SubsystemVendorId != MAX_UINT16) && (DeviceInfo->SubsystemVendorId != Pci.Device.SubsystemVendorID)) ||\r
+ ((DeviceInfo->SubsystemId != MAX_UINT16) && (DeviceInfo->SubsystemId != Pci.Device.SubsystemID))\r
+ )\r
+ ) {\r
+ //\r
+ // It's not a video device, or device infomation doesn't match.\r
+ //\r
+ Status = EFI_UNSUPPORTED;\r
+ } else {\r
+ //\r
+ // If it's a video device and device information matches, use the BarIndex\r
+ // from device information, or any BAR if BarIndex is not specified\r
+ // whose size >= the frame buffer size from GraphicsInfo HOB.\r
+ // Store the new frame buffer base.\r
+ //\r
+ for (Index = 0; Index < MAX_PCI_BAR; Index++) {\r
+ if ((DeviceInfo->BarIndex != MAX_UINT8) && (DeviceInfo->BarIndex != Index)) {\r
+ continue;\r
+ }\r
+ Status = PciIo->GetBarAttributes (PciIo, Index, NULL, (VOID**) &Resources);\r
+ if (!EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_INFO, "[%a]: BAR[%d]: Base = %lx, Length = %lx\n",\r
+ gEfiCallerBaseName, Index, Resources->AddrRangeMin, Resources->AddrLen));\r
+ if ((Resources->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) &&\r
+ (Resources->Len == (UINT16) (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3)) &&\r
+ (Resources->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) &&\r
+ (Resources->AddrLen >= GraphicsInfo->FrameBufferSize)\r
+ ) {\r
+ if (FrameBufferBase == 0) {\r
+ FrameBufferBase = Resources->AddrRangeMin;\r
+ }\r
+ if (DeviceInfo->BarIndex == MAX_UINT8) {\r
+ if (Resources->AddrRangeMin == GraphicsInfo->FrameBufferBase) {\r
+ FrameBufferBase = Resources->AddrRangeMin;\r
+ break;\r
+ }\r
+ } else {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ if (Index == MAX_PCI_BAR) {\r
+ Status = EFI_UNSUPPORTED;\r
+ } else {\r
+ DEBUG ((DEBUG_INFO, "[%a]: ... matched!\n", gEfiCallerBaseName));\r
+ }\r
+ }\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto CloseProtocols;\r
+ }\r
+\r
+ if ((RemainingDevicePath != NULL) && IsDevicePathEnd (RemainingDevicePath)) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ Private = AllocateCopyPool (sizeof (mGraphicsOutputInstanceTemplate), &mGraphicsOutputInstanceTemplate);\r
+ if (Private == NULL) {\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto CloseProtocols;\r
+ }\r
+\r
+ Private->GraphicsOutputMode.FrameBufferBase = FrameBufferBase;\r
+ Private->GraphicsOutputMode.FrameBufferSize = GraphicsInfo->FrameBufferSize;\r
+ Private->GraphicsOutputMode.Info = &GraphicsInfo->GraphicsMode;\r
+\r
+ //\r
+ // Fix up Mode pointer in GraphicsOutput\r
+ //\r
+ Private->GraphicsOutput.Mode = &Private->GraphicsOutputMode;\r
+\r
+ //\r
+ // Set attributes\r
+ //\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationGet,\r
+ 0,\r
+ &Private->PciAttributes\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ EFI_PCI_DEVICE_ENABLE,\r
+ NULL\r
+ );\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto FreeMemory;\r
+ }\r
+\r
+ //\r
+ // Create the FrameBufferBltLib configuration.\r
+ //\r
+ ReturnStatus = FrameBufferBltConfigure (\r
+ (VOID *) (UINTN) Private->GraphicsOutput.Mode->FrameBufferBase,\r
+ Private->GraphicsOutput.Mode->Info,\r
+ Private->FrameBufferBltLibConfigure,\r
+ &Private->FrameBufferBltLibConfigureSize\r
+ );\r
+ if (ReturnStatus == RETURN_BUFFER_TOO_SMALL) {\r
+ Private->FrameBufferBltLibConfigure = AllocatePool (Private->FrameBufferBltLibConfigureSize);\r
+ if (Private->FrameBufferBltLibConfigure != NULL) {\r
+ ReturnStatus = FrameBufferBltConfigure (\r
+ (VOID *) (UINTN) Private->GraphicsOutput.Mode->FrameBufferBase,\r
+ Private->GraphicsOutput.Mode->Info,\r
+ Private->FrameBufferBltLibConfigure,\r
+ &Private->FrameBufferBltLibConfigureSize\r
+ );\r
+ }\r
+ }\r
+ if (RETURN_ERROR (ReturnStatus)) {\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto RestorePciAttributes;\r
+ }\r
+\r
+ Private->DevicePath = AppendDevicePathNode (PciDevicePath, (EFI_DEVICE_PATH_PROTOCOL *) &mGraphicsOutputAdrNode);\r
+ if (Private->DevicePath == NULL) {\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto RestorePciAttributes;\r
+ }\r
+\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &Private->GraphicsOutputHandle,\r
+ &gEfiGraphicsOutputProtocolGuid, &Private->GraphicsOutput,\r
+ &gEfiDevicePathProtocolGuid, Private->DevicePath,\r
+ NULL\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &Private->PciIo,\r
+ This->DriverBindingHandle,\r
+ Private->GraphicsOutputHandle,\r
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ mDriverStarted = TRUE;\r
+ } else {\r
+ gBS->UninstallMultipleProtocolInterfaces (\r
+ Private->GraphicsOutputHandle,\r
+ &gEfiGraphicsOutputProtocolGuid, &Private->GraphicsOutput,\r
+ &gEfiDevicePathProtocolGuid, Private->DevicePath,\r
+ NULL\r
+ );\r
+ }\r
+ }\r
+\r
+RestorePciAttributes:\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ Private->PciAttributes,\r
+ NULL\r
+ );\r
+ }\r
+\r
+FreeMemory:\r
+ if (EFI_ERROR (Status)) {\r
+ if (Private != NULL) {\r
+ if (Private->DevicePath != NULL) {\r
+ FreePool (Private->DevicePath);\r
+ }\r
+ if (Private->FrameBufferBltLibConfigure != NULL) {\r
+ FreePool (Private->FrameBufferBltLibConfigure);\r
+ }\r
+ FreePool (Private);\r
+ }\r
+ }\r
+\r
+CloseProtocols:\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Close the PCI I/O Protocol\r
+ //\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ //\r
+ // Close the PCI I/O Protocol\r
+ //\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+ }\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Stop the video controller.\r
+\r
+ @param This Driver Binding protocol instance pointer.\r
+ @param Controller The PCI controller.\r
+ @param NumberOfChildren The number of child device handles in ChildHandleBuffer.\r
+ @param ChildHandleBuffer An array of child handles to be freed. May be NULL\r
+ if NumberOfChildren is 0.\r
+\r
+ @retval EFI_SUCCESS The device was stopped.\r
+ @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GraphicsOutputDriverBindingStop (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop;\r
+ GRAPHICS_OUTPUT_PRIVATE_DATA *Private;\r
+\r
+ if (NumberOfChildren == 0) {\r
+\r
+ //\r
+ // Close the PCI I/O Protocol\r
+ //\r
+ Status = gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ ASSERT (NumberOfChildren == 1);\r
+ Status = gBS->OpenProtocol (\r
+ ChildHandleBuffer[0],\r
+ &gEfiGraphicsOutputProtocolGuid,\r
+ (VOID **) &Gop,\r
+ This->DriverBindingHandle,\r
+ ChildHandleBuffer[0],\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Private = GRAPHICS_OUTPUT_PRIVATE_FROM_THIS (Gop);\r
+\r
+ Status = gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Private->GraphicsOutputHandle\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Remove the GOP protocol interface from the system\r
+ //\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ Private->GraphicsOutputHandle,\r
+ &gEfiGraphicsOutputProtocolGuid, &Private->GraphicsOutput,\r
+ &gEfiDevicePathProtocolGuid, Private->DevicePath,\r
+ NULL\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ Status = Private->PciIo->Attributes (\r
+ Private->PciIo,\r
+ EfiPciIoAttributeOperationSet,\r
+ Private->PciAttributes,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ FreePool (Private->DevicePath);\r
+ FreePool (Private->FrameBufferBltLibConfigure);\r
+ mDriverStarted = FALSE;\r
+ } else {\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &Private->PciIo,\r
+ This->DriverBindingHandle,\r
+ Private->GraphicsOutputHandle,\r
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ return Status;\r
+}\r
+\r
+EFI_DRIVER_BINDING_PROTOCOL mGraphicsOutputDriverBinding = {\r
+ GraphicsOutputDriverBindingSupported,\r
+ GraphicsOutputDriverBindingStart,\r
+ GraphicsOutputDriverBindingStop,\r
+ 0x10,\r
+ NULL,\r
+ NULL\r
+};\r
+\r
+/**\r
+ The Entry Point for GraphicsOutput driver.\r
+\r
+ It installs DriverBinding, ComponentName and ComponentName2 protocol if there is\r
+ GraphicsInfo HOB passed from Graphics PEIM.\r
+\r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
+ @param[in] SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS The entry point is executed successfully.\r
+ @retval other Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeGraphicsOutput (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *HobStart;\r
+\r
+ HobStart = GetFirstGuidHob (&gEfiGraphicsInfoHobGuid);\r
+\r
+ if ((HobStart == NULL) || (GET_GUID_HOB_DATA_SIZE (HobStart) < sizeof (EFI_PEI_GRAPHICS_INFO_HOB))) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ Status = EfiLibInstallDriverBindingComponentName2 (\r
+ ImageHandle,\r
+ SystemTable,\r
+ &mGraphicsOutputDriverBinding,\r
+ ImageHandle,\r
+ &mGraphicsOutputComponentName,\r
+ &mGraphicsOutputComponentName2\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+ Header file for a generic GOP driver.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+\r
+**/\r
+#ifndef _GRAPHICS_OUTPUT_DXE_H_\r
+#define _GRAPHICS_OUTPUT_DXE_H_\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <Guid/GraphicsInfoHob.h>\r
+#include <Protocol/DriverBinding.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/GraphicsOutput.h>\r
+#include <Protocol/ComponentName.h>\r
+#include <Protocol/ComponentName2.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/FrameBufferBltLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiLib.h>\r
+\r
+#define MAX_PCI_BAR 6\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_HANDLE GraphicsOutputHandle;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL GraphicsOutput;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE GraphicsOutputMode;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINT64 PciAttributes;\r
+ FRAME_BUFFER_CONFIGURE *FrameBufferBltLibConfigure;\r
+ UINTN FrameBufferBltLibConfigureSize;\r
+} GRAPHICS_OUTPUT_PRIVATE_DATA;\r
+\r
+#define GRAPHICS_OUTPUT_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('g', 'g', 'o', 'p')\r
+#define GRAPHICS_OUTPUT_PRIVATE_FROM_THIS(a) \\r
+ CR(a, GRAPHICS_OUTPUT_PRIVATE_DATA, GraphicsOutput, GRAPHICS_OUTPUT_PRIVATE_DATA_SIGNATURE)\r
+\r
+extern EFI_COMPONENT_NAME_PROTOCOL mGraphicsOutputComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL mGraphicsOutputComponentName2;\r
+#endif\r
--- /dev/null
+## @file\r
+# This driver produces GraphicsOutput protocol based on the GraphicsInfo HOB information.\r
+#\r
+# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = GraphicsOutputDxe\r
+ FILE_GUID = 0B04B2ED-861C-42cd-A22F-C3AAFACCB896\r
+ MODULE_TYPE = UEFI_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = InitializeGraphicsOutput\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources.common]\r
+ GraphicsOutput.h\r
+ GraphicsOutput.c\r
+ ComponentName.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ DxeServicesTableLib\r
+ DebugLib\r
+ MemoryAllocationLib\r
+ BaseMemoryLib\r
+ DevicePathLib\r
+ FrameBufferBltLib\r
+ UefiLib\r
+ HobLib\r
+\r
+[Guids]\r
+ gEfiGraphicsInfoHobGuid ## CONSUMES ## HOB\r
+ gEfiGraphicsDeviceInfoHobGuid ## CONSUMES ## HOB\r
+\r
+[Protocols]\r
+ gEfiGraphicsOutputProtocolGuid ## BY_START\r
+ gEfiDevicePathProtocolGuid ## BY_START\r
+ gEfiPciIoProtocolGuid ## TO_START\r
--- /dev/null
+/** @file\r
+ Coreboot PEI module include file.\r
+\r
+ Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+/*\r
+ * This file is part of the libpayload project.\r
+ *\r
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _COREBOOT_PEI_H_INCLUDED_\r
+#define _COREBOOT_PEI_H_INCLUDED_\r
+\r
+#if defined(_MSC_VER)\r
+#pragma warning( disable : 4200 )\r
+#endif\r
+\r
+#define DYN_CBMEM_ALIGN_SIZE (4096)\r
+\r
+#define IMD_ENTRY_MAGIC (~0xC0389481)\r
+#define CBMEM_ENTRY_MAGIC (~0xC0389479)\r
+\r
+struct cbmem_entry {\r
+ UINT32 magic;\r
+ UINT32 start;\r
+ UINT32 size;\r
+ UINT32 id;\r
+};\r
+\r
+struct cbmem_root {\r
+ UINT32 max_entries;\r
+ UINT32 num_entries;\r
+ UINT32 locked;\r
+ UINT32 size;\r
+ struct cbmem_entry entries[0];\r
+};\r
+\r
+struct imd_entry {\r
+ UINT32 magic;\r
+ UINT32 start_offset;\r
+ UINT32 size;\r
+ UINT32 id;\r
+};\r
+\r
+struct imd_root {\r
+ UINT32 max_entries;\r
+ UINT32 num_entries;\r
+ UINT32 flags;\r
+ UINT32 entry_align;\r
+ UINT32 max_offset;\r
+ struct imd_entry entries[0];\r
+};\r
+\r
+struct cbuint64 {\r
+ UINT32 lo;\r
+ UINT32 hi;\r
+};\r
+\r
+#define CB_HEADER_SIGNATURE 0x4F49424C\r
+\r
+struct cb_header {\r
+ UINT32 signature;\r
+ UINT32 header_bytes;\r
+ UINT32 header_checksum;\r
+ UINT32 table_bytes;\r
+ UINT32 table_checksum;\r
+ UINT32 table_entries;\r
+};\r
+\r
+struct cb_record {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+};\r
+\r
+#define CB_TAG_UNUSED 0x0000\r
+#define CB_TAG_MEMORY 0x0001\r
+\r
+struct cb_memory_range {\r
+ struct cbuint64 start;\r
+ struct cbuint64 size;\r
+ UINT32 type;\r
+};\r
+\r
+#define CB_MEM_RAM 1\r
+#define CB_MEM_RESERVED 2\r
+#define CB_MEM_ACPI 3\r
+#define CB_MEM_NVS 4\r
+#define CB_MEM_UNUSABLE 5\r
+#define CB_MEM_VENDOR_RSVD 6\r
+#define CB_MEM_TABLE 16\r
+\r
+struct cb_memory {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+ struct cb_memory_range map[0];\r
+};\r
+\r
+#define CB_TAG_MAINBOARD 0x0003\r
+\r
+struct cb_mainboard {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+ UINT8 vendor_idx;\r
+ UINT8 part_number_idx;\r
+ UINT8 strings[0];\r
+};\r
+#define CB_TAG_VERSION 0x0004\r
+#define CB_TAG_EXTRA_VERSION 0x0005\r
+#define CB_TAG_BUILD 0x0006\r
+#define CB_TAG_COMPILE_TIME 0x0007\r
+#define CB_TAG_COMPILE_BY 0x0008\r
+#define CB_TAG_COMPILE_HOST 0x0009\r
+#define CB_TAG_COMPILE_DOMAIN 0x000a\r
+#define CB_TAG_COMPILER 0x000b\r
+#define CB_TAG_LINKER 0x000c\r
+#define CB_TAG_ASSEMBLER 0x000d\r
+\r
+struct cb_string {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+ UINT8 string[0];\r
+};\r
+\r
+#define CB_TAG_SERIAL 0x000f\r
+\r
+struct cb_serial {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+#define CB_SERIAL_TYPE_IO_MAPPED 1\r
+#define CB_SERIAL_TYPE_MEMORY_MAPPED 2\r
+ UINT32 type;\r
+ UINT32 baseaddr;\r
+ UINT32 baud;\r
+ UINT32 regwidth;\r
+\r
+ // Crystal or input frequency to the chip containing the UART.\r
+ // Provide the board specific details to allow the payload to\r
+ // initialize the chip containing the UART and make independent\r
+ // decisions as to which dividers to select and their values\r
+ // to eventually arrive at the desired console baud-rate.\r
+ UINT32 input_hertz;\r
+\r
+ // UART PCI address: bus, device, function\r
+ // 1 << 31 - Valid bit, PCI UART in use\r
+ // Bus << 20\r
+ // Device << 15\r
+ // Function << 12\r
+ UINT32 uart_pci_addr;\r
+};\r
+\r
+#define CB_TAG_CONSOLE 0x00010\r
+\r
+struct cb_console {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+ UINT16 type;\r
+};\r
+\r
+#define CB_TAG_CONSOLE_SERIAL8250 0\r
+#define CB_TAG_CONSOLE_VGA 1 // OBSOLETE\r
+#define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE\r
+#define CB_TAG_CONSOLE_LOGBUF 3\r
+#define CB_TAG_CONSOLE_SROM 4 // OBSOLETE\r
+#define CB_TAG_CONSOLE_EHCI 5\r
+\r
+#define CB_TAG_FORWARD 0x00011\r
+\r
+struct cb_forward {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+ UINT64 forward;\r
+};\r
+\r
+#define CB_TAG_FRAMEBUFFER 0x0012\r
+struct cb_framebuffer {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+\r
+ UINT64 physical_address;\r
+ UINT32 x_resolution;\r
+ UINT32 y_resolution;\r
+ UINT32 bytes_per_line;\r
+ UINT8 bits_per_pixel;\r
+ UINT8 red_mask_pos;\r
+ UINT8 red_mask_size;\r
+ UINT8 green_mask_pos;\r
+ UINT8 green_mask_size;\r
+ UINT8 blue_mask_pos;\r
+ UINT8 blue_mask_size;\r
+ UINT8 reserved_mask_pos;\r
+ UINT8 reserved_mask_size;\r
+};\r
+\r
+#define CB_TAG_VDAT 0x0015\r
+struct cb_vdat {\r
+ UINT32 tag;\r
+ UINT32 size; /* size of the entire entry */\r
+ UINT64 vdat_addr;\r
+ UINT32 vdat_size;\r
+};\r
+\r
+#define CB_TAG_TIMESTAMPS 0x0016\r
+#define CB_TAG_CBMEM_CONSOLE 0x0017\r
+#define CB_TAG_MRC_CACHE 0x0018\r
+struct cb_cbmem_tab {\r
+ UINT32 tag;\r
+ UINT32 size;\r
+ UINT64 cbmem_tab;\r
+};\r
+\r
+/* Helpful macros */\r
+\r
+#define MEM_RANGE_COUNT(_rec) \\r
+ (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))\r
+\r
+#define MEM_RANGE_PTR(_rec, _idx) \\r
+ (void *)(((UINT8 *) (_rec)) + sizeof(*(_rec)) \\r
+ + (sizeof((_rec)->map[0]) * (_idx)))\r
+\r
+\r
+#endif // _COREBOOT_PEI_H_INCLUDED_\r
--- /dev/null
+/** @file\r
+ This file defines the hob structure for board related information from acpi table\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __ACPI_BOARD_INFO_GUID_H__\r
+#define __ACPI_BOARD_INFO_GUID_H__\r
+\r
+///\r
+/// Board information GUID\r
+///\r
+extern EFI_GUID gUefiAcpiBoardInfoGuid;\r
+\r
+typedef struct {\r
+ UINT8 Revision;\r
+ UINT8 Reserved0[2];\r
+ UINT8 ResetValue;\r
+ UINT64 PmEvtBase;\r
+ UINT64 PmGpeEnBase;\r
+ UINT64 PmCtrlRegBase;\r
+ UINT64 PmTimerRegBase;\r
+ UINT64 ResetRegAddress;\r
+ UINT64 PcieBaseAddress;\r
+} ACPI_BOARD_INFO;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file defines the hob structure for memory map information.\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __MEMORY_MAP_INFO_GUID_H__\r
+#define __MEMORY_MAP_INFO_GUID_H__\r
+\r
+#include <Library/PcdLib.h>\r
+\r
+///\r
+/// Memory Map Information GUID\r
+///\r
+extern EFI_GUID gLoaderMemoryMapInfoGuid;\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT64 Base;\r
+ UINT64 Size;\r
+ UINT8 Type;\r
+ UINT8 Flag;\r
+ UINT8 Reserved[6];\r
+} MEMROY_MAP_ENTRY;\r
+\r
+typedef struct {\r
+ UINT8 Revision;\r
+ UINT8 Reserved0[3];\r
+ UINT32 Count;\r
+ MEMROY_MAP_ENTRY Entry[0];\r
+} MEMROY_MAP_INFO;\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file defines the hob structure for serial port.\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __SERIAL_PORT_INFO_GUID_H__\r
+#define __SERIAL_PORT_INFO_GUID_H__\r
+\r
+///\r
+/// Serial Port Information GUID\r
+///\r
+extern EFI_GUID gUefiSerialPortInfoGuid;\r
+\r
+#define PLD_SERIAL_TYPE_IO_MAPPED 1\r
+#define PLD_SERIAL_TYPE_MEMORY_MAPPED 2\r
+\r
+typedef struct {\r
+ UINT8 Revision;\r
+ UINT8 Reserved0[3];\r
+ UINT32 Type;\r
+ UINT32 BaseAddr;\r
+ UINT32 Baud;\r
+ UINT32 RegWidth;\r
+ UINT32 InputHertz;\r
+ UINT32 UartPciAddr;\r
+} SERIAL_PORT_INFO;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This file defines the hob structure for system tables like ACPI, SMBIOS tables.\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __SYSTEM_TABLE_INFO_GUID_H__\r
+#define __SYSTEM_TABLE_INFO_GUID_H__\r
+\r
+///\r
+/// System Table Information GUID\r
+///\r
+extern EFI_GUID gUefiSystemTableInfoGuid;\r
+\r
+typedef struct {\r
+ UINT8 Revision;\r
+ UINT8 Reserved0[3];\r
+ UINT64 AcpiTableBase;\r
+ UINT32 AcpiTableSize;\r
+ UINT64 SmbiosTableBase;\r
+ UINT32 SmbiosTableSize;\r
+} SYSTEM_TABLE_INFO;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ This library will parse the coreboot table in memory and extract those required\r
+ information.\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+#include <PiPei.h>\r
+#include <Guid/GraphicsInfoHob.h>\r
+#include <Guid/MemoryMapInfoGuid.h>\r
+#include <Guid/SerialPortInfoGuid.h>\r
+#include <Guid/SystemTableInfoGuid.h>\r
+#include <Guid/AcpiBoardInfoGuid.h>\r
+\r
+#ifndef __BOOTLOADER_PARSE_LIB__\r
+#define __BOOTLOADER_PARSE_LIB__\r
+\r
+#define GET_BOOTLOADER_PARAMETER() (*(UINT32 *)(UINTN)(PcdGet32(PcdPayloadStackTop) - sizeof(UINT32)))\r
+#define SET_BOOTLOADER_PARAMETER(Value) GET_BOOTLOADER_PARAMETER()=Value\r
+\r
+typedef RETURN_STATUS \\r
+ (*BL_MEM_INFO_CALLBACK) (MEMROY_MAP_ENTRY *MemoryMapEntry, VOID *Param);\r
+\r
+/**\r
+ This function retrieves the parameter base address from boot loader.\r
+\r
+ This function will get bootloader specific parameter address for UEFI payload.\r
+ e.g. HobList pointer for Slim Bootloader, and coreboot table header for Coreboot.\r
+\r
+ @retval NULL Failed to find the GUID HOB.\r
+ @retval others GUIDed HOB data pointer.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetParameterBase (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Acquire the memory map information.\r
+\r
+ @param MemInfoCallback The callback routine\r
+ @param Params Pointer to the callback routine parameter\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the memory information.\r
+ @retval RETURN_NOT_FOUND Failed to find the memory information.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseMemoryInfo (\r
+ IN BL_MEM_INFO_CALLBACK MemInfoCallback,\r
+ IN VOID *Params\r
+ );\r
+\r
+/**\r
+ Acquire acpi table and smbios table from slim bootloader\r
+\r
+ @param SystemTableInfo Pointer to the system table info\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the tables.\r
+ @retval RETURN_NOT_FOUND Failed to find the tables.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseSystemTable (\r
+ OUT SYSTEM_TABLE_INFO *SystemTableInfo\r
+ );\r
+\r
+\r
+/**\r
+ Find the serial port information\r
+\r
+ @param SERIAL_PORT_INFO Pointer to serial port info structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the serial port information.\r
+ @retval RETURN_NOT_FOUND Failed to find the serial port information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseSerialInfo (\r
+ OUT SERIAL_PORT_INFO *SerialPortInfo\r
+ );\r
+\r
+\r
+/**\r
+ Find the video frame buffer information\r
+\r
+ @param GfxInfo Pointer to the EFI_PEI_GRAPHICS_INFO_HOB structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the video frame buffer information.\r
+ @retval RETURN_NOT_FOUND Failed to find the video frame buffer information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseGfxInfo (\r
+ OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo\r
+ );\r
+\r
+/**\r
+ Find the video frame buffer device information\r
+\r
+ @param GfxDeviceInfo Pointer to the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the video frame buffer information.\r
+ @retval RETURN_NOT_FOUND Failed to find the video frame buffer information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseGfxDeviceInfo (\r
+ OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Bootloader Platform Support library. Platform can provide an implementation of this\r
+ library class to provide hooks that may be required for some type of\r
+ platform features.\r
+\r
+Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef __BOOTLOADER_PLATFORM_SUPPORT_LIB__\r
+#define __BOOTLOADER_PLATFORM_SUPPORT_LIB__\r
+\r
+/**\r
+ Parse platform specific information from bootloader\r
+\r
+ @retval RETURN_SUCCESS The platform specific coreboot support succeeded.\r
+ @retval RETURN_DEVICE_ERROR The platform specific coreboot support could not be completed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ParsePlatformInfo (\r
+ VOID\r
+ );\r
+\r
+#endif // __BOOTLOADER_PLATFORM_SUPPORT_LIB__\r
+\r
--- /dev/null
+/** @file\r
+ ACPI Timer implements one instance of Timer Library.\r
+\r
+ Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Guid/AcpiBoardInfoGuid.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+#define ACPI_TIMER_COUNT_SIZE BIT24\r
+\r
+UINTN mPmTimerReg = 0;\r
+\r
+/**\r
+ The constructor function enables ACPI IO space.\r
+\r
+ If ACPI I/O space not enabled, this function will enable it.\r
+ It will always return RETURN_SUCCESS.\r
+\r
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+AcpiTimerLibConstructor (\r
+ VOID\r
+ )\r
+{\r
+ EFI_HOB_GUID_TYPE *GuidHob;\r
+ ACPI_BOARD_INFO *pAcpiBoardInfo;\r
+\r
+ //\r
+ // Find the acpi board information guid hob\r
+ //\r
+ GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);\r
+ ASSERT (GuidHob != NULL);\r
+\r
+ pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);\r
+\r
+ mPmTimerReg = (UINTN)pAcpiBoardInfo->PmTimerRegBase;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Internal function to read the current tick counter of ACPI.\r
+\r
+ Internal function to read the current tick counter of ACPI.\r
+\r
+ @return The tick counter read.\r
+\r
+**/\r
+UINT32\r
+InternalAcpiGetTimerTick (\r
+ VOID\r
+ )\r
+{\r
+ if (mPmTimerReg == 0) {\r
+ AcpiTimerLibConstructor ();\r
+ }\r
+ return IoRead32 (mPmTimerReg);\r
+}\r
+\r
+/**\r
+ Stalls the CPU for at least the given number of ticks.\r
+\r
+ Stalls the CPU for at least the given number of ticks. It's invoked by\r
+ MicroSecondDelay() and NanoSecondDelay().\r
+\r
+ @param Delay A period of time to delay in ticks.\r
+\r
+**/\r
+VOID\r
+InternalAcpiDelay (\r
+ IN UINT32 Delay\r
+ )\r
+{\r
+ UINT32 Ticks;\r
+ UINT32 Times;\r
+\r
+ Times = Delay >> 22;\r
+ Delay &= BIT22 - 1;\r
+ do {\r
+ //\r
+ // The target timer count is calculated here\r
+ //\r
+ Ticks = InternalAcpiGetTimerTick () + Delay;\r
+ Delay = BIT22;\r
+ //\r
+ // Wait until time out\r
+ // Delay >= 2^23 could not be handled by this function\r
+ // Timer wrap-arounds are handled correctly by this function\r
+ //\r
+ while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {\r
+ CpuPause ();\r
+ }\r
+ } while (Times-- > 0);\r
+}\r
+\r
+/**\r
+ Stalls the CPU for at least the given number of microseconds.\r
+\r
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.\r
+\r
+ @param MicroSeconds The minimum number of microseconds to delay.\r
+\r
+ @return MicroSeconds\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+MicroSecondDelay (\r
+ IN UINTN MicroSeconds\r
+ )\r
+{\r
+ InternalAcpiDelay (\r
+ (UINT32)DivU64x32 (\r
+ MultU64x32 (\r
+ MicroSeconds,\r
+ ACPI_TIMER_FREQUENCY\r
+ ),\r
+ 1000000u\r
+ )\r
+ );\r
+ return MicroSeconds;\r
+}\r
+\r
+/**\r
+ Stalls the CPU for at least the given number of nanoseconds.\r
+\r
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r
+\r
+ @param NanoSeconds The minimum number of nanoseconds to delay.\r
+\r
+ @return NanoSeconds\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+NanoSecondDelay (\r
+ IN UINTN NanoSeconds\r
+ )\r
+{\r
+ InternalAcpiDelay (\r
+ (UINT32)DivU64x32 (\r
+ MultU64x32 (\r
+ NanoSeconds,\r
+ ACPI_TIMER_FREQUENCY\r
+ ),\r
+ 1000000000u\r
+ )\r
+ );\r
+ return NanoSeconds;\r
+}\r
+\r
+/**\r
+ Retrieves the current value of a 64-bit free running performance counter.\r
+\r
+ Retrieves the current value of a 64-bit free running performance counter. The\r
+ counter can either count up by 1 or count down by 1. If the physical\r
+ performance counter counts by a larger increment, then the counter values\r
+ must be translated. The properties of the counter can be retrieved from\r
+ GetPerformanceCounterProperties().\r
+\r
+ @return The current value of the free running performance counter.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPerformanceCounter (\r
+ VOID\r
+ )\r
+{\r
+ return (UINT64)InternalAcpiGetTimerTick ();\r
+}\r
+\r
+/**\r
+ Retrieves the 64-bit frequency in Hz and the range of performance counter\r
+ values.\r
+\r
+ If StartValue is not NULL, then the value that the performance counter starts\r
+ with immediately after is it rolls over is returned in StartValue. If\r
+ EndValue is not NULL, then the value that the performance counter end with\r
+ immediately before it rolls over is returned in EndValue. The 64-bit\r
+ frequency of the performance counter in Hz is always returned. If StartValue\r
+ is less than EndValue, then the performance counter counts up. If StartValue\r
+ is greater than EndValue, then the performance counter counts down. For\r
+ example, a 64-bit free running counter that counts up would have a StartValue\r
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r
+\r
+ @param StartValue The value the performance counter starts with when it\r
+ rolls over.\r
+ @param EndValue The value that the performance counter ends with before\r
+ it rolls over.\r
+\r
+ @return The frequency in Hz.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPerformanceCounterProperties (\r
+ OUT UINT64 *StartValue, OPTIONAL\r
+ OUT UINT64 *EndValue OPTIONAL\r
+ )\r
+{\r
+ if (StartValue != NULL) {\r
+ *StartValue = 0;\r
+ }\r
+\r
+ if (EndValue != NULL) {\r
+ *EndValue = ACPI_TIMER_COUNT_SIZE - 1;\r
+ }\r
+\r
+ return ACPI_TIMER_FREQUENCY;\r
+}\r
+\r
+/**\r
+ Converts elapsed ticks of performance counter to time in nanoseconds.\r
+\r
+ This function converts the elapsed ticks of running performance counter to\r
+ time value in unit of nanoseconds.\r
+\r
+ @param Ticks The number of elapsed ticks of running performance counter.\r
+\r
+ @return The elapsed time in nanoseconds.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetTimeInNanoSecond (\r
+ IN UINT64 Ticks\r
+ )\r
+{\r
+ UINT64 Frequency;\r
+ UINT64 NanoSeconds;\r
+ UINT64 Remainder;\r
+ INTN Shift;\r
+\r
+ Frequency = GetPerformanceCounterProperties (NULL, NULL);\r
+\r
+ //\r
+ // Ticks\r
+ // Time = --------- x 1,000,000,000\r
+ // Frequency\r
+ //\r
+ NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);\r
+\r
+ //\r
+ // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.\r
+ // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
+ // i.e. highest bit set in Remainder should <= 33.\r
+ //\r
+ Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
+ Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
+ Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
+ NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
+\r
+ return NanoSeconds;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# ACPI Timer Library Instance.\r
+#\r
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = AcpiTimerLib\r
+ FILE_GUID = A41BF616-EF77-4658-9992-D813071C34CF\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = TimerLib\r
+\r
+ CONSTRUCTOR = AcpiTimerLibConstructor\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ AcpiTimerLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ IoLib\r
+ HobLib\r
+ DebugLib\r
+\r
+[Guids]\r
+ gUefiAcpiBoardInfoGuid\r
--- /dev/null
+/** @file\r
+ This library will parse the coreboot table in memory and extract those required\r
+ information.\r
+\r
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/BlParseLib.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <Coreboot.h>\r
+\r
+\r
+/**\r
+ Convert a packed value from cbuint64 to a UINT64 value.\r
+\r
+ @param val The pointer to packed data.\r
+\r
+ @return the UNIT64 value after conversion.\r
+\r
+**/\r
+UINT64\r
+cb_unpack64 (\r
+ IN struct cbuint64 val\r
+ )\r
+{\r
+ return LShiftU64 (val.hi, 32) | val.lo;\r
+}\r
+\r
+\r
+/**\r
+ Returns the sum of all elements in a buffer of 16-bit values. During\r
+ calculation, the carry bits are also been added.\r
+\r
+ @param Buffer The pointer to the buffer to carry out the sum operation.\r
+ @param Length The size, in bytes, of Buffer.\r
+\r
+ @return Sum The sum of Buffer with carry bits included during additions.\r
+\r
+**/\r
+UINT16\r
+CbCheckSum16 (\r
+ IN UINT16 *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINT32 Sum;\r
+ UINT32 TmpValue;\r
+ UINTN Idx;\r
+ UINT8 *TmpPtr;\r
+\r
+ Sum = 0;\r
+ TmpPtr = (UINT8 *)Buffer;\r
+ for(Idx = 0; Idx < Length; Idx++) {\r
+ TmpValue = TmpPtr[Idx];\r
+ if (Idx % 2 == 1) {\r
+ TmpValue <<= 8;\r
+ }\r
+\r
+ Sum += TmpValue;\r
+\r
+ // Wrap\r
+ if (Sum >= 0x10000) {\r
+ Sum = (Sum + (Sum >> 16)) & 0xFFFF;\r
+ }\r
+ }\r
+\r
+ return (UINT16)((~Sum) & 0xFFFF);\r
+}\r
+\r
+\r
+/**\r
+ Check the coreboot table if it is valid.\r
+\r
+ @param Header Pointer to coreboot table\r
+\r
+ @retval TRUE The coreboot table is valid.\r
+ @retval Others The coreboot table is not valid.\r
+\r
+**/\r
+BOOLEAN\r
+IsValidCbTable (\r
+ IN struct cb_header *Header\r
+ )\r
+{\r
+ UINT16 CheckSum;\r
+\r
+ if ((Header == NULL) || (Header->table_bytes == 0)) {\r
+ return FALSE;\r
+ }\r
+\r
+ if (Header->signature != CB_HEADER_SIGNATURE) {\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // Check the checksum of the coreboot table header\r
+ //\r
+ CheckSum = CbCheckSum16 ((UINT16 *)Header, sizeof (*Header));\r
+ if (CheckSum != 0) {\r
+ DEBUG ((DEBUG_ERROR, "Invalid coreboot table header checksum\n"));\r
+ return FALSE;\r
+ }\r
+\r
+ CheckSum = CbCheckSum16 ((UINT16 *)((UINT8 *)Header + sizeof (*Header)), Header->table_bytes);\r
+ if (CheckSum != Header->table_checksum) {\r
+ DEBUG ((DEBUG_ERROR, "Incorrect checksum of all the coreboot table entries\n"));\r
+ return FALSE;\r
+ }\r
+\r
+ return TRUE;\r
+}\r
+\r
+\r
+/**\r
+ This function retrieves the parameter base address from boot loader.\r
+\r
+ This function will get bootloader specific parameter address for UEFI payload.\r
+ e.g. HobList pointer for Slim Bootloader, and coreboot table header for Coreboot.\r
+\r
+ @retval NULL Failed to find the GUID HOB.\r
+ @retval others GUIDed HOB data pointer.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetParameterBase (\r
+ VOID\r
+ )\r
+{\r
+ struct cb_header *Header;\r
+ struct cb_record *Record;\r
+ UINT8 *TmpPtr;\r
+ UINT8 *CbTablePtr;\r
+ UINTN Idx;\r
+\r
+ //\r
+ // coreboot could pass coreboot table to UEFI payload\r
+ //\r
+ Header = (struct cb_header *)(UINTN)GET_BOOTLOADER_PARAMETER ();\r
+ if (IsValidCbTable (Header)) {\r
+ return Header;\r
+ }\r
+\r
+ //\r
+ // Find simplified coreboot table in memory range 0 ~ 4KB.\r
+ // Some GCC version does not allow directly access to NULL pointer,\r
+ // so start the search from 0x10 instead.\r
+ //\r
+ for (Idx = 16; Idx < 4096; Idx += 16) {\r
+ Header = (struct cb_header *)Idx;\r
+ if (Header->signature == CB_HEADER_SIGNATURE) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (Idx >= 4096) {\r
+ return NULL;\r
+ }\r
+\r
+ //\r
+ // Check the coreboot header\r
+ //\r
+ if (!IsValidCbTable (Header)) {\r
+ return NULL;\r
+ }\r
+\r
+ //\r
+ // Find full coreboot table in high memory\r
+ //\r
+ CbTablePtr = NULL;\r
+ TmpPtr = (UINT8 *)Header + Header->header_bytes;\r
+ for (Idx = 0; Idx < Header->table_entries; Idx++) {\r
+ Record = (struct cb_record *)TmpPtr;\r
+ if (Record->tag == CB_TAG_FORWARD) {\r
+ CbTablePtr = (VOID *)(UINTN)((struct cb_forward *)(UINTN)Record)->forward;\r
+ break;\r
+ }\r
+ TmpPtr += Record->size;\r
+ }\r
+\r
+ //\r
+ // Check the coreboot header in high memory\r
+ //\r
+ if (!IsValidCbTable ((struct cb_header *)CbTablePtr)) {\r
+ return NULL;\r
+ }\r
+\r
+ SET_BOOTLOADER_PARAMETER ((UINT32)(UINTN)CbTablePtr);\r
+\r
+ return CbTablePtr;\r
+}\r
+\r
+\r
+/**\r
+ Find coreboot record with given Tag.\r
+\r
+ @param Tag The tag id to be found\r
+\r
+ @retval NULL The Tag is not found.\r
+ @retval Others The pointer to the record found.\r
+\r
+**/\r
+VOID *\r
+FindCbTag (\r
+ IN UINT32 Tag\r
+ )\r
+{\r
+ struct cb_header *Header;\r
+ struct cb_record *Record;\r
+ UINT8 *TmpPtr;\r
+ UINT8 *TagPtr;\r
+ UINTN Idx;\r
+\r
+ Header = (struct cb_header *) GetParameterBase ();\r
+\r
+ TagPtr = NULL;\r
+ TmpPtr = (UINT8 *)Header + Header->header_bytes;\r
+ for (Idx = 0; Idx < Header->table_entries; Idx++) {\r
+ Record = (struct cb_record *)TmpPtr;\r
+ if (Record->tag == Tag) {\r
+ TagPtr = TmpPtr;\r
+ break;\r
+ }\r
+ TmpPtr += Record->size;\r
+ }\r
+\r
+ return TagPtr;\r
+}\r
+\r
+\r
+/**\r
+ Find the given table with TableId from the given coreboot memory Root.\r
+\r
+ @param Root The coreboot memory table to be searched in\r
+ @param TableId Table id to be found\r
+ @param MemTable To save the base address of the memory table found\r
+ @param MemTableSize To save the size of memory table found\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the memory table.\r
+ @retval RETURN_INVALID_PARAMETER Invalid input parameters.\r
+ @retval RETURN_NOT_FOUND Failed to find the memory table.\r
+\r
+**/\r
+RETURN_STATUS\r
+FindCbMemTable (\r
+ IN struct cbmem_root *Root,\r
+ IN UINT32 TableId,\r
+ OUT VOID **MemTable,\r
+ OUT UINT32 *MemTableSize\r
+ )\r
+{\r
+ UINTN Idx;\r
+ BOOLEAN IsImdEntry;\r
+ struct cbmem_entry *Entries;\r
+\r
+ if ((Root == NULL) || (MemTable == NULL)) {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Check if the entry is CBMEM or IMD\r
+ // and handle them separately\r
+ //\r
+ Entries = Root->entries;\r
+ if (Entries[0].magic == CBMEM_ENTRY_MAGIC) {\r
+ IsImdEntry = FALSE;\r
+ } else {\r
+ Entries = (struct cbmem_entry *)((struct imd_root *)Root)->entries;\r
+ if (Entries[0].magic == IMD_ENTRY_MAGIC) {\r
+ IsImdEntry = TRUE;\r
+ } else {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ for (Idx = 0; Idx < Root->num_entries; Idx++) {\r
+ if (Entries[Idx].id == TableId) {\r
+ if (IsImdEntry) {\r
+ *MemTable = (VOID *) ((UINTN)Entries[Idx].start + (UINTN)Root);\r
+ } else {\r
+ *MemTable = (VOID *) (UINTN)Entries[Idx].start;\r
+ }\r
+ if (MemTableSize != NULL) {\r
+ *MemTableSize = Entries[Idx].size;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",\r
+ TableId, *MemTable, Entries[Idx].size));\r
+ return RETURN_SUCCESS;\r
+ }\r
+ }\r
+\r
+ return RETURN_NOT_FOUND;\r
+}\r
+\r
+/**\r
+ Acquire the coreboot memory table with the given table id\r
+\r
+ @param TableId Table id to be searched\r
+ @param MemTable Pointer to the base address of the memory table\r
+ @param MemTableSize Pointer to the size of the memory table\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the memory table.\r
+ @retval RETURN_INVALID_PARAMETER Invalid input parameters.\r
+ @retval RETURN_NOT_FOUND Failed to find the memory table.\r
+\r
+**/\r
+RETURN_STATUS\r
+ParseCbMemTable (\r
+ IN UINT32 TableId,\r
+ OUT VOID **MemTable,\r
+ OUT UINT32 *MemTableSize\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ struct cb_memory *rec;\r
+ struct cb_memory_range *Range;\r
+ UINT64 Start;\r
+ UINT64 Size;\r
+ UINTN Index;\r
+ struct cbmem_root *CbMemRoot;\r
+\r
+ if (MemTable == NULL) {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ *MemTable = NULL;\r
+ Status = RETURN_NOT_FOUND;\r
+\r
+ //\r
+ // Get the coreboot memory table\r
+ //\r
+ rec = (struct cb_memory *)FindCbTag (CB_TAG_MEMORY);\r
+ if (rec == NULL) {\r
+ return Status;\r
+ }\r
+\r
+ for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {\r
+ Range = MEM_RANGE_PTR(rec, Index);\r
+ Start = cb_unpack64(Range->start);\r
+ Size = cb_unpack64(Range->size);\r
+\r
+ if ((Range->type == CB_MEM_TABLE) && (Start > 0x1000)) {\r
+ CbMemRoot = (struct cbmem_root *)(UINTN)(Start + Size - DYN_CBMEM_ALIGN_SIZE);\r
+ Status = FindCbMemTable (CbMemRoot, TableId, MemTable, MemTableSize);\r
+ if (!EFI_ERROR (Status)) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+\r
+/**\r
+ Acquire the memory information from the coreboot table in memory.\r
+\r
+ @param MemInfoCallback The callback routine\r
+ @param Params Pointer to the callback routine parameter\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the memory information.\r
+ @retval RETURN_NOT_FOUND Failed to find the memory information.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseMemoryInfo (\r
+ IN BL_MEM_INFO_CALLBACK MemInfoCallback,\r
+ IN VOID *Params\r
+ )\r
+{\r
+ struct cb_memory *rec;\r
+ struct cb_memory_range *Range;\r
+ UINTN Index;\r
+ MEMROY_MAP_ENTRY MemoryMap;\r
+\r
+ //\r
+ // Get the coreboot memory table\r
+ //\r
+ rec = (struct cb_memory *)FindCbTag (CB_TAG_MEMORY);\r
+ if (rec == NULL) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {\r
+ Range = MEM_RANGE_PTR(rec, Index);\r
+ MemoryMap.Base = cb_unpack64(Range->start);\r
+ MemoryMap.Size = cb_unpack64(Range->size);\r
+ MemoryMap.Type = (UINT8)Range->type;\r
+ MemoryMap.Flag = 0;\r
+ DEBUG ((DEBUG_INFO, "%d. %016lx - %016lx [%02x]\n",\r
+ Index, MemoryMap.Base, MemoryMap.Base + MemoryMap.Size - 1, MemoryMap.Type));\r
+\r
+ MemInfoCallback (&MemoryMap, Params);\r
+ }\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Acquire acpi table and smbios table from coreboot\r
+\r
+ @param SystemTableInfo Pointer to the system table info\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the tables.\r
+ @retval RETURN_NOT_FOUND Failed to find the tables.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseSystemTable (\r
+ OUT SYSTEM_TABLE_INFO *SystemTableInfo\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *MemTable;\r
+ UINT32 MemTableSize;\r
+\r
+ Status = ParseCbMemTable (SIGNATURE_32 ('T', 'B', 'M', 'S'), &MemTable, &MemTableSize);\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ SystemTableInfo->SmbiosTableBase = (UINT64) (UINTN)MemTable;\r
+ SystemTableInfo->SmbiosTableSize = MemTableSize;\r
+\r
+ Status = ParseCbMemTable (SIGNATURE_32 ('I', 'P', 'C', 'A'), &MemTable, &MemTableSize);\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ SystemTableInfo->AcpiTableBase = (UINT64) (UINTN)MemTable;\r
+ SystemTableInfo->AcpiTableSize = MemTableSize;\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Find the serial port information\r
+\r
+ @param SERIAL_PORT_INFO Pointer to serial port info structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the serial port information.\r
+ @retval RETURN_NOT_FOUND Failed to find the serial port information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseSerialInfo (\r
+ OUT SERIAL_PORT_INFO *SerialPortInfo\r
+ )\r
+{\r
+ struct cb_serial *CbSerial;\r
+\r
+ CbSerial = FindCbTag (CB_TAG_SERIAL);\r
+ if (CbSerial == NULL) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ SerialPortInfo->BaseAddr = CbSerial->baseaddr;\r
+ SerialPortInfo->RegWidth = CbSerial->regwidth;\r
+ SerialPortInfo->Type = CbSerial->type;\r
+ SerialPortInfo->Baud = CbSerial->baud;\r
+ SerialPortInfo->InputHertz = CbSerial->input_hertz;\r
+ SerialPortInfo->UartPciAddr = CbSerial->uart_pci_addr;\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Find the video frame buffer information\r
+\r
+ @param GfxInfo Pointer to the EFI_PEI_GRAPHICS_INFO_HOB structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the video frame buffer information.\r
+ @retval RETURN_NOT_FOUND Failed to find the video frame buffer information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseGfxInfo (\r
+ OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo\r
+ )\r
+{\r
+ struct cb_framebuffer *CbFbRec;\r
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *GfxMode;\r
+\r
+ if (GfxInfo == NULL) {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ CbFbRec = FindCbTag (CB_TAG_FRAMEBUFFER);\r
+ if (CbFbRec == NULL) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ DEBUG ((DEBUG_INFO, "Found coreboot video frame buffer information\n"));\r
+ DEBUG ((DEBUG_INFO, "physical_address: 0x%lx\n", CbFbRec->physical_address));\r
+ DEBUG ((DEBUG_INFO, "x_resolution: 0x%x\n", CbFbRec->x_resolution));\r
+ DEBUG ((DEBUG_INFO, "y_resolution: 0x%x\n", CbFbRec->y_resolution));\r
+ DEBUG ((DEBUG_INFO, "bits_per_pixel: 0x%x\n", CbFbRec->bits_per_pixel));\r
+ DEBUG ((DEBUG_INFO, "bytes_per_line: 0x%x\n", CbFbRec->bytes_per_line));\r
+\r
+ DEBUG ((DEBUG_INFO, "red_mask_size: 0x%x\n", CbFbRec->red_mask_size));\r
+ DEBUG ((DEBUG_INFO, "red_mask_pos: 0x%x\n", CbFbRec->red_mask_pos));\r
+ DEBUG ((DEBUG_INFO, "green_mask_size: 0x%x\n", CbFbRec->green_mask_size));\r
+ DEBUG ((DEBUG_INFO, "green_mask_pos: 0x%x\n", CbFbRec->green_mask_pos));\r
+ DEBUG ((DEBUG_INFO, "blue_mask_size: 0x%x\n", CbFbRec->blue_mask_size));\r
+ DEBUG ((DEBUG_INFO, "blue_mask_pos: 0x%x\n", CbFbRec->blue_mask_pos));\r
+ DEBUG ((DEBUG_INFO, "reserved_mask_size: 0x%x\n", CbFbRec->reserved_mask_size));\r
+ DEBUG ((DEBUG_INFO, "reserved_mask_pos: 0x%x\n", CbFbRec->reserved_mask_pos));\r
+\r
+ GfxMode = &GfxInfo->GraphicsMode;\r
+ GfxMode->Version = 0;\r
+ GfxMode->HorizontalResolution = CbFbRec->x_resolution;\r
+ GfxMode->VerticalResolution = CbFbRec->y_resolution;\r
+ GfxMode->PixelsPerScanLine = (CbFbRec->bytes_per_line << 3) / CbFbRec->bits_per_pixel;\r
+ if ((CbFbRec->red_mask_pos == 0) && (CbFbRec->green_mask_pos == 8) && (CbFbRec->blue_mask_pos == 16)) {\r
+ GfxMode->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;\r
+ } else if ((CbFbRec->blue_mask_pos == 0) && (CbFbRec->green_mask_pos == 8) && (CbFbRec->red_mask_pos == 16)) {\r
+ GfxMode->PixelFormat = PixelBlueGreenRedReserved8BitPerColor;\r
+ }\r
+ GfxMode->PixelInformation.RedMask = ((1 << CbFbRec->red_mask_size) - 1) << CbFbRec->red_mask_pos;\r
+ GfxMode->PixelInformation.GreenMask = ((1 << CbFbRec->green_mask_size) - 1) << CbFbRec->green_mask_pos;\r
+ GfxMode->PixelInformation.BlueMask = ((1 << CbFbRec->blue_mask_size) - 1) << CbFbRec->blue_mask_pos;\r
+ GfxMode->PixelInformation.ReservedMask = ((1 << CbFbRec->reserved_mask_size) - 1) << CbFbRec->reserved_mask_pos;\r
+\r
+ GfxInfo->FrameBufferBase = CbFbRec->physical_address;\r
+ GfxInfo->FrameBufferSize = CbFbRec->bytes_per_line * CbFbRec->y_resolution;\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Find the video frame buffer device information\r
+\r
+ @param GfxDeviceInfo Pointer to the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the video frame buffer information.\r
+ @retval RETURN_NOT_FOUND Failed to find the video frame buffer information.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseGfxDeviceInfo (\r
+ OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo\r
+ )\r
+{\r
+ return RETURN_NOT_FOUND;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# Coreboot Table Parse Library.\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = CbParseLib\r
+ FILE_GUID = 49EDFC9E-5945-4386-9C0B-C9B60CD45BB1\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = BlParseLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ CbParseLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ IoLib\r
+ DebugLib\r
+ PcdLib\r
+\r
+[Pcd]\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadStackTop\r
--- /dev/null
+/** @file\r
+ Header file of PciHostBridgeLib.\r
+\r
+ Copyright (C) 2016, Red Hat, Inc.\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef _PCI_HOST_BRIDGE_H\r
+#define _PCI_HOST_BRIDGE_H\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
+} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+ UINTN *NumberOfRootBridges\r
+);\r
+\r
+/**\r
+ Initialize a PCI_ROOT_BRIDGE structure.\r
+\r
+ @param[in] Supports Supported attributes.\r
+\r
+ @param[in] Attributes Initial attributes.\r
+\r
+ @param[in] AllocAttributes Allocation attributes.\r
+\r
+ @param[in] RootBusNumber The bus number to store in RootBus.\r
+\r
+ @param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
+ assigned to any subordinate bus found behind any\r
+ PCI bridge hanging off this root bus.\r
+\r
+ The caller is responsible for ensuring that\r
+ RootBusNumber <= MaxSubBusNumber. If\r
+ RootBusNumber equals MaxSubBusNumber, then the\r
+ root bus has no room for subordinate buses.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+\r
+ @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
+ caller) that should be filled in by this\r
+ function.\r
+\r
+ @retval EFI_SUCCESS Initialization successful. A device path\r
+ consisting of an ACPI device path node, with\r
+ UID = RootBusNumber, has been allocated and\r
+ linked into RootBus.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
+**/\r
+EFI_STATUS\r
+InitRootBridge (\r
+ IN UINT64 Supports,\r
+ IN UINT64 Attributes,\r
+ IN UINT64 AllocAttributes,\r
+ IN UINT8 RootBusNumber,\r
+ IN UINT8 MaxSubBusNumber,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
+ OUT PCI_ROOT_BRIDGE *RootBus\r
+);\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Library instance of PciHostBridgeLib library class for coreboot.\r
+\r
+ Copyright (C) 2016, Red Hat, Inc.\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciHostBridgeLib.h>\r
+#include <Library/PciLib.h>\r
+\r
+#include "PciHostBridge.h"\r
+\r
+STATIC\r
+CONST\r
+CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {\r
+ {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ {\r
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EISA_PNP_ID(0x0A03), // HID\r
+ 0 // UID\r
+ },\r
+\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+};\r
+\r
+\r
+/**\r
+ Initialize a PCI_ROOT_BRIDGE structure.\r
+\r
+ @param[in] Supports Supported attributes.\r
+\r
+ @param[in] Attributes Initial attributes.\r
+\r
+ @param[in] AllocAttributes Allocation attributes.\r
+\r
+ @param[in] RootBusNumber The bus number to store in RootBus.\r
+\r
+ @param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
+ assigned to any subordinate bus found behind any\r
+ PCI bridge hanging off this root bus.\r
+\r
+ The caller is responsible for ensuring that\r
+ RootBusNumber <= MaxSubBusNumber. If\r
+ RootBusNumber equals MaxSubBusNumber, then the\r
+ root bus has no room for subordinate buses.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+\r
+ @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
+ caller) that should be filled in by this\r
+ function.\r
+\r
+ @retval EFI_SUCCESS Initialization successful. A device path\r
+ consisting of an ACPI device path node, with\r
+ UID = RootBusNumber, has been allocated and\r
+ linked into RootBus.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
+**/\r
+EFI_STATUS\r
+InitRootBridge (\r
+ IN UINT64 Supports,\r
+ IN UINT64 Attributes,\r
+ IN UINT64 AllocAttributes,\r
+ IN UINT8 RootBusNumber,\r
+ IN UINT8 MaxSubBusNumber,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
+ OUT PCI_ROOT_BRIDGE *RootBus\r
+)\r
+{\r
+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
+\r
+ //\r
+ // Be safe if other fields are added to PCI_ROOT_BRIDGE later.\r
+ //\r
+ ZeroMem (RootBus, sizeof *RootBus);\r
+\r
+ RootBus->Segment = 0;\r
+\r
+ RootBus->Supports = Supports;\r
+ RootBus->Attributes = Attributes;\r
+\r
+ RootBus->DmaAbove4G = FALSE;\r
+\r
+ RootBus->AllocationAttributes = AllocAttributes;\r
+ RootBus->Bus.Base = RootBusNumber;\r
+ RootBus->Bus.Limit = MaxSubBusNumber;\r
+ CopyMem (&RootBus->Io, Io, sizeof (*Io));\r
+ CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));\r
+ CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));\r
+ CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));\r
+ CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));\r
+\r
+ RootBus->NoExtendedConfigSpace = FALSE;\r
+\r
+ DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),\r
+ &mRootBridgeDevicePathTemplate);\r
+ if (DevicePath == NULL) {\r
+ DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ DevicePath->AcpiDevicePath.UID = RootBusNumber;\r
+ RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
+\r
+ DEBUG ((DEBUG_INFO,\r
+ "%a: populated root bus %d, with room for %d subordinate bus(es)\n",\r
+ __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Return all the root bridge instances in an array.\r
+\r
+ @param Count Return the count of root bridge instances.\r
+\r
+ @return All the root bridge instances in an array.\r
+ The array should be passed into PciHostBridgeFreeRootBridges()\r
+ when it's not used.\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+EFIAPI\r
+PciHostBridgeGetRootBridges (\r
+ UINTN *Count\r
+)\r
+{\r
+ return ScanForRootBridges (Count);\r
+}\r
+\r
+\r
+/**\r
+ Free the root bridge instances array returned from\r
+ PciHostBridgeGetRootBridges().\r
+\r
+ @param The root bridge instances array.\r
+ @param The count of the array.\r
+**/\r
+VOID\r
+EFIAPI\r
+PciHostBridgeFreeRootBridges (\r
+ PCI_ROOT_BRIDGE *Bridges,\r
+ UINTN Count\r
+)\r
+{\r
+ if (Bridges == NULL && Count == 0) {\r
+ return;\r
+ }\r
+ ASSERT (Bridges != NULL && Count > 0);\r
+\r
+ do {\r
+ --Count;\r
+ FreePool (Bridges[Count].DevicePath);\r
+ } while (Count > 0);\r
+\r
+ FreePool (Bridges);\r
+}\r
+\r
+\r
+/**\r
+ Inform the platform that the resource conflict happens.\r
+\r
+ @param HostBridgeHandle Handle of the Host Bridge.\r
+ @param Configuration Pointer to PCI I/O and PCI memory resource\r
+ descriptors. The Configuration contains the resources\r
+ for all the root bridges. The resource for each root\r
+ bridge is terminated with END descriptor and an\r
+ additional END is appended indicating the end of the\r
+ entire resources. The resource descriptor field\r
+ values follow the description in\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r
+ .SubmitResources().\r
+**/\r
+VOID\r
+EFIAPI\r
+PciHostBridgeResourceConflict (\r
+ EFI_HANDLE HostBridgeHandle,\r
+ VOID *Configuration\r
+)\r
+{\r
+ //\r
+ // coreboot UEFI Payload does not do PCI enumeration and should not call this\r
+ // library interface.\r
+ //\r
+ ASSERT (FALSE);\r
+}\r
--- /dev/null
+## @file\r
+# Library instance of PciHostBridgeLib library class for coreboot.\r
+#\r
+# Copyright (C) 2016, Red Hat, Inc.\r
+# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PciHostBridgeLib\r
+ FILE_GUID = 62EE5269-CFFD-43a3-BE3F-622FC79F467E\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PciHostBridgeLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build\r
+# tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ PciHostBridge.h\r
+ PciHostBridgeLib.c\r
+ PciHostBridgeSupport.c\r
+\r
+[Packages]\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseMemoryLib\r
+ DebugLib\r
+ DevicePathLib\r
+ MemoryAllocationLib\r
+ PciLib\r
--- /dev/null
+/** @file\r
+ Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Pci.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciHostBridgeLib.h>\r
+#include <Library/PciLib.h>\r
+#include "PciHostBridge.h"\r
+\r
+/**\r
+ Adjust the collected PCI resource.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+**/\r
+VOID\r
+AdjustRootBridgeResource (\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
+)\r
+{\r
+ UINT64 Mask;\r
+\r
+ //\r
+ // For now try to downgrade everything into MEM32 since\r
+ // - coreboot does not assign resource above 4GB\r
+ // - coreboot might allocate interleaved MEM32 and PMEM32 resource\r
+ // in some cases\r
+ //\r
+ if (PMem->Base < Mem->Base) {\r
+ Mem->Base = PMem->Base;\r
+ }\r
+\r
+ if (PMem->Limit > Mem->Limit) {\r
+ Mem->Limit = PMem->Limit;\r
+ }\r
+\r
+ PMem->Base = MAX_UINT64;\r
+ PMem->Limit = 0;\r
+\r
+ if (MemAbove4G->Base < 0x100000000ULL) {\r
+ if (MemAbove4G->Base < Mem->Base) {\r
+ Mem->Base = MemAbove4G->Base;\r
+ }\r
+ if (MemAbove4G->Limit > Mem->Limit) {\r
+ Mem->Limit = MemAbove4G->Limit;\r
+ }\r
+ MemAbove4G->Base = MAX_UINT64;\r
+ MemAbove4G->Limit = 0;\r
+ }\r
+\r
+ if (PMemAbove4G->Base < 0x100000000ULL) {\r
+ if (PMemAbove4G->Base < Mem->Base) {\r
+ Mem->Base = PMemAbove4G->Base;\r
+ }\r
+ if (PMemAbove4G->Limit > Mem->Limit) {\r
+ Mem->Limit = PMemAbove4G->Limit;\r
+ }\r
+ PMemAbove4G->Base = MAX_UINT64;\r
+ PMemAbove4G->Limit = 0;\r
+ }\r
+\r
+ //\r
+ // Align IO resource at 4K boundary\r
+ //\r
+ Mask = 0xFFFULL;\r
+ Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;\r
+ if (Io->Base != MAX_UINT64) {\r
+ Io->Base &= ~Mask;\r
+ }\r
+\r
+ //\r
+ // Align MEM resource at 1MB boundary\r
+ //\r
+ Mask = 0xFFFFFULL;\r
+ Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;\r
+ if (Mem->Base != MAX_UINT64) {\r
+ Mem->Base &= ~Mask;\r
+ }\r
+}\r
+\r
+/**\r
+ Probe a bar is existed or not.\r
+\r
+ @param[in] Address PCI address for the BAR.\r
+ @param[out] OriginalValue The original bar value returned.\r
+ @param[out] Value The probed bar value returned.\r
+**/\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeBarExisted (\r
+ IN UINT64 Address,\r
+ OUT UINT32 *OriginalValue,\r
+ OUT UINT32 *Value\r
+)\r
+{\r
+ UINTN PciAddress;\r
+\r
+ PciAddress = (UINTN)Address;\r
+\r
+ //\r
+ // Preserve the original value\r
+ //\r
+ *OriginalValue = PciRead32 (PciAddress);\r
+\r
+ //\r
+ // Disable timer interrupt while the BAR is probed\r
+ //\r
+ DisableInterrupts ();\r
+\r
+ PciWrite32 (PciAddress, 0xFFFFFFFF);\r
+ *Value = PciRead32 (PciAddress);\r
+ PciWrite32 (PciAddress, *OriginalValue);\r
+\r
+ //\r
+ // Enable interrupt\r
+ //\r
+ EnableInterrupts ();\r
+}\r
+\r
+/**\r
+ Parse PCI bar and collect the assigned PCI resource information.\r
+\r
+ @param[in] Command Supported attributes.\r
+\r
+ @param[in] Bus PCI bus number.\r
+\r
+ @param[in] Device PCI device number.\r
+\r
+ @param[in] Function PCI function number.\r
+\r
+ @param[in] BarOffsetBase PCI bar start offset.\r
+\r
+ @param[in] BarOffsetEnd PCI bar end offset.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+**/\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeParseBars (\r
+ IN UINT16 Command,\r
+ IN UINTN Bus,\r
+ IN UINTN Device,\r
+ IN UINTN Function,\r
+ IN UINTN BarOffsetBase,\r
+ IN UINTN BarOffsetEnd,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
+\r
+)\r
+{\r
+ UINT32 OriginalValue;\r
+ UINT32 Value;\r
+ UINT32 OriginalUpperValue;\r
+ UINT32 UpperValue;\r
+ UINT64 Mask;\r
+ UINTN Offset;\r
+ UINTN LowBit;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Limit;\r
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
+\r
+ for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalValue, &Value\r
+ );\r
+ if (Value == 0) {\r
+ continue;\r
+ }\r
+ if ((Value & BIT0) == BIT0) {\r
+ //\r
+ // IO Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
+ Mask = 0xfffffffc;\r
+ Base = OriginalValue & Mask;\r
+ Length = ((~(Value & Mask)) & Mask) + 0x04;\r
+ if (!(Value & 0xFFFF0000)) {\r
+ Length &= 0x0000FFFF;\r
+ }\r
+ Limit = Base + Length - 1;\r
+\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (Io->Base > Base) {\r
+ Io->Base = Base;\r
+ }\r
+ if (Io->Limit < Limit) {\r
+ Io->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ } else {\r
+ //\r
+ // Mem Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
+\r
+ Mask = 0xfffffff0;\r
+ Base = OriginalValue & Mask;\r
+ Length = Value & Mask;\r
+\r
+ if ((Value & (BIT1 | BIT2)) == 0) {\r
+ //\r
+ // 32bit\r
+ //\r
+ Length = ((~Length) + 1) & 0xffffffff;\r
+\r
+ if ((Value & BIT3) == BIT3) {\r
+ MemAperture = PMem;\r
+ } else {\r
+ MemAperture = Mem;\r
+ }\r
+ } else {\r
+ //\r
+ // 64bit\r
+ //\r
+ Offset += 4;\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalUpperValue,\r
+ &UpperValue\r
+ );\r
+\r
+ Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
+ Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
+ if (Length != 0) {\r
+ LowBit = LowBitSet64 (Length);\r
+ Length = LShiftU64 (1ULL, LowBit);\r
+ }\r
+\r
+ if ((Value & BIT3) == BIT3) {\r
+ MemAperture = PMemAbove4G;\r
+ } else {\r
+ MemAperture = MemAbove4G;\r
+ }\r
+ }\r
+\r
+ Limit = Base + Length - 1;\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Scan for all root bridges in platform.\r
+\r
+ @param[out] NumberOfRootBridges Number of root bridges detected\r
+\r
+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
+**/\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+ OUT UINTN *NumberOfRootBridges\r
+)\r
+{\r
+ UINTN PrimaryBus;\r
+ UINTN SubBus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINTN NumberOfDevices;\r
+ UINTN Address;\r
+ PCI_TYPE01 Pci;\r
+ UINT64 Attributes;\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+ UINT64 Value;\r
+ PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
+ PCI_ROOT_BRIDGE *RootBridges;\r
+ UINTN BarOffsetEnd;\r
+\r
+\r
+ *NumberOfRootBridges = 0;\r
+ RootBridges = NULL;\r
+\r
+ //\r
+ // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
+ // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
+ // root bridge's subordinate bus number + 1.\r
+ //\r
+ for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
+ SubBus = PrimaryBus;\r
+ Attributes = 0;\r
+\r
+ ZeroMem (&Io, sizeof (Io));\r
+ ZeroMem (&Mem, sizeof (Mem));\r
+ ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r
+ ZeroMem (&PMem, sizeof (PMem));\r
+ ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));\r
+ Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
+ //\r
+ // Scan all the PCI devices on the primary bus of the PCI root bridge\r
+ //\r
+ for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
+\r
+ for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
+\r
+ //\r
+ // Compute the PCI configuration address of the PCI device to probe\r
+ //\r
+ Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
+\r
+ //\r
+ // Read the Vendor ID from the PCI Configuration Header\r
+ //\r
+ if (PciRead16 (Address) == MAX_UINT16) {\r
+ if (Function == 0) {\r
+ //\r
+ // If the PCI Configuration Read fails, or a PCI device does not\r
+ // exist, then skip this entire PCI device\r
+ //\r
+ break;\r
+ } else {\r
+ //\r
+ // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
+ // PCI function.\r
+ //\r
+ continue;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Read the entire PCI Configuration Header\r
+ //\r
+ PciReadBuffer (Address, sizeof (Pci), &Pci);\r
+\r
+ //\r
+ // Increment the number of PCI device found on the primary bus of the\r
+ // PCI root bridge\r
+ //\r
+ NumberOfDevices++;\r
+\r
+ //\r
+ // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
+ // register of the PCI Config Header\r
+ //\r
+ if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ }\r
+\r
+ BarOffsetEnd = 0;\r
+\r
+ //\r
+ // PCI-PCI Bridge\r
+ //\r
+ if (IS_PCI_BRIDGE (&Pci)) {\r
+ //\r
+ // Get the Bus range that the PPB is decoding\r
+ //\r
+ if (Pci.Bridge.SubordinateBus > SubBus) {\r
+ //\r
+ // If the subordinate bus number of the PCI-PCI bridge is greater\r
+ // than the PCI root bridge's current subordinate bus number,\r
+ // then update the PCI root bridge's subordinate bus number\r
+ //\r
+ SubBus = Pci.Bridge.SubordinateBus;\r
+ }\r
+\r
+ //\r
+ // Get the I/O range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.IoBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
+ Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
+ if (Value == BIT0) {\r
+ Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
+ Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
+ }\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (Io.Base > Base) {\r
+ Io.Base = Base;\r
+ }\r
+ if (Io.Limit < Limit) {\r
+ Io.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Memory range that the PPB is decoding\r
+ //\r
+ Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (Mem.Base > Base) {\r
+ Mem.Base = Base;\r
+ }\r
+ if (Mem.Limit < Limit) {\r
+ Mem.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Prefetchable Memory range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
+ << 16) | 0xfffff;\r
+ MemAperture = &PMem;\r
+ if (Value == BIT0) {\r
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
+ MemAperture = &PMemAbove4G;\r
+ }\r
+ if ((Base > 0) && (Base < Limit)) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Look at the PPB Configuration for legacy decoding attributes\r
+ //\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
+ == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
+ == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
+ != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+ }\r
+\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
+ } else {\r
+ //\r
+ // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
+ // Ranges, and Prefetchable Memory Ranges the device is decoding\r
+ //\r
+ if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
+ }\r
+ }\r
+\r
+ PcatPciRootBridgeParseBars (\r
+ Pci.Hdr.Command,\r
+ PrimaryBus,\r
+ Device,\r
+ Function,\r
+ OFFSET_OF (PCI_TYPE00, Device.Bar),\r
+ BarOffsetEnd,\r
+ &Io,\r
+ &Mem, &MemAbove4G,\r
+ &PMem, &PMemAbove4G\r
+ );\r
+\r
+ //\r
+ // See if the PCI device is an IDE controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
+ PCI_CLASS_MASS_STORAGE_IDE)) {\r
+ if (Pci.Hdr.ClassCode[0] & 0x80) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x01) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x04) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // See if the PCI device is a legacy VGA controller or\r
+ // a standard VGA controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
+ IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
+ ) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+\r
+ //\r
+ // See if the PCI Device is a PCI - ISA or PCI - EISA\r
+ // or ISA_POSITIVE_DECODE Bridge device\r
+ //\r
+ if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
+ if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // If this device is not a multi function device, then skip the rest\r
+ // of this PCI device\r
+ //\r
+ if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If at least one PCI device was found on the primary bus of this PCI\r
+ // root bridge, then the PCI root bridge exists.\r
+ //\r
+ if (NumberOfDevices > 0) {\r
+ RootBridges = ReallocatePool (\r
+ (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
+ (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
+ RootBridges\r
+ );\r
+ ASSERT (RootBridges != NULL);\r
+\r
+ AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);\r
+\r
+ InitRootBridge (\r
+ Attributes, Attributes, 0,\r
+ (UINT8) PrimaryBus, (UINT8) SubBus,\r
+ &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
+ &RootBridges[*NumberOfRootBridges]\r
+ );\r
+ RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
+ //\r
+ // Increment the index for the next PCI Root Bridge\r
+ //\r
+ (*NumberOfRootBridges)++;\r
+ }\r
+ }\r
+\r
+ return RootBridges;\r
+}\r
--- /dev/null
+/** @file\r
+ This file include all platform action which can be customized\r
+ by IBV/OEM.\r
+\r
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include "PlatformBootManager.h"\r
+#include "PlatformConsole.h"\r
+\r
+VOID\r
+InstallReadyToLock (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle;\r
+ EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;\r
+\r
+ DEBUG((DEBUG_INFO,"InstallReadyToLock entering......\n"));\r
+ //\r
+ // Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter\r
+ // Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth\r
+ //\r
+ EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);\r
+ DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n"));\r
+\r
+ //\r
+ // Install DxeSmmReadyToLock protocol in order to lock SMM\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **) &SmmAccess);\r
+ if (!EFI_ERROR (Status)) {\r
+ Handle = NULL;\r
+ Status = gBS->InstallProtocolInterface (\r
+ &Handle,\r
+ &gEfiDxeSmmReadyToLockProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ DEBUG((DEBUG_INFO,"InstallReadyToLock end\n"));\r
+ return;\r
+}\r
+\r
+/**\r
+ Return the index of the load option in the load option array.\r
+\r
+ The function consider two load options are equal when the\r
+ OptionType, Attributes, Description, FilePath and OptionalData are equal.\r
+\r
+ @param Key Pointer to the load option to be found.\r
+ @param Array Pointer to the array of load options to be found.\r
+ @param Count Number of entries in the Array.\r
+\r
+ @retval -1 Key wasn't found in the Array.\r
+ @retval 0 ~ Count-1 The index of the Key in the Array.\r
+**/\r
+INTN\r
+PlatformFindLoadOption (\r
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,\r
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,\r
+ IN UINTN Count\r
+)\r
+{\r
+ UINTN Index;\r
+\r
+ for (Index = 0; Index < Count; Index++) {\r
+ if ((Key->OptionType == Array[Index].OptionType) &&\r
+ (Key->Attributes == Array[Index].Attributes) &&\r
+ (StrCmp (Key->Description, Array[Index].Description) == 0) &&\r
+ (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&\r
+ (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&\r
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {\r
+ return (INTN) Index;\r
+ }\r
+ }\r
+\r
+ return -1;\r
+}\r
+\r
+/**\r
+ Register a boot option using a file GUID in the FV.\r
+\r
+ @param FileGuid The file GUID name in FV.\r
+ @param Description The boot option description.\r
+ @param Attributes The attributes used for the boot option loading.\r
+**/\r
+VOID\r
+PlatformRegisterFvBootOption (\r
+ EFI_GUID *FileGuid,\r
+ CHAR16 *Description,\r
+ UINT32 Attributes\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN OptionIndex;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
+ UINTN BootOptionCount;\r
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);\r
+ DevicePath = AppendDevicePathNode (\r
+ DevicePathFromHandle (LoadedImage->DeviceHandle),\r
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode\r
+ );\r
+\r
+ Status = EfiBootManagerInitializeLoadOption (\r
+ &NewOption,\r
+ LoadOptionNumberUnassigned,\r
+ LoadOptionTypeBoot,\r
+ Attributes,\r
+ Description,\r
+ DevicePath,\r
+ NULL,\r
+ 0\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);\r
+\r
+ OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);\r
+\r
+ if (OptionIndex == -1) {\r
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ EfiBootManagerFreeLoadOption (&NewOption);\r
+ EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);\r
+ }\r
+}\r
+\r
+/**\r
+ Do the platform specific action before the console is connected.\r
+\r
+ Such as:\r
+ Update console variable;\r
+ Register new Driver#### or Boot####;\r
+ Signal ReadyToLock event.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerBeforeConsole (\r
+ VOID\r
+)\r
+{\r
+ EFI_INPUT_KEY Enter;\r
+ EFI_INPUT_KEY F2;\r
+ EFI_INPUT_KEY Down;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;\r
+\r
+ PlatformConsoleInit ();\r
+\r
+ //\r
+ // Register ENTER as CONTINUE key\r
+ //\r
+ Enter.ScanCode = SCAN_NULL;\r
+ Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;\r
+ EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);\r
+\r
+ //\r
+ // Map F2 to Boot Manager Menu\r
+ //\r
+ F2.ScanCode = SCAN_F2;\r
+ F2.UnicodeChar = CHAR_NULL;\r
+ EfiBootManagerGetBootManagerMenu (&BootOption);\r
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);\r
+\r
+ //\r
+ // Also add Down key to Boot Manager Menu since some serial terminals don't support F2 key.\r
+ //\r
+ Down.ScanCode = SCAN_DOWN;\r
+ Down.UnicodeChar = CHAR_NULL;\r
+ EfiBootManagerGetBootManagerMenu (&BootOption);\r
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL);\r
+\r
+ //\r
+ // Install ready to lock.\r
+ // This needs to be done before option rom dispatched.\r
+ //\r
+ InstallReadyToLock ();\r
+\r
+ //\r
+ // Dispatch deferred images after EndOfDxe event and ReadyToLock installation.\r
+ //\r
+ EfiBootManagerDispatchDeferredImages ();\r
+}\r
+\r
+/**\r
+ Do the platform specific action after the console is connected.\r
+\r
+ Such as:\r
+ Dynamically switch output mode;\r
+ Signal console ready platform customized event;\r
+ Run diagnostics like memory testing;\r
+ Connect certain devices;\r
+ Dispatch additional option roms.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerAfterConsole (\r
+ VOID\r
+)\r
+{\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;\r
+\r
+ Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;\r
+ White.Blue = White.Green = White.Red = White.Reserved = 0xFF;\r
+\r
+ EfiBootManagerConnectAll ();\r
+ EfiBootManagerRefreshAllBootOption ();\r
+\r
+ //\r
+ // Register UEFI Shell\r
+ //\r
+ PlatformRegisterFvBootOption (PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE);\r
+\r
+ Print (\r
+ L"\n"\r
+ L"F2 or Down to enter Boot Manager Menu.\n"\r
+ L"ENTER to boot directly.\n"\r
+ L"\n"\r
+ );\r
+\r
+}\r
+\r
+/**\r
+ This function is called each second during the boot manager waits the timeout.\r
+\r
+ @param TimeoutRemain The remaining timeout.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerWaitCallback (\r
+ UINT16 TimeoutRemain\r
+)\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ The function is called when no boot option could be launched,\r
+ including platform recovery options and options pointing to applications\r
+ built into firmware volumes.\r
+\r
+ If this function returns, BDS attempts to enter an infinite loop.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerUnableToBoot (\r
+ VOID\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
--- /dev/null
+/**@file\r
+ Head file for BDS Platform specific code\r
+\r
+Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#ifndef _PLATFORM_BOOT_MANAGER_H\r
+#define _PLATFORM_BOOT_MANAGER_H\r
+\r
+#include <PiDxe.h>\r
+#include <Protocol/LoadedImage.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiBootManagerLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/BootLogoLib.h>\r
+#include <Protocol/SmmAccess2.h>\r
+\r
+typedef struct {\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ UINTN ConnectType;\r
+} PLATFORM_CONSOLE_CONNECT_ENTRY;\r
+\r
+extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];\r
+\r
+#define gEndEntire \\r
+ { \\r
+ END_DEVICE_PATH_TYPE,\\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\\r
+ { END_DEVICE_PATH_LENGTH, 0 },\\r
+ }\r
+\r
+#define CONSOLE_OUT BIT0\r
+#define CONSOLE_IN BIT1\r
+#define STD_ERROR BIT2\r
+\r
+#define CLASS_HID 3\r
+#define SUBCLASS_BOOT 1\r
+#define PROTOCOL_KEYBOARD 1\r
+\r
+typedef struct {\r
+ USB_CLASS_DEVICE_PATH UsbClass;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} USB_CLASS_FORMAT_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH VendorDevicePath;\r
+ UINT32 Instance;\r
+} WIN_NT_VENDOR_DEVICE_PATH_NODE;\r
+\r
+//\r
+// Below is the platform console device path\r
+//\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH NtBus;\r
+ WIN_NT_VENDOR_DEVICE_PATH_NODE SerialDevice;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEVICE_PATH TerminalType;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} NT_ISA_SERIAL_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH NtBus;\r
+ WIN_NT_VENDOR_DEVICE_PATH_NODE NtGopDevice;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} NT_PLATFORM_GOP_DEVICE_PATH;\r
+\r
+extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath;\r
+\r
+/**\r
+ Use SystemTable Conout to stop video based Simple Text Out consoles from going\r
+ to the video device. Put up LogoFile on every video device that is a console.\r
+\r
+ @param[in] LogoFile File name of logo to display on the center of the screen.\r
+\r
+ @retval EFI_SUCCESS ConsoleControl has been flipped to graphics and logo displayed.\r
+ @retval EFI_UNSUPPORTED Logo not found\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformBootManagerEnableQuietBoot (\r
+ IN EFI_GUID *LogoFile\r
+);\r
+\r
+/**\r
+ Use SystemTable Conout to turn on video based Simple Text Out consoles. The\r
+ Simple Text Out screens will now be synced up with all non video output devices\r
+\r
+ @retval EFI_SUCCESS UGA devices are back in text mode and synced up.\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformBootManagerDisableQuietBoot (\r
+ VOID\r
+);\r
+\r
+/**\r
+ Show progress bar with title above it. It only works in Graphics mode.\r
+\r
+ @param TitleForeground Foreground color for Title.\r
+ @param TitleBackground Background color for Title.\r
+ @param Title Title above progress bar.\r
+ @param ProgressColor Progress bar color.\r
+ @param Progress Progress (0-100)\r
+ @param PreviousValue The previous value of the progress.\r
+\r
+ @retval EFI_STATUS Success update the progress bar\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformBootManagerShowProgress (\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,\r
+ IN CHAR16 *Title,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,\r
+ IN UINTN Progress,\r
+ IN UINTN PreviousValue\r
+);\r
+\r
+#endif // _PLATFORM_BOOT_MANAGER_H\r
--- /dev/null
+## @file\r
+# Include all platform action which can be customized by IBV/OEM.\r
+#\r
+# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformBootManagerLib\r
+ FILE_GUID = F0D9063A-DADB-4185-85E2-D7ACDA93F7A6\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ PlatformData.c\r
+ PlatformConsole.c\r
+ PlatformConsole.h\r
+ PlatformBootManager.c\r
+ PlatformBootManager.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiLib\r
+ UefiBootManagerLib\r
+ PcdLib\r
+ DxeServicesLib\r
+ MemoryAllocationLib\r
+ DevicePathLib\r
+ HiiLib\r
+ PrintLib\r
+ PlatformHookLib\r
+\r
+[Guids]\r
+ gEfiEndOfDxeEventGroupGuid\r
+\r
+[Protocols]\r
+ gEfiGenericMemTestProtocolGuid ## CONSUMES\r
+ gEfiGraphicsOutputProtocolGuid ## CONSUMES\r
+ gEfiUgaDrawProtocolGuid ## CONSUMES\r
+ gEfiBootLogoProtocolGuid ## CONSUMES\r
+ gEfiDxeSmmReadyToLockProtocolGuid\r
+ gEfiSmmAccess2ProtocolGuid\r
+\r
+[Pcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut\r
+ gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdShellFile\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
--- /dev/null
+/** @file\r
+This file include all platform action which can be customized by IBV/OEM.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include "PlatformBootManager.h"\r
+#include "PlatformConsole.h"\r
+\r
+#define PCI_DEVICE_PATH_NODE(Func, Dev) \\r
+ { \\r
+ { \\r
+ HARDWARE_DEVICE_PATH, \\r
+ HW_PCI_DP, \\r
+ { \\r
+ (UINT8) (sizeof (PCI_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \\r
+ } \\r
+ }, \\r
+ (Func), \\r
+ (Dev) \\r
+ }\r
+\r
+#define PNPID_DEVICE_PATH_NODE(PnpId) \\r
+ { \\r
+ { \\r
+ ACPI_DEVICE_PATH, \\r
+ ACPI_DP, \\r
+ { \\r
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \\r
+ }, \\r
+ }, \\r
+ EISA_PNP_ID((PnpId)), \\r
+ 0 \\r
+ }\r
+\r
+#define gPciRootBridge \\r
+ PNPID_DEVICE_PATH_NODE(0x0A03)\r
+\r
+#define gPnp16550ComPort \\r
+ PNPID_DEVICE_PATH_NODE(0x0501)\r
+\r
+#define gUartVendor \\r
+ { \\r
+ { \\r
+ HARDWARE_DEVICE_PATH, \\r
+ HW_VENDOR_DP, \\r
+ { \\r
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
+ } \\r
+ }, \\r
+ {0xD3987D4B, 0x971A, 0x435F, {0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41}} \\r
+ }\r
+\r
+#define gUart \\r
+ { \\r
+ { \\r
+ MESSAGING_DEVICE_PATH, \\r
+ MSG_UART_DP, \\r
+ { \\r
+ (UINT8) (sizeof (UART_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \\r
+ } \\r
+ }, \\r
+ 0, \\r
+ 115200, \\r
+ 8, \\r
+ 1, \\r
+ 1 \\r
+ }\r
+\r
+#define gPcAnsiTerminal \\r
+ { \\r
+ { \\r
+ MESSAGING_DEVICE_PATH, \\r
+ MSG_VENDOR_DP, \\r
+ { \\r
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
+ } \\r
+ }, \\r
+ DEVICE_PATH_MESSAGING_PC_ANSI \\r
+ }\r
+\r
+\r
+ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;\r
+UART_DEVICE_PATH gUartDeviceNode = gUart;\r
+VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal;\r
+VENDOR_DEVICE_PATH gUartDeviceVendorNode = gUartVendor;\r
+\r
+//\r
+// Predefined platform root bridge\r
+//\r
+PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {\r
+ gPciRootBridge,\r
+ gEndEntire\r
+};\r
+\r
+EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = {\r
+ (EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0,\r
+ NULL\r
+};\r
+\r
+BOOLEAN mDetectVgaOnly;\r
+\r
+/**\r
+ Add UART to ConOut, ConIn, ErrOut.\r
+\r
+ @param[in] DeviceHandle - LPC device path.\r
+\r
+ @retval EFI_SUCCESS - Serial console is added to ConOut, ConIn, and ErrOut.\r
+ @retval EFI_STATUS - No serial console is added.\r
+**/\r
+EFI_STATUS\r
+PrepareLpcBridgeDevicePath (\r
+ IN EFI_HANDLE DeviceHandle\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ DevicePath = NULL;\r
+ Status = gBS->HandleProtocol (\r
+ DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID*)&DevicePath\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Register COM1\r
+ //\r
+ DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceVendorNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);\r
+\r
+ EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);\r
+ EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);\r
+ EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Return the GOP device path in the platform.\r
+\r
+ @param[in] PciDevicePath - Device path for the PCI graphics device.\r
+ @param[out] GopDevicePath - Return the device path with GOP installed.\r
+\r
+ @retval EFI_SUCCESS - PCI VGA is added to ConOut.\r
+ @retval EFI_INVALID_PARAMETER - The device path parameter is invalid.\r
+ @retval EFI_STATUS - No GOP device found.\r
+**/\r
+EFI_STATUS\r
+GetGopDevicePath (\r
+ IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,\r
+ OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath\r
+)\r
+{\r
+ UINTN Index;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE PciDeviceHandle;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;\r
+ UINTN GopHandleCount;\r
+ EFI_HANDLE *GopHandleBuffer;\r
+\r
+ if (PciDevicePath == NULL || GopDevicePath == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Initialize the GopDevicePath to be PciDevicePath\r
+ //\r
+ *GopDevicePath = PciDevicePath;\r
+ TempPciDevicePath = PciDevicePath;\r
+\r
+ Status = gBS->LocateDevicePath (\r
+ &gEfiDevicePathProtocolGuid,\r
+ &TempPciDevicePath,\r
+ &PciDeviceHandle\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE);\r
+\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiGraphicsOutputProtocolGuid,\r
+ NULL,\r
+ &GopHandleCount,\r
+ &GopHandleBuffer\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Add all the child handles as possible Console Device\r
+ //\r
+ for (Index = 0; Index < GopHandleCount; Index++) {\r
+ Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath);\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+ if (CompareMem (\r
+ PciDevicePath,\r
+ TempDevicePath,\r
+ GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH\r
+ ) == 0) {\r
+ //\r
+ // In current implementation, we only enable one of the child handles\r
+ // as console device, i.e. sotre one of the child handle's device\r
+ // path to variable "ConOut"\r
+ // In future, we could select all child handles to be console device\r
+ //\r
+ *GopDevicePath = TempDevicePath;\r
+\r
+ //\r
+ // Delete the PCI device's path that added by GetPlugInPciVgaDevicePath()\r
+ // Add the integrity GOP device path.\r
+ //\r
+ EfiBootManagerUpdateConsoleVariable (ConOut, NULL, PciDevicePath);\r
+ EfiBootManagerUpdateConsoleVariable (ConOut, TempDevicePath, NULL);\r
+ }\r
+ }\r
+ gBS->FreePool (GopHandleBuffer);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Add PCI VGA to ConOut, ConIn, ErrOut.\r
+\r
+ @param[in] DeviceHandle - Handle of PciIo protocol.\r
+\r
+ @retval EFI_SUCCESS - PCI VGA is added to ConOut.\r
+ @retval EFI_STATUS - No PCI VGA device is added.\r
+\r
+**/\r
+EFI_STATUS\r
+PreparePciVgaDevicePath (\r
+ IN EFI_HANDLE DeviceHandle\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;\r
+\r
+ DevicePath = NULL;\r
+ Status = gBS->HandleProtocol (\r
+ DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID*)&DevicePath\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ GetGopDevicePath (DevicePath, &GopDevicePath);\r
+ DevicePath = GopDevicePath;\r
+\r
+ EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Add PCI Serial to ConOut, ConIn, ErrOut.\r
+\r
+ @param[in] DeviceHandle - Handle of PciIo protocol.\r
+\r
+ @retval EFI_SUCCESS - PCI Serial is added to ConOut, ConIn, and ErrOut.\r
+ @retval EFI_STATUS - No PCI Serial device is added.\r
+\r
+**/\r
+EFI_STATUS\r
+PreparePciSerialDevicePath (\r
+ IN EFI_HANDLE DeviceHandle\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ DevicePath = NULL;\r
+ Status = gBS->HandleProtocol (\r
+ DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID*)&DevicePath\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);\r
+\r
+ EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);\r
+ EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);\r
+ EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ For every PCI instance execute a callback function.\r
+\r
+ @param[in] Id - The protocol GUID for callback\r
+ @param[in] CallBackFunction - The callback function\r
+ @param[in] Context - The context of the callback\r
+\r
+ @retval EFI_STATUS - Callback function failed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+VisitAllInstancesOfProtocol (\r
+ IN EFI_GUID *Id,\r
+ IN PROTOCOL_INSTANCE_CALLBACK CallBackFunction,\r
+ IN VOID *Context\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN Index;\r
+ VOID *Instance;\r
+\r
+ //\r
+ // Start to check all the PciIo to find all possible device\r
+ //\r
+ HandleCount = 0;\r
+ HandleBuffer = NULL;\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ Id,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ for (Index = 0; Index < HandleCount; Index++) {\r
+ Status = gBS->HandleProtocol (HandleBuffer[Index], Id, &Instance);\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+\r
+ Status = (*CallBackFunction) (\r
+ HandleBuffer[Index],\r
+ Instance,\r
+ Context\r
+ );\r
+ }\r
+\r
+ gBS->FreePool (HandleBuffer);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ For every PCI instance execute a callback function.\r
+\r
+ @param[in] Handle - The PCI device handle\r
+ @param[in] Instance - The instance of the PciIo protocol\r
+ @param[in] Context - The context of the callback\r
+\r
+ @retval EFI_STATUS - Callback function failed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+VisitingAPciInstance (\r
+ IN EFI_HANDLE Handle,\r
+ IN VOID *Instance,\r
+ IN VOID *Context\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE00 Pci;\r
+\r
+ PciIo = (EFI_PCI_IO_PROTOCOL*) Instance;\r
+\r
+ //\r
+ // Check for all PCI device\r
+ //\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0,\r
+ sizeof (Pci) / sizeof (UINT32),\r
+ &Pci\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ return (*(VISIT_PCI_INSTANCE_CALLBACK)(UINTN) Context) (\r
+ Handle,\r
+ PciIo,\r
+ &Pci\r
+ );\r
+\r
+}\r
+\r
+\r
+/**\r
+ For every PCI instance execute a callback function.\r
+\r
+ @param[in] CallBackFunction - Callback function pointer\r
+\r
+ @retval EFI_STATUS - Callback function failed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+VisitAllPciInstances (\r
+ IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction\r
+)\r
+{\r
+ return VisitAllInstancesOfProtocol (\r
+ &gEfiPciIoProtocolGuid,\r
+ VisitingAPciInstance,\r
+ (VOID*)(UINTN) CallBackFunction\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ Do platform specific PCI Device check and add them to\r
+ ConOut, ConIn, ErrOut.\r
+\r
+ @param[in] Handle - Handle of PCI device instance\r
+ @param[in] PciIo - PCI IO protocol instance\r
+ @param[in] Pci - PCI Header register block\r
+\r
+ @retval EFI_SUCCESS - PCI Device check and Console variable update successfully.\r
+ @retval EFI_STATUS - PCI Device check or Console variable update fail.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DetectAndPreparePlatformPciDevicePath (\r
+ IN EFI_HANDLE Handle,\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN PCI_TYPE00 *Pci\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ EFI_PCI_DEVICE_ENABLE,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (!mDetectVgaOnly) {\r
+ //\r
+ // Here we decide whether it is LPC Bridge\r
+ //\r
+ if ((IS_PCI_LPC (Pci)) ||\r
+ ((IS_PCI_ISA_PDECODE (Pci)) &&\r
+ (Pci->Hdr.VendorId == 0x8086)\r
+ )\r
+ ) {\r
+ //\r
+ // Add IsaKeyboard to ConIn,\r
+ // add IsaSerial to ConOut, ConIn, ErrOut\r
+ //\r
+ DEBUG ((DEBUG_INFO, "Found LPC Bridge device\n"));\r
+ PrepareLpcBridgeDevicePath (Handle);\r
+ return EFI_SUCCESS;\r
+ }\r
+ //\r
+ // Here we decide which Serial device to enable in PCI bus\r
+ //\r
+ if (IS_PCI_16550SERIAL (Pci)) {\r
+ //\r
+ // Add them to ConOut, ConIn, ErrOut.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "Found PCI 16550 SERIAL device\n"));\r
+ PreparePciSerialDevicePath (Handle);\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Here we decide which VGA device to enable in PCI bus\r
+ //\r
+ if (IS_PCI_VGA (Pci)) {\r
+ //\r
+ // Add them to ConOut.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "Found PCI VGA device\n"));\r
+ PreparePciVgaDevicePath (Handle);\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut\r
+\r
+ @param[in] DetectVgaOnly - Only detect VGA device if it's TRUE.\r
+\r
+ @retval EFI_SUCCESS - PCI Device check and Console variable update successfully.\r
+ @retval EFI_STATUS - PCI Device check or Console variable update fail.\r
+\r
+**/\r
+EFI_STATUS\r
+DetectAndPreparePlatformPciDevicePaths (\r
+ BOOLEAN DetectVgaOnly\r
+)\r
+{\r
+ mDetectVgaOnly = DetectVgaOnly;\r
+\r
+ EfiBootManagerUpdateConsoleVariable (\r
+ ConIn,\r
+ (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath,\r
+ NULL\r
+ );\r
+\r
+ return VisitAllPciInstances (DetectAndPreparePlatformPciDevicePath);\r
+}\r
+\r
+\r
+/**\r
+ The function will connect root bridge\r
+\r
+ @return EFI_SUCCESS Connect RootBridge successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+ConnectRootBridge (\r
+ VOID\r
+)\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE RootHandle;\r
+\r
+ //\r
+ // Make all the PCI_IO protocols on PCI Seg 0 show up\r
+ //\r
+ Status = gBS->LocateDevicePath (\r
+ &gEfiDevicePathProtocolGuid,\r
+ &gPlatformRootBridges[0],\r
+ &RootHandle\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = gBS->ConnectController (RootHandle, NULL, NULL, FALSE);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Platform console init. Include the platform firmware vendor, revision\r
+ and so crc check.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformConsoleInit (\r
+ VOID\r
+)\r
+{\r
+ gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);\r
+ gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);\r
+ gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity);\r
+ gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);\r
+\r
+ ConnectRootBridge ();\r
+\r
+ //\r
+ // Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut\r
+ //\r
+ DetectAndPreparePlatformPciDevicePaths (FALSE);\r
+\r
+}\r
--- /dev/null
+/** @file\r
+Head file for BDS Platform specific code\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#ifndef _PLATFORM_CONSOLE_H\r
+#define _PLATFORM_CONSOLE_H\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Pci.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Protocol/PciIo.h>\r
+\r
+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)\r
+#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+\r
+//\r
+// Type definitions\r
+//\r
+\r
+//\r
+// Platform Root Bridge\r
+//\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PROTOCOL_INSTANCE_CALLBACK)(\r
+ IN EFI_HANDLE Handle,\r
+ IN VOID *Instance,\r
+ IN VOID *Context\r
+);\r
+\r
+/**\r
+ @param[in] Handle - Handle of PCI device instance\r
+ @param[in] PciIo - PCI IO protocol instance\r
+ @param[in] Pci - PCI Header register block\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *VISIT_PCI_INSTANCE_CALLBACK)(\r
+ IN EFI_HANDLE Handle,\r
+ IN EFI_PCI_IO_PROTOCOL *PciIo,\r
+ IN PCI_TYPE00 *Pci\r
+);\r
+\r
+/**\r
+ Platform console init. Include the platform firmware vendor, revision\r
+ and so crc check.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformConsoleInit (\r
+ VOID\r
+);\r
+\r
+#endif\r
--- /dev/null
+/**@file\r
+ Defined the platform specific device path which will be filled to\r
+ ConIn/ConOut variables.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#include "PlatformBootManager.h"\r
+\r
+///\r
+/// Predefined platform default console device path\r
+///\r
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {\r
+ {\r
+ NULL,\r
+ 0\r
+ }\r
+};\r
+\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_USB_CLASS_DP,\r
+ {\r
+ (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)),\r
+ (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ 0xffff, // VendorId\r
+ 0xffff, // ProductId\r
+ CLASS_HID, // DeviceClass\r
+ SUBCLASS_BOOT, // DeviceSubClass\r
+ PROTOCOL_KEYBOARD // DeviceProtocol\r
+ },\r
+ gEndEntire\r
+};\r
--- /dev/null
+/** @file\r
+ Platform Hook Library instance for UART device.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+#include <Uefi/UefiBaseType.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PlatformHookLib.h>\r
+#include <Library/BlParseLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+typedef struct {\r
+ UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ UINT64 Offset; ///< The byte offset into to the BAR\r
+ UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ UINT8 Reserved[2];\r
+} PCI_SERIAL_PARAMETER;\r
+\r
+/**\r
+ Performs platform specific initialization required for the CPU to access\r
+ the hardware associated with a SerialPortLib instance. This function does\r
+ not initialize the serial port hardware itself. Instead, it initializes\r
+ hardware devices that are required for the CPU to access the serial port\r
+ hardware. This function may be called more than once.\r
+\r
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.\r
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PlatformHookSerialPortInitialize (\r
+ VOID\r
+ )\r
+{\r
+ RETURN_STATUS Status;\r
+ UINT32 DeviceVendor;\r
+ PCI_SERIAL_PARAMETER *SerialParam;\r
+ SERIAL_PORT_INFO SerialPortInfo;\r
+\r
+ Status = ParseSerialInfo (&SerialPortInfo);\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if (SerialPortInfo.Type == PLD_SERIAL_TYPE_MEMORY_MAPPED) {\r
+ Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);\r
+ } else { //IO\r
+ Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);\r
+ }\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ Status = PcdSet64S (PcdSerialRegisterBase, SerialPortInfo.BaseAddr);\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = PcdSet32S (PcdSerialRegisterStride, SerialPortInfo.RegWidth);\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = PcdSet32S (PcdSerialBaudRate, SerialPortInfo.Baud);\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);\r
+ if (RETURN_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if (SerialPortInfo.UartPciAddr >= 0x80000000) {\r
+ DeviceVendor = PciRead32 (SerialPortInfo.UartPciAddr & 0x0ffff000);\r
+ SerialParam = PcdGetPtr(PcdPciSerialParameters);\r
+ SerialParam->VendorId = (UINT16)DeviceVendor;\r
+ SerialParam->DeviceId = DeviceVendor >> 16;\r
+ SerialParam->ClockRate = SerialPortInfo.InputHertz;\r
+ SerialParam->RegisterStride = (UINT8)SerialPortInfo.RegWidth;\r
+ }\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Platform Hook Library instance for UART device.\r
+#\r
+# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformHookLib\r
+ FILE_GUID = 40A2CBC6-CFB8-447b-A90E-198E88FD345E\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformHookLib\r
+ CONSTRUCTOR = PlatformHookSerialPortInitialize\r
+\r
+[Sources]\r
+ PlatformHookLib.c\r
+\r
+[LibraryClasses]\r
+ BlParseLib\r
+ PcdLib\r
+ PciLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES\r
--- /dev/null
+/** @file\r
+ Include all platform specific features which can be customized by IBV/OEM.\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PlatformSupportLib.h>\r
+\r
+/**\r
+ Parse platform specific information from coreboot.\r
+\r
+ @retval RETURN_SUCCESS The platform specific coreboot support succeeded.\r
+ @retval RETURN_DEVICE_ERROR The platform specific coreboot support could not be completed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ParsePlatformInfo (\r
+ VOID\r
+ )\r
+{\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# Include all platform specific features which can be customized by IBV/OEM.\r
+#\r
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformSupportLib\r
+ FILE_GUID = B42AA265-00CA-4d4b-AC14-DBD5268E1BC7\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformSupportLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ PlatformSupportLibNull.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
--- /dev/null
+/** @file\r
+ Reset System Library functions for bootloader\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Guid/AcpiBoardInfoGuid.h>\r
+\r
+ACPI_BOARD_INFO mAcpiBoardInfo;\r
+\r
+/**\r
+ The constructor function to initialize mAcpiBoardInfo.\r
+\r
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ResetSystemLibConstructor (\r
+ VOID\r
+ )\r
+{\r
+ EFI_HOB_GUID_TYPE *GuidHob;\r
+ ACPI_BOARD_INFO *AcpiBoardInfoPtr;\r
+\r
+ //\r
+ // Find the acpi board information guid hob\r
+ //\r
+ GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);\r
+ ASSERT (GuidHob != NULL);\r
+\r
+ AcpiBoardInfoPtr = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);\r
+ CopyMem (&mAcpiBoardInfo, AcpiBoardInfoPtr, sizeof (ACPI_BOARD_INFO));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+VOID\r
+AcpiPmControl (\r
+ UINTN SuspendType\r
+ )\r
+{\r
+ UINTN PmCtrlReg;\r
+\r
+ ASSERT (SuspendType <= 7);\r
+\r
+ PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;\r
+ IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (SuspendType << 10));\r
+ IoOr16 (PmCtrlReg, BIT13);\r
+ CpuDeadLoop ();\r
+}\r
+\r
+/**\r
+ Calling this function causes a system-wide reset. This sets\r
+ all circuitry within the system to its initial state. This type of reset\r
+ is asynchronous to system operation and operates without regard to\r
+ cycle boundaries.\r
+\r
+ System reset should not return, if it returns, it means the system does\r
+ not support cold reset.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetCold (\r
+ VOID\r
+ )\r
+{\r
+ IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);\r
+ CpuDeadLoop ();\r
+}\r
+\r
+/**\r
+ Calling this function causes a system-wide initialization. The processors\r
+ are set to their initial state, and pending cycles are not corrupted.\r
+\r
+ System reset should not return, if it returns, it means the system does\r
+ not support warm reset.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetWarm (\r
+ VOID\r
+ )\r
+{\r
+ IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);\r
+ CpuDeadLoop ();\r
+}\r
+\r
+/**\r
+ Calling this function causes the system to enter a power state equivalent\r
+ to the ACPI G2/S5 or G3 states.\r
+\r
+ System shutdown should not return, if it returns, it means the system does\r
+ not support shut down reset.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetShutdown (\r
+ VOID\r
+ )\r
+{\r
+ UINTN PmCtrlReg;\r
+\r
+ //\r
+ // GPE0_EN should be disabled to avoid any GPI waking up the system from S5\r
+ //\r
+ IoWrite16 ((UINTN)mAcpiBoardInfo.PmGpeEnBase, 0);\r
+\r
+ //\r
+ // Clear Power Button Status\r
+ //\r
+ IoWrite16((UINTN) mAcpiBoardInfo.PmEvtBase, BIT8);\r
+\r
+ //\r
+ // Transform system into S5 sleep state\r
+ //\r
+ PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;\r
+ IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (7 << 10));\r
+ IoOr16 (PmCtrlReg, BIT13);\r
+ CpuDeadLoop ();\r
+\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ Calling this function causes the system to enter a power state for capsule\r
+ update.\r
+\r
+ Reset update should not return, if it returns, it means the system does\r
+ not support capsule update.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnterS3WithImmediateWake (\r
+ VOID\r
+ )\r
+{\r
+ AcpiPmControl (5);\r
+ ASSERT (FALSE);\r
+}\r
+\r
+/**\r
+ This function causes a systemwide reset. The exact type of the reset is\r
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed\r
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData\r
+ the platform must pick a supported reset type to perform.The platform may\r
+ optionally log the parameters from any non-normal reset that occurs.\r
+\r
+ @param[in] DataSize The size, in bytes, of ResetData.\r
+ @param[in] ResetData The data buffer starts with a Null-terminated string,\r
+ followed by the EFI_GUID.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetPlatformSpecific (\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData\r
+ )\r
+{\r
+ ResetCold ();\r
+}\r
--- /dev/null
+## @file\r
+# Library instance for ResetSystem library class for bootloader\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ResetSystemLib\r
+ FILE_GUID = C5CD4EEE-527F-47df-9C92-B41414AF7479\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ResetSystemLib\r
+\r
+ CONSTRUCTOR = ResetSystemLibConstructor\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ ResetSystemLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ IoLib\r
+ HobLib\r
+ BaseMemoryLib\r
+\r
+[Guids]\r
+ gUefiAcpiBoardInfoGuid\r
+\r
--- /dev/null
+/** @file\r
+ This library will parse the Slim Bootloader to get required information.\r
+\r
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BlParseLib.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+\r
+/**\r
+ This function retrieves the parameter base address from boot loader.\r
+\r
+ This function will get bootloader specific parameter address for UEFI payload.\r
+ e.g. HobList pointer for Slim Bootloader, and coreboot table header for Coreboot.\r
+\r
+ @retval NULL Failed to find the GUID HOB.\r
+ @retval others GUIDed HOB data pointer.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+GetParameterBase (\r
+ VOID\r
+ )\r
+{\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HandoffTable;\r
+\r
+ HandoffTable = (EFI_HOB_HANDOFF_INFO_TABLE *)(UINTN) GET_BOOTLOADER_PARAMETER ();\r
+ if ((HandoffTable->Header.HobType == EFI_HOB_TYPE_HANDOFF) &&\r
+ (HandoffTable->Header.HobLength == sizeof (EFI_HOB_HANDOFF_INFO_TABLE)) &&\r
+ (HandoffTable->Header.Reserved == 0)) {\r
+ return (VOID *)HandoffTable;\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+\r
+/**\r
+ This function retrieves a GUIDed HOB data from Slim Bootloader.\r
+\r
+ This function will search SBL HOB list to find the first GUIDed HOB that\r
+ its GUID matches Guid.\r
+\r
+ @param[in] Guid A pointer to HOB GUID to search.\r
+\r
+ @retval NULL Failed to find the GUID HOB.\r
+ @retval others GUIDed HOB data pointer.\r
+\r
+**/\r
+VOID *\r
+GetGuidHobDataFromSbl (\r
+ IN EFI_GUID *Guid\r
+ )\r
+{\r
+ UINT8 *GuidHob;\r
+ CONST VOID *HobList;\r
+\r
+ HobList = GetParameterBase ();\r
+ ASSERT (HobList != NULL);\r
+ GuidHob = GetNextGuidHob (Guid, HobList);\r
+ if (GuidHob != NULL) {\r
+ return GET_GUID_HOB_DATA (GuidHob);\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ Acquire the memory map information.\r
+\r
+ @param MemInfoCallback The callback routine\r
+ @param Params Pointer to the callback routine parameter\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the memory information.\r
+ @retval RETURN_NOT_FOUND Failed to find the memory information.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseMemoryInfo (\r
+ IN BL_MEM_INFO_CALLBACK MemInfoCallback,\r
+ IN VOID *Params\r
+ )\r
+{\r
+ MEMROY_MAP_INFO *MemoryMapInfo;\r
+ UINTN Idx;\r
+\r
+ MemoryMapInfo = (MEMROY_MAP_INFO *) GetGuidHobDataFromSbl (&gLoaderMemoryMapInfoGuid);\r
+ if (MemoryMapInfo == NULL) {\r
+ ASSERT (FALSE);\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ for (Idx = 0; Idx < MemoryMapInfo->Count; Idx++) {\r
+ MemInfoCallback (&MemoryMapInfo->Entry[Idx], Params);\r
+ }\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Acquire acpi table and smbios table from slim bootloader\r
+\r
+ @param SystemTableInfo Pointer to the system table info\r
+\r
+ @retval RETURN_SUCCESS Successfully find out the tables.\r
+ @retval RETURN_NOT_FOUND Failed to find the tables.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseSystemTable (\r
+ OUT SYSTEM_TABLE_INFO *SystemTableInfo\r
+ )\r
+{\r
+ SYSTEM_TABLE_INFO *TableInfo;\r
+\r
+ TableInfo = (SYSTEM_TABLE_INFO *)GetGuidHobDataFromSbl (&gUefiSystemTableInfoGuid);\r
+ if (TableInfo == NULL) {\r
+ ASSERT (FALSE);\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ CopyMem (SystemTableInfo, TableInfo, sizeof (SYSTEM_TABLE_INFO));\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Find the serial port information\r
+\r
+ @param SERIAL_PORT_INFO Pointer to serial port info structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the serial port information.\r
+ @retval RETURN_NOT_FOUND Failed to find the serial port information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseSerialInfo (\r
+ OUT SERIAL_PORT_INFO *SerialPortInfo\r
+ )\r
+{\r
+ SERIAL_PORT_INFO *BlSerialInfo;\r
+\r
+ BlSerialInfo = (SERIAL_PORT_INFO *) GetGuidHobDataFromSbl (&gUefiSerialPortInfoGuid);\r
+ if (BlSerialInfo == NULL) {\r
+ ASSERT (FALSE);\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ CopyMem (SerialPortInfo, BlSerialInfo, sizeof (SERIAL_PORT_INFO));\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Find the video frame buffer information\r
+\r
+ @param GfxInfo Pointer to the EFI_PEI_GRAPHICS_INFO_HOB structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the video frame buffer information.\r
+ @retval RETURN_NOT_FOUND Failed to find the video frame buffer information .\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseGfxInfo (\r
+ OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo\r
+ )\r
+{\r
+ EFI_PEI_GRAPHICS_INFO_HOB *BlGfxInfo;\r
+\r
+ BlGfxInfo = (EFI_PEI_GRAPHICS_INFO_HOB *) GetGuidHobDataFromSbl (&gEfiGraphicsInfoHobGuid);\r
+ if (BlGfxInfo == NULL) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ CopyMem (GfxInfo, BlGfxInfo, sizeof (EFI_PEI_GRAPHICS_INFO_HOB));\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Find the video frame buffer device information\r
+\r
+ @param GfxDeviceInfo Pointer to the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB structure\r
+\r
+ @retval RETURN_SUCCESS Successfully find the video frame buffer information.\r
+ @retval RETURN_NOT_FOUND Failed to find the video frame buffer information.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+ParseGfxDeviceInfo (\r
+ OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo\r
+ )\r
+{\r
+ EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *BlGfxDeviceInfo;\r
+\r
+ BlGfxDeviceInfo = (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *) GetGuidHobDataFromSbl (&gEfiGraphicsDeviceInfoHobGuid);\r
+ if (BlGfxDeviceInfo == NULL) {\r
+ return RETURN_NOT_FOUND;\r
+ }\r
+\r
+ CopyMem (GfxDeviceInfo, BlGfxDeviceInfo, sizeof (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB));\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# Slim Bootloader parse library.\r
+#\r
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SblParseLib\r
+ FILE_GUID = DE6FB32C-52CF-4A17-A84C-B323653CB5E0\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = BlParseLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ SblParseLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ PcdLib\r
+ HobLib\r
+\r
+[Guids]\r
+ gUefiSystemTableInfoGuid\r
+ gUefiSerialPortInfoGuid\r
+ gLoaderMemoryMapInfoGuid\r
+ gEfiGraphicsInfoHobGuid\r
+ gEfiGraphicsDeviceInfoHobGuid\r
+\r
+[Pcd]\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadStackTop\r
--- /dev/null
+/** @file\r
+ Locate the entry point for the PEI Core\r
+\r
+Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+\r
+#include "SecMain.h"\r
+\r
+/**\r
+ Find core image base.\r
+\r
+ @param BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param SecCoreImageBase The base address of the SEC core image.\r
+ @param PeiCoreImageBase The base address of the PEI core image.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FindImageBase (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,\r
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase\r
+ )\r
+{\r
+ EFI_PHYSICAL_ADDRESS CurrentAddress;\r
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;\r
+ EFI_FFS_FILE_HEADER *File;\r
+ UINT32 Size;\r
+ EFI_PHYSICAL_ADDRESS EndOfFile;\r
+ EFI_COMMON_SECTION_HEADER *Section;\r
+ EFI_PHYSICAL_ADDRESS EndOfSection;\r
+\r
+ *SecCoreImageBase = 0;\r
+ *PeiCoreImageBase = 0;\r
+\r
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;\r
+ EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;\r
+\r
+ //\r
+ // Loop through the FFS files in the Boot Firmware Volume\r
+ //\r
+ for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {\r
+\r
+ CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;\r
+ if (CurrentAddress > EndOfFirmwareVolume) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;\r
+ if (IS_FFS_FILE2 (File)) {\r
+ Size = FFS_FILE2_SIZE (File);\r
+ if (Size <= 0x00FFFFFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ } else {\r
+ Size = FFS_FILE_SIZE (File);\r
+ if (Size < sizeof (EFI_FFS_FILE_HEADER)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ EndOfFile = CurrentAddress + Size;\r
+ if (EndOfFile > EndOfFirmwareVolume) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Look for SEC Core / PEI Core files\r
+ //\r
+ if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&\r
+ File->Type != EFI_FV_FILETYPE_PEI_CORE) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Loop through the FFS file sections within the FFS file\r
+ //\r
+ if (IS_FFS_FILE2 (File)) {\r
+ EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));\r
+ } else {\r
+ EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));\r
+ }\r
+ for (;;) {\r
+ CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;\r
+ Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;\r
+\r
+ if (IS_SECTION2 (Section)) {\r
+ Size = SECTION2_SIZE (Section);\r
+ if (Size <= 0x00FFFFFF) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ } else {\r
+ Size = SECTION_SIZE (Section);\r
+ if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+\r
+ EndOfSection = CurrentAddress + Size;\r
+ if (EndOfSection > EndOfFile) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ //\r
+ // Look for executable sections\r
+ //\r
+ if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {\r
+ if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {\r
+ if (IS_SECTION2 (Section)) {\r
+ *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+ } else {\r
+ *SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+ }\r
+ } else {\r
+ if (IS_SECTION2 (Section)) {\r
+ *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+ } else {\r
+ *PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+ }\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Both SEC Core and PEI Core images found\r
+ //\r
+ if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Find and return Pei Core entry point.\r
+\r
+ It also find SEC and PEI Core file debug information. It will report them if\r
+ remote debug is enabled.\r
+\r
+ @param BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param PeiCoreEntryPoint The entry point of the PEI core.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS SecCoreImageBase;\r
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+\r
+ //\r
+ // Find SEC Core and PEI Core image base\r
+ //\r
+ Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
+ //\r
+ // Report SEC Core debug information when remote debug is enabled\r
+ //\r
+ ImageContext.ImageAddress = SecCoreImageBase;\r
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+ //\r
+ // Report PEI Core debug information when remote debug is enabled\r
+ //\r
+ ImageContext.ImageAddress = PeiCoreImageBase;\r
+ ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+ PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
+\r
+ //\r
+ // Find PEI Core entry point\r
+ //\r
+ Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);\r
+ if (EFI_ERROR (Status)) {\r
+ *PeiCoreEntryPoint = 0;\r
+ }\r
+\r
+ return;\r
+}\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Abstract:\r
+;\r
+; Entry point for the coreboot UEFI payload.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+SECTION .text\r
+\r
+; C Functions\r
+extern ASM_PFX(SecStartup)\r
+\r
+; Pcds\r
+extern ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))\r
+extern ASM_PFX(PcdGet32 (PcdPayloadStackTop))\r
+\r
+;\r
+; SecCore Entry Point\r
+;\r
+; Processor is in flat protected mode\r
+;\r
+; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test)\r
+; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor\r
+; @param[in] EBP Pointer to the start of the Boot Firmware Volume\r
+;\r
+; @return None This routine does not return\r
+;\r
+global ASM_PFX(_ModuleEntryPoint)\r
+ASM_PFX(_ModuleEntryPoint):\r
+ ;\r
+ ; Disable all the interrupts\r
+ ;\r
+ cli\r
+\r
+ ;\r
+ ; Save the Payload HOB base address before switching the stack\r
+ ;\r
+ mov eax, [esp + 4]\r
+\r
+ ;\r
+ ; Construct the temporary memory at 0x80000, length 0x10000\r
+ ;\r
+ mov esp, DWORD [ASM_PFX(PcdGet32 (PcdPayloadStackTop))]\r
+\r
+ ;\r
+ ; Push the Payload HOB base address onto new stack\r
+ ;\r
+ push eax\r
+\r
+ ;\r
+ ; Pass BFV into the PEI Core\r
+ ;\r
+ push DWORD [ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))]\r
+\r
+ ;\r
+ ; Pass stack base into the PEI Core\r
+ ;\r
+ push BASE_512KB\r
+\r
+ ;\r
+ ; Pass stack size into the PEI Core\r
+ ;\r
+ push SIZE_64KB\r
+\r
+ ;\r
+ ; Pass Control into the PEI Core\r
+ ;\r
+ call ASM_PFX(SecStartup)\r
+\r
+ ;\r
+ ; Should never return\r
+ ;\r
+ jmp $\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+; Abstract:\r
+;\r
+; Switch the stack from temporary memory to permanent memory.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+SECTION .text\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; SecSwitchStack (\r
+; UINT32 TemporaryMemoryBase,\r
+; UINT32 PermenentMemoryBase\r
+; );\r
+;------------------------------------------------------------------------------\r
+global ASM_PFX(SecSwitchStack)\r
+ASM_PFX(SecSwitchStack):\r
+ ;\r
+ ; Save three register: eax, ebx, ecx\r
+ ;\r
+ push eax\r
+ push ebx\r
+ push ecx\r
+ push edx\r
+\r
+ ;\r
+ ; !!CAUTION!! this function address's is pushed into stack after\r
+ ; migration of whole temporary memory, so need save it to permanent\r
+ ; memory at first!\r
+ ;\r
+\r
+ mov ebx, [esp + 20] ; Save the first parameter\r
+ mov ecx, [esp + 24] ; Save the second parameter\r
+\r
+ ;\r
+ ; Save this function's return address into permanent memory at first.\r
+ ; Then, Fixup the esp point to permanent memory\r
+ ;\r
+ mov eax, esp\r
+ sub eax, ebx\r
+ add eax, ecx\r
+ mov edx, [esp] ; copy pushed register's value to permanent memory\r
+ mov [eax], edx\r
+ mov edx, [esp + 4]\r
+ mov [eax + 4], edx\r
+ mov edx, [esp + 8]\r
+ mov [eax + 8], edx\r
+ mov edx, [esp + 12]\r
+ mov [eax + 12], edx\r
+ mov edx, [esp + 16] ; Update return address into permanent memory\r
+ mov [eax + 16], edx\r
+ mov esp, eax ; From now, esp is pointed to permanent memory\r
+\r
+ ;\r
+ ; Fixup the ebp point to permanent memory\r
+ ;\r
+ mov eax, ebp\r
+ sub eax, ebx\r
+ add eax, ecx\r
+ mov ebp, eax ; From now, ebp is pointed to permanent memory\r
+\r
+ pop edx\r
+ pop ecx\r
+ pop ebx\r
+ pop eax\r
+ ret\r
--- /dev/null
+## @file\r
+# This is the first module taking control from the coreboot.\r
+#\r
+# Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SecCore\r
+ FILE_GUID = BA7BE337-6CFB-4dbb-B26C-21EC2FC16073\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ SecMain.c\r
+ SecMain.h\r
+ FindPeiCore.c\r
+\r
+[Sources.IA32]\r
+ Ia32/Stack.nasm\r
+ Ia32/SecEntry.nasm\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ UefiPayloadPkg/UefiPayloadPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseMemoryLib\r
+ DebugLib\r
+ BaseLib\r
+ PcdLib\r
+ DebugAgentLib\r
+ UefiCpuLib\r
+ PeCoffGetEntryPointLib\r
+ PeCoffExtraActionLib\r
+\r
+[Ppis]\r
+ gEfiSecPlatformInformationPpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPayLoadHobBasePpiGuid # PPI ALWAYS_PRODUCED\r
+\r
+[Pcd]\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemBase\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemSize\r
+ gUefiPayloadPkgTokenSpaceGuid.PcdPayloadStackTop\r
--- /dev/null
+/** @file\r
+ C functions in SEC\r
+\r
+Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+\r
+#include "SecMain.h"\r
+\r
+EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {\r
+ SecTemporaryRamSupport\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {\r
+ {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiTemporaryRamSupportPpiGuid,\r
+ &gSecTemporaryRamSupportPpi\r
+ }\r
+};\r
+\r
+//\r
+// These are IDT entries pointing to 10:FFFFFFE4h.\r
+//\r
+UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;\r
+\r
+/**\r
+ Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] Context The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+ IN VOID *Context\r
+ );\r
+\r
+\r
+/**\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+\r
+ @param SizeOfRam Size of the temporary memory available for use.\r
+ @param TempRamBase Base address of temporary ram\r
+ @param BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+ @param BootloaderParameter A parameter from bootloader, e.g. HobList from SlimBootloader\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume,\r
+ IN UINT32 BootloaderParameter\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ SEC_IDT_TABLE IdtTableInStack;\r
+ UINT32 Index;\r
+ UINT32 PeiStackSize;\r
+\r
+ PeiStackSize = (SizeOfRam >> 1);\r
+\r
+ ASSERT (PeiStackSize < SizeOfRam);\r
+\r
+ //\r
+ // Process all libraries constructor function linked to SecCore.\r
+ //\r
+ ProcessLibraryConstructorList ();\r
+\r
+ //\r
+ // Initialize floating point operating environment\r
+ // to be compliant with UEFI spec.\r
+ //\r
+ InitializeFloatingPointUnits ();\r
+\r
+\r
+ // |-------------------|---->\r
+ // |Idt Table |\r
+ // |-------------------|\r
+ // |PeiService Pointer | PeiStackSize\r
+ // |-------------------|\r
+ // | |\r
+ // | Stack |\r
+ // |-------------------|---->\r
+ // | |\r
+ // | |\r
+ // | Heap | PeiTemporaryRamSize\r
+ // | |\r
+ // | |\r
+ // |-------------------|----> TempRamBase\r
+\r
+ IdtTableInStack.PeiService = 0;\r
+ for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {\r
+ CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));\r
+ }\r
+\r
+ IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;\r
+ IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
+\r
+ AsmWriteIdtr (&IdtDescriptor);\r
+\r
+ //\r
+ // Update the base address and length of Pei temporary memory\r
+ //\r
+ SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
+ SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
+ SecCoreData.BootFirmwareVolumeSize = (UINTN)(0x100000000ULL - (UINTN) BootFirmwareVolume);\r
+ SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;\r
+ SecCoreData.TemporaryRamSize = SizeOfRam;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;\r
+ SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackSize = PeiStackSize;\r
+\r
+ //\r
+ // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
+ //\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);\r
+\r
+}\r
+\r
+/**\r
+ Caller provided function to be invoked at the end of InitializeDebugAgent().\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param[in] Context The first input parameter of InitializeDebugAgent().\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartupPhase2(\r
+ IN VOID *Context\r
+ )\r
+{\r
+ EFI_SEC_PEI_HAND_OFF *SecCoreData;\r
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;\r
+\r
+ SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;\r
+ //\r
+ // Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug\r
+ // is enabled.\r
+ //\r
+ FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);\r
+ if (PeiCoreEntryPoint == NULL)\r
+ {\r
+ CpuDeadLoop ();\r
+ }\r
+\r
+ //\r
+ // Transfer the control to the PEI core\r
+ //\r
+ ASSERT (PeiCoreEntryPoint != NULL);\r
+ (*PeiCoreEntryPoint) (SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPeiSecPlatformInformationPpi);\r
+\r
+ //\r
+ // Should not come here.\r
+ //\r
+ return ;\r
+}\r
+\r
+/**\r
+ This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+ permanent memory.\r
+\r
+ @param PeiServices Pointer to the PEI Services Table.\r
+ @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param CopySize Amount of memory to migrate from temporary to permanent memory.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+ TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ )\r
+{\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ VOID* OldHeap;\r
+ VOID* NewHeap;\r
+ VOID* OldStack;\r
+ VOID* NewStack;\r
+ DEBUG_AGENT_CONTEXT_POSTMEM_SEC DebugAgentContext;\r
+ BOOLEAN OldStatus;\r
+ UINTN PeiStackSize;\r
+\r
+ PeiStackSize = (CopySize >> 1);\r
+\r
+ ASSERT (PeiStackSize < CopySize);\r
+\r
+ //\r
+ // |-------------------|---->\r
+ // | Stack | PeiStackSize\r
+ // |-------------------|---->\r
+ // | Heap | PeiTemporaryRamSize\r
+ // |-------------------|----> TempRamBase\r
+ //\r
+ // |-------------------|---->\r
+ // | Heap | PeiTemporaryRamSize\r
+ // |-------------------|---->\r
+ // | Stack | PeiStackSize\r
+ // |-------------------|----> PermanentMemoryBase\r
+ //\r
+\r
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + PeiStackSize);\r
+\r
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize - PeiStackSize);\r
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+\r
+ DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap - (UINTN)OldHeap;\r
+ DebugAgentContext.StackMigrateOffset = (UINTN)NewStack - (UINTN)OldStack;\r
+\r
+ OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);\r
+ //\r
+ // Initialize Debug Agent to support source level debug in PEI phase after memory ready.\r
+ // It will build HOB and fix up the pointer in IDT table.\r
+ //\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *) &DebugAgentContext, NULL);\r
+\r
+ //\r
+ // Migrate Heap\r
+ //\r
+ CopyMem (NewHeap, OldHeap, CopySize - PeiStackSize);\r
+\r
+ //\r
+ // Migrate Stack\r
+ //\r
+ CopyMem (NewStack, OldStack, PeiStackSize);\r
+\r
+\r
+ //\r
+ // We need *not* fix the return address because currently,\r
+ // The PeiCore is executed in flash.\r
+ //\r
+\r
+ //\r
+ // Rebase IDT table in permanent memory\r
+ //\r
+ AsmReadIdtr (&IdtDescriptor);\r
+ IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;\r
+\r
+ AsmWriteIdtr (&IdtDescriptor);\r
+\r
+\r
+ //\r
+ // Program MTRR\r
+ //\r
+\r
+ //\r
+ // SecSwitchStack function must be invoked after the memory migration\r
+ // immediately, also we need fixup the stack change caused by new call into\r
+ // permanent memory.\r
+ //\r
+ SecSwitchStack (\r
+ (UINT32) (UINTN) OldStack,\r
+ (UINT32) (UINTN) NewStack\r
+ );\r
+\r
+ SaveAndSetDebugTimerInterrupt (OldStatus);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Master header file for SecCore.\r
+\r
+Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef _SEC_CORE_H_\r
+#define _SEC_CORE_H_\r
+\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/TemporaryRamSupport.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiCpuLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/PeCoffExtraActionLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+\r
+#define SEC_IDT_ENTRY_COUNT 34\r
+\r
+typedef struct _SEC_IDT_TABLE {\r
+ //\r
+ // Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base\r
+ // address should be 8-byte alignment.\r
+ // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
+ // EFI_PEI_SERVICES**\r
+ //\r
+ UINT64 PeiService;\r
+ UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];\r
+} SEC_IDT_TABLE;\r
+\r
+/**\r
+ Switch the stack in the temporary memory to the one in the permanent memory.\r
+\r
+ This function must be invoked after the memory migration immediately. The relative\r
+ position of the stack in the temporary and permanent memory is same.\r
+\r
+ @param TemporaryMemoryBase Base address of the temporary memory.\r
+ @param PermenentMemoryBase Base address of the permanent memory.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecSwitchStack (\r
+ UINT32 TemporaryMemoryBase,\r
+ UINT32 PermenentMemoryBase\r
+ );\r
+\r
+/**\r
+ This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+ permanent memory.\r
+\r
+ @param PeiServices Pointer to the PEI Services Table.\r
+ @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param CopySize Amount of memory to migrate from temporary to permanent memory.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+ TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ );\r
+\r
+/**\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param SizeOfRam Size of the temporary memory available for use.\r
+ @param TempRamBase Base address of temporary ram\r
+ @param BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+ @param BootloaderParameter A parameter from bootloader, e.g. HobList from SlimBootloader\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume,\r
+ IN UINT32 BootloaderParameter\r
+ );\r
+\r
+/**\r
+ Find and return Pei Core entry point.\r
+\r
+ It also find SEC and PEI Core file debug information. It will report them if\r
+ remote debug is enabled.\r
+\r
+ @param BootFirmwareVolumePtr Point to the boot firmware volume.\r
+ @param PeiCoreEntryPoint Point to the PEI core entry point.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FindAndReportEntryPoints (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,\r
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint\r
+ );\r
+\r
+/**\r
+ Autogenerated function that calls the library constructors for all of the module's\r
+ dependent libraries. This function must be called by the SEC Core once a stack has\r
+ been established.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessLibraryConstructorList (\r
+ VOID\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# UEFI Payload Package\r
+#\r
+# Provides drivers and definitions to create uefi payload for bootloaders.\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = UefiPayloadPkg\r
+ PACKAGE_GUID = E0FC9D50-415E-4946-B686-9A130D5859E7\r
+ PACKAGE_VERSION = 0.1\r
+\r
+[Includes]\r
+ Include\r
+\r
+\r
+[Guids]\r
+ #\r
+ ## Defines the token space for the UEFI Payload Package PCDs.\r
+ #\r
+ gUefiPayloadPkgTokenSpaceGuid = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}}\r
+\r
+ #\r
+ # Gop Temp\r
+ #\r
+ gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }\r
+\r
+ gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}}\r
+ gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}}\r
+ gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }\r
+ gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }\r
+\r
+[Ppis]\r
+ gEfiPayLoadHobBasePpiGuid = { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }\r
+\r
+[Protocols]\r
+ #\r
+ # Gop Temp\r
+ #\r
+ gPlatformGOPPolicyGuid = { 0xec2e931b, 0x3281, 0x48a5, { 0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } }\r
+\r
+################################################################################\r
+#\r
+# PCD Declarations section - list of all PCDs Declared by this Package\r
+# Only this package should be providing the\r
+# declaration, other packages should not.\r
+#\r
+################################################################################\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+## Indicates the base address of the payload binary in memory\r
+gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemBase|0|UINT32|0x10000001\r
+## Provides the size of the payload binary in memory\r
+gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemSize|0|UINT32|0x10000002\r
+## Payload stack top\r
+gUefiPayloadPkgTokenSpaceGuid.PcdPayloadStackTop|0x90000|UINT32|0x10000004\r
+\r
+## FFS filename to find the shell application.\r
+gUefiPayloadPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1c, 0x4f, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x10000005\r
+\r
+## Used to help reduce fragmentation in the EFI memory map\r
+gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0x08|UINT32|0x10000012\r
+gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0x04|UINT32|0x10000013\r
+gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0x04|UINT32|0x00000014\r
+gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|0xC0|UINT32|0x00000015\r
+gUefiPayloadPkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x80|UINT32|0x00000016\r
+\r
+\r
--- /dev/null
+## @file\r
+# Bootloader Payload Package\r
+#\r
+# Provides drivers and definitions to create uefi payload for bootloaders.\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+################################################################################\r
+[FD.UefiPayload]\r
+BaseAddress = 0x800000|gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemBase\r
+Size = 0x410000|gUefiPayloadPkgTokenSpaceGuid.PcdPayloadFdMemSize\r
+ErasePolarity = 1\r
+BlockSize = 0x1000\r
+NumBlocks = 0x410\r
+\r
+0x00000000|0x030000\r
+FV = PEIFV\r
+\r
+0x00030000|0x3E0000\r
+FV = DXEFV\r
+\r
+################################################################################\r
+[FV.PEIFV]\r
+BlockSize = 0x1000\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+INF UefiPayloadPkg/SecCore/SecCore.inf\r
+\r
+INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
+INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r
+INF UefiPayloadPkg/BlSupportPei/BlSupportPei.inf\r
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+################################################################################\r
+\r
+[FV.DXEFV]\r
+BlockSize = 0x1000\r
+FvForceRebase = FALSE\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+APRIORI DXE {\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
+}\r
+\r
+#\r
+# DXE Phase modules\r
+#\r
+INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
+\r
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+INF MdeModulePkg/Application/UiApp/UiApp.inf\r
+INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+INF MdeModulePkg/Universal/Metronome/Metronome.inf\r
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+\r
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+INF UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf\r
+\r
+INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
+#\r
+# PCI Support\r
+#\r
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+\r
+#\r
+# ISA Support\r
+#\r
+INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
+\r
+#\r
+# Console Support\r
+#\r
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+INF UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf\r
+\r
+#\r
+# SCSI/ATA/IDE/DISK Support\r
+#\r
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf\r
+INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf\r
+INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf\r
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+\r
+INF FatPkg/EnhancedFatDxe/Fat.inf\r
+\r
+#\r
+# SD/eMMC Support\r
+#\r
+INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf\r
+INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf\r
+INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf\r
+\r
+#\r
+# Usb Support\r
+#\r
+INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
+INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+\r
+\r
+#\r
+# Shell\r
+#\r
+!if $(SHELL_TYPE) == BUILD_SHELL\r
+INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf\r
+INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf\r
+INF ShellPkg/Application/Shell/Shell.inf\r
+!endif\r
+\r
+!if $(SHELL_TYPE) == MIN_BIN\r
+!if $(ARCH) == IA32\r
+INF RuleOverride = BINARY USE = IA32 ShellBinPkg/MinUefiShell/MinUefiShell.inf\r
+!else\r
+INF RuleOverride = BINARY USE = X64 ShellBinPkg/MinUefiShell/MinUefiShell.inf\r
+!endif\r
+!endif\r
+\r
+!if $(SHELL_TYPE) == UEFI_BIN\r
+!if $(ARCH) == IA32\r
+INF RuleOverride = BINARY USE = IA32 ShellBinPkg/UefiShell/UefiShell.inf\r
+!else\r
+INF RuleOverride = BINARY USE = X64 ShellBinPkg/UefiShell/UefiShell.inf\r
+!endif\r
+!endif\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) {\r
+ PE32 PE32 Align=32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 Align=Auto $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 Align=Auto $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER.BINARY]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.BINARY]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.USER_DEFINED.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ }\r
+\r
+[Rule.Common.USER_DEFINED.CSM]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW BIN |.bin\r
+ }\r
+\r
+[Rule.Common.SEC.RESET_VECTOR]\r
+ FILE RAW = $(NAMED_GUID) {\r
+ RAW RAW |.raw\r
+ }\r
--- /dev/null
+## @file\r
+# Bootloader Payload Package\r
+#\r
+# Provides drivers and definitions to create uefi payload for bootloaders.\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = UefiPayloadPkg\r
+ PLATFORM_GUID = F71608AB-D63D-4491-B744-A99998C8CD96\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ SUPPORTED_ARCHITECTURES = IA32\r
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ OUTPUT_DIRECTORY = Build/UefiPayloadPkgIA32\r
+ FLASH_DEFINITION = UefiPayloadPkg/UefiPayloadPkg.fdf\r
+\r
+ DEFINE SOURCE_DEBUG_ENABLE = FALSE\r
+\r
+ #\r
+ # SBL: UEFI payload for Slim Bootloader\r
+ # COREBOOT: UEFI payload for coreboot\r
+ #\r
+ DEFINE BOOTLOADER = SBL\r
+\r
+ #\r
+ # CPU options\r
+ #\r
+ DEFINE MAX_LOGICAL_PROCESSORS = 64\r
+\r
+ #\r
+ # PCI options\r
+ #\r
+ DEFINE PCIE_BASE = 0xE0000000\r
+\r
+ #\r
+ # Serial port set up\r
+ #\r
+ DEFINE BAUD_RATE = 115200\r
+ DEFINE SERIAL_CLOCK_RATE = 1843200\r
+ DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity\r
+ DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE\r
+ DEFINE SERIAL_DETECT_CABLE = FALSE\r
+ DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO\r
+ DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16\r
+ DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)\r
+ DEFINE UART_DEFAULT_DATA_BITS = 8\r
+ DEFINE UART_DEFAULT_PARITY = 1\r
+ DEFINE UART_DEFAULT_STOP_BITS = 1\r
+ DEFINE DEFAULT_TERMINAL_TYPE = 0\r
+\r
+ #\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ #\r
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)\r
+ #\r
+ # [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]\r
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}\r
+\r
+ #\r
+ # Shell options: [BUILD_SHELL, MIN_BIN, NONE, UEFI_BIN]\r
+ #\r
+ DEFINE SHELL_TYPE = BUILD_SHELL\r
+\r
+[BuildOptions]\r
+ *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES\r
+ GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+ INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG\r
+ MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG\r
+\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses]\r
+ #\r
+ # Entry point\r
+ #\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+\r
+ #\r
+ # Basic\r
+ #\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+!if $(PCIE_BASE) == 0\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+!else\r
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf\r
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf\r
+!endif\r
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+\r
+ #\r
+ # UEFI & PI\r
+ #\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+\r
+ #\r
+ # Generic Modules\r
+ #\r
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf\r
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
+ FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf\r
+\r
+ #\r
+ # CPU\r
+ #\r
+ MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf\r
+ LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf\r
+\r
+ #\r
+ # Platform\r
+ #\r
+ TimerLib|UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ ResetSystemLib|UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf\r
+ SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf\r
+ PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf\r
+ PlatformBootManagerLib|UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf\r
+ IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf\r
+\r
+ #\r
+ # Misc\r
+ #\r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+!if $(SOURCE_DEBUG_ENABLE) == TRUE\r
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf\r
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf\r
+!else\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+!endif\r
+ PlatformSupportLib|UefiPayloadPkg/Library/PlatformSupportLibNull/PlatformSupportLibNull.inf\r
+!if $(BOOTLOADER) == "COREBOOT"\r
+ BlParseLib|UefiPayloadPkg/Library/CbParseLib/CbParseLib.inf\r
+!else\r
+ BlParseLib|UefiPayloadPkg/Library/SblParseLib/SblParseLib.inf\r
+!endif\r
+\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf\r
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf\r
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf\r
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf\r
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf\r
+\r
+[LibraryClasses.IA32.SEC]\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+\r
+[LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]\r
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf\r
+!endif\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+!endif\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+!endif\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag]\r
+!if $(TARGET) == DEBUG\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE\r
+!else\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
+\r
+[PcdsFixedAtBuild]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000\r
+ #\r
+ # Make VariableRuntimeDxe work at emulated non-volatile variable mode.\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
+!endif\r
+\r
+[PcdsPatchableInModule.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
+!endif\r
+\r
+ #\r
+ # The following parameters are set by Library/PlatformHookLib\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1\r
+\r
+ #\r
+ # Enable these parameters to be set on the command line\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONTROL)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIAL_HARDWARE_FLOW_CONTROL)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CABLE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)\r
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)\r
+\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsDynamicDefault]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3\r
+\r
+ ## This PCD defines the video horizontal resolution.\r
+ # This PCD could be set to 0 then video resolution could be at highest resolution.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0\r
+ ## This PCD defines the video vertical resolution.\r
+ # This PCD could be set to 0 then video resolution could be at highest resolution.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0\r
+\r
+ ## The PCD is used to specify the video horizontal resolution of text setup.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0\r
+ ## The PCD is used to specify the video vertical resolution of text setup.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform.\r
+#\r
+################################################################################\r
+[Components.IA32]\r
+ #\r
+ # SEC Core\r
+ #\r
+ UefiPayloadPkg/SecCore/SecCore.inf\r
+\r
+ #\r
+ # PEI Core\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+\r
+ #\r
+ # PEIM\r
+ #\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r
+\r
+ UefiPayloadPkg/BlSupportPei/BlSupportPei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+[Components.IA32]\r
+ #\r
+ # DXE Core\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ #\r
+ # Components that produce the architectural protocols\r
+ #\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+ MdeModulePkg/Application/UiApp/UiApp.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf\r
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf\r
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf\r
+ }\r
+\r
+ PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+\r
+ #\r
+ # Following are the DXE drivers\r
+ #\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+ PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+\r
+ UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf\r
+\r
+ #\r
+ # SMBIOS Support\r
+ #\r
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+\r
+ #\r
+ # PCI Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {\r
+ <LibraryClasses>\r
+ PciHostBridgeLib|UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf\r
+ }\r
+\r
+ #\r
+ # SCSI/ATA/IDE/DISK Support\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ FatPkg/EnhancedFatDxe/Fat.inf\r
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf\r
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf\r
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+\r
+ #\r
+ # SD/eMMC Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf\r
+ MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf\r
+ MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf\r
+\r
+ #\r
+ # Usb Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+\r
+ #\r
+ # ISA Support\r
+ #\r
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
+\r
+ #\r
+ # Console Support\r
+ #\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf\r
+\r
+ #------------------------------\r
+ # Build the shell\r
+ #------------------------------\r
+\r
+!if $(SHELL_TYPE) == BUILD_SHELL\r
+\r
+ #\r
+ # Shell Lib\r
+ #\r
+[LibraryClasses]\r
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+\r
+[Components.IA32]\r
+ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {\r
+ <PcdsFixedAtBuild>\r
+ ## This flag is used to control initialization of the shell library\r
+ # This should be FALSE for compiling the dynamic command.\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ }\r
+ ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf {\r
+ <PcdsFixedAtBuild>\r
+ ## This flag is used to control initialization of the shell library\r
+ # This should be FALSE for compiling the dynamic command.\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ }\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <PcdsFixedAtBuild>\r
+ ## This flag is used to control initialization of the shell library\r
+ # This should be FALSE for compiling the shell application itself only.\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+\r
+ #------------------------------\r
+ # Basic commands\r
+ #------------------------------\r
+\r
+ <LibraryClasses>\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+\r
+ #------------------------------\r
+ # Networking commands\r
+ #------------------------------\r
+\r
+ <LibraryClasses>\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+\r
+ #------------------------------\r
+ # Support libraries\r
+ #------------------------------\r
+\r
+ <LibraryClasses>\r
+ DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+ }\r
+\r
+!endif\r
--- /dev/null
+## @file\r
+# Bootloader Payload Package\r
+#\r
+# Provides drivers and definitions to create uefi payload for bootloaders.\r
+#\r
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = UefiPayloadPkg\r
+ PLATFORM_GUID = F71608AB-D63D-4491-B744-A99998C8CD96\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_SPECIFICATION = 0x00010005\r
+ SUPPORTED_ARCHITECTURES = IA32|X64\r
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ OUTPUT_DIRECTORY = Build/UefiPayloadPkgX64\r
+ FLASH_DEFINITION = UefiPayloadPkg/UefiPayloadPkg.fdf\r
+\r
+ DEFINE SOURCE_DEBUG_ENABLE = FALSE\r
+\r
+ #\r
+ # SBL: UEFI payload for Slim Bootloader\r
+ # COREBOOT: UEFI payload for coreboot\r
+ #\r
+ DEFINE BOOTLOADER = SBL\r
+\r
+ #\r
+ # CPU options\r
+ #\r
+ DEFINE MAX_LOGICAL_PROCESSORS = 64\r
+\r
+ #\r
+ # PCI options\r
+ #\r
+ DEFINE PCIE_BASE = 0xE0000000\r
+\r
+ #\r
+ # Serial port set up\r
+ #\r
+ DEFINE BAUD_RATE = 115200\r
+ DEFINE SERIAL_CLOCK_RATE = 1843200\r
+ DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity\r
+ DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE\r
+ DEFINE SERIAL_DETECT_CABLE = FALSE\r
+ DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO\r
+ DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16\r
+ DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)\r
+ DEFINE UART_DEFAULT_DATA_BITS = 8\r
+ DEFINE UART_DEFAULT_PARITY = 1\r
+ DEFINE UART_DEFAULT_STOP_BITS = 1\r
+ DEFINE DEFAULT_TERMINAL_TYPE = 0\r
+\r
+ #\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ #\r
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)\r
+ #\r
+ # [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]\r
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}\r
+\r
+ #\r
+ # Shell options: [BUILD_SHELL, MIN_BIN, NONE, UEFI_BIN]\r
+ #\r
+ DEFINE SHELL_TYPE = BUILD_SHELL\r
+\r
+[BuildOptions]\r
+ *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES\r
+ GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG\r
+ INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG\r
+ MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG\r
+\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses]\r
+ #\r
+ # Entry point\r
+ #\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+\r
+ #\r
+ # Basic\r
+ #\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+!if $(PCIE_BASE) == 0\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+!else\r
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf\r
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf\r
+!endif\r
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+\r
+ #\r
+ # UEFI & PI\r
+ #\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+\r
+ #\r
+ # Generic Modules\r
+ #\r
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf\r
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
+ FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf\r
+\r
+ #\r
+ # CPU\r
+ #\r
+ MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf\r
+ LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf\r
+\r
+ #\r
+ # Platform\r
+ #\r
+ TimerLib|UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ ResetSystemLib|UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf\r
+ SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf\r
+ PlatformHookLib|UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf\r
+ PlatformBootManagerLib|UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf\r
+ IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf\r
+\r
+ #\r
+ # Misc\r
+ #\r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+!if $(SOURCE_DEBUG_ENABLE) == TRUE\r
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf\r
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf\r
+!else\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+!endif\r
+ PlatformSupportLib|UefiPayloadPkg/Library/PlatformSupportLibNull/PlatformSupportLibNull.inf\r
+!if $(BOOTLOADER) == "COREBOOT"\r
+ BlParseLib|UefiPayloadPkg/Library/CbParseLib/CbParseLib.inf\r
+!else\r
+ BlParseLib|UefiPayloadPkg/Library/SblParseLib/SblParseLib.inf\r
+!endif\r
+\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf\r
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf\r
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf\r
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf\r
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf\r
+\r
+[LibraryClasses.IA32.SEC]\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+\r
+[LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]\r
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf\r
+!endif\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+!endif\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+!endif\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag]\r
+!if $(TARGET) == DEBUG\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE\r
+!else\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
+\r
+[PcdsFixedAtBuild]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000\r
+ #\r
+ # Make VariableRuntimeDxe work at emulated non-volatile variable mode.\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
+!endif\r
+\r
+[PcdsPatchableInModule.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
+!endif\r
+\r
+ #\r
+ # The following parameters are set by Library/PlatformHookLib\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1\r
+\r
+ #\r
+ # Enable these parameters to be set on the command line\r
+ #\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONTROL)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIAL_HARDWARE_FLOW_CONTROL)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CABLE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)\r
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)\r
+\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)\r
+\r
+\r
+################################################################################\r
+#\r
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsDynamicDefault]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3\r
+\r
+ ## This PCD defines the video horizontal resolution.\r
+ # This PCD could be set to 0 then video resolution could be at highest resolution.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0\r
+ ## This PCD defines the video vertical resolution.\r
+ # This PCD could be set to 0 then video resolution could be at highest resolution.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0\r
+\r
+ ## The PCD is used to specify the video horizontal resolution of text setup.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0\r
+ ## The PCD is used to specify the video vertical resolution of text setup.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform.\r
+#\r
+################################################################################\r
+[Components.IA32]\r
+ #\r
+ # SEC Core\r
+ #\r
+ UefiPayloadPkg/SecCore/SecCore.inf\r
+\r
+ #\r
+ # PEI Core\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+\r
+ #\r
+ # PEIM\r
+ #\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r
+\r
+ UefiPayloadPkg/BlSupportPei/BlSupportPei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+[Components.X64]\r
+ #\r
+ # DXE Core\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ #\r
+ # Components that produce the architectural protocols\r
+ #\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+ MdeModulePkg/Application/UiApp/UiApp.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf\r
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf\r
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf\r
+ }\r
+\r
+ PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
+\r
+ #\r
+ # Following are the DXE drivers\r
+ #\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+ PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+\r
+ UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf\r
+\r
+ #\r
+ # SMBIOS Support\r
+ #\r
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+\r
+ #\r
+ # PCI Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {\r
+ <LibraryClasses>\r
+ PciHostBridgeLib|UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf\r
+ }\r
+\r
+ #\r
+ # SCSI/ATA/IDE/DISK Support\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ FatPkg/EnhancedFatDxe/Fat.inf\r
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf\r
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf\r
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+\r
+ #\r
+ # SD/eMMC Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf\r
+ MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf\r
+ MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf\r
+\r
+ #\r
+ # Usb Support\r
+ #\r
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf\r
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+\r
+ #\r
+ # ISA Support\r
+ #\r
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
+\r
+ #\r
+ # Console Support\r
+ #\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ UefiPayloadPkg/GraphicsOutputDxe/GraphicsOutputDxe.inf\r
+\r
+ #------------------------------\r
+ # Build the shell\r
+ #------------------------------\r
+\r
+!if $(SHELL_TYPE) == BUILD_SHELL\r
+\r
+ #\r
+ # Shell Lib\r
+ #\r
+[LibraryClasses]\r
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+\r
+[Components.X64]\r
+ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {\r
+ <PcdsFixedAtBuild>\r
+ ## This flag is used to control initialization of the shell library\r
+ # This should be FALSE for compiling the dynamic command.\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ }\r
+ ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf {\r
+ <PcdsFixedAtBuild>\r
+ ## This flag is used to control initialization of the shell library\r
+ # This should be FALSE for compiling the dynamic command.\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ }\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <PcdsFixedAtBuild>\r
+ ## This flag is used to control initialization of the shell library\r
+ # This should be FALSE for compiling the shell application itself only.\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+\r
+ #------------------------------\r
+ # Basic commands\r
+ #------------------------------\r
+\r
+ <LibraryClasses>\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+\r
+ #------------------------------\r
+ # Networking commands\r
+ #------------------------------\r
+\r
+ <LibraryClasses>\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+\r
+ #------------------------------\r
+ # Support libraries\r
+ #------------------------------\r
+\r
+ <LibraryClasses>\r
+ DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+ }\r
+\r
+!endif\r
projects / mirror_edk2.git / commitdiff