Omap35xxPkg/PciEmulation: port to new non-discoverable device infrastructure

Move to the new non-discoverable device protocols for wiring the PCI based
EHCI controller driver to the non-discoverable EHCI controller found on the
OMAP 3530.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/BeagleBoardPkg/BeagleBoardPkg.dsc b/BeagleBoardPkg/BeagleBoardPkg.dsc
index 69d3c5f1841b7578cf50ca3cf32a94a9930ba085..b24db6cbfb04b91c3114261786a3a1fdf76fccbe 100644 (file)
--- a/BeagleBoardPkg/BeagleBoardPkg.dsc
+++ b/BeagleBoardPkg/BeagleBoardPkg.dsc
@@ -185,6 +185,7 @@
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
   SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
   SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
   PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r

+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf\r

 \r
 [LibraryClasses.common.UEFI_APPLICATION]\r
   ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
 \r
 [LibraryClasses.common.UEFI_APPLICATION]\r
   ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r


@@ -447,6 +448,7 @@
   # USB\r
   #\r
   Omap35xxPkg/PciEmulation/PciEmulation.inf\r
   # USB\r
   #\r
   Omap35xxPkg/PciEmulation/PciEmulation.inf\r

+  MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf\r

 \r
   MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf {\r
     <PcdsFixedAtBuild>\r
 \r
   MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf {\r
     <PcdsFixedAtBuild>\r

diff --git a/BeagleBoardPkg/BeagleBoardPkg.fdf b/BeagleBoardPkg/BeagleBoardPkg.fdf
index 42e097f641183f7c7ce977fa367b020d4809b685..f140d9019cac701e74be3023f2c4a6bb5a64eafc 100644 (file)
--- a/BeagleBoardPkg/BeagleBoardPkg.fdf
+++ b/BeagleBoardPkg/BeagleBoardPkg.fdf
@@ -2,6 +2,7 @@
 #\r
 # Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
 #\r
 # Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
 # Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r

+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>\r

 #\r
 #    This program and the accompanying materials\r
 #    are licensed and made available under the terms and conditions of the BSD License\r
 #\r
 #    This program and the accompanying materials\r
 #    are licensed and made available under the terms and conditions of the BSD License\r


@@ -167,6 +168,7 @@ FvNameGuid         = d0dd3e90-343d-4cb3-8f69-772214989282
   #\r
 \r
   INF Omap35xxPkg/PciEmulation/PciEmulation.inf\r
   #\r
 \r
   INF Omap35xxPkg/PciEmulation/PciEmulation.inf\r

+  INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf\r

 \r
   INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
   INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
 \r
   INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
   INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r

diff --git a/Omap35xxPkg/Omap35xxPkg.dsc b/Omap35xxPkg/Omap35xxPkg.dsc
index 436c10bb7f2fc44e20b7118429e1d9b15ccf8d8e..9395570ccaa33997cc5a32a13e0d53936540c587 100644 (file)
--- a/Omap35xxPkg/Omap35xxPkg.dsc
+++ b/Omap35xxPkg/Omap35xxPkg.dsc
@@ -80,7 +80,7 @@
 \r
 [LibraryClasses.common.DXE_DRIVER]\r
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
 \r
 [LibraryClasses.common.DXE_DRIVER]\r
   DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r

-\r
+  NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf\r

 \r
 [LibraryClasses.ARM]\r
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r
 \r
 [LibraryClasses.ARM]\r
   NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf\r

diff --git a/Omap35xxPkg/PciEmulation/PciEmulation.c b/Omap35xxPkg/PciEmulation/PciEmulation.c
index 17ea03ccf486eed9ab575625d69b0605f486a52f..d17646a9ed5800197fe2228141725312549f21a1 100644 (file)
--- a/Omap35xxPkg/PciEmulation/PciEmulation.c
+++ b/Omap35xxPkg/PciEmulation/PciEmulation.c
@@ -1,6 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r

+  Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>\r

 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r


@@ -12,49 +13,27 @@
 \r
 **/\r
 \r
 \r
 **/\r
 \r

-#include "PciEmulation.h"\r
+#include <PiDxe.h>\r

 \r
 \r

-EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;\r
-\r
-#define HOST_CONTROLLER_OPERATION_REG_SIZE  0x44\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r

 \r
 \r

-typedef struct {\r
-  ACPI_HID_DEVICE_PATH      AcpiDevicePath;\r
-  PCI_DEVICE_PATH           PciDevicePath;\r
-  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;\r
-} EFI_PCI_IO_DEVICE_PATH;\r
+#include <Protocol/EmbeddedExternalDevice.h>\r

 \r
 \r

-typedef struct {\r
-  UINT32                  Signature;\r
-  EFI_PCI_IO_DEVICE_PATH  DevicePath;\r
-  EFI_PCI_IO_PROTOCOL     PciIoProtocol;\r
-  PCI_TYPE00              *ConfigSpace;\r
-  PCI_ROOT_BRIDGE         RootBridge;\r
-  UINTN                   Segment;\r
-} EFI_PCI_IO_PRIVATE_DATA;\r
+#include <TPS65950.h>\r
+#include <Omap3530/Omap3530.h>\r

 \r
 \r

-#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE     SIGNATURE_32('p', 'c', 'i', 'o')\r
-#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a)  CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)\r
+EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;\r

 \r
 \r

-EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =\r
-{\r
-  {\r
-    { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },\r
-    EISA_PNP_ID(0x0A03),  // HID\r
-    0                     // UID\r
-  },\r
-  {\r
-    { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },\r
-    0,\r
-    0\r
-  },\r
-  { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }\r
-};\r
+#define HOST_CONTROLLER_OPERATION_REG_SIZE  0x44\r

 \r
 STATIC\r
 \r
 STATIC\r

-VOID\r
+EFI_STATUS\r

 ConfigureUSBHost (\r
 ConfigureUSBHost (\r

-  VOID\r
+  NON_DISCOVERABLE_DEVICE   *Device\r

   )\r
 {\r
   EFI_STATUS Status;\r
   )\r
 {\r
   EFI_STATUS Status;\r


@@ -103,454 +82,10 @@ ConfigureUSBHost (
 \r
   Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
   ASSERT_EFI_ERROR (Status);\r

-}\r
-\r
-\r
-EFI_STATUS\r
-PciIoPollMem (\r
-  IN EFI_PCI_IO_PROTOCOL           *This,\r
-  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN  UINT8                        BarIndex,\r
-  IN  UINT64                       Offset,\r
-  IN  UINT64                       Mask,\r
-  IN  UINT64                       Value,\r
-  IN  UINT64                       Delay,\r
-  OUT UINT64                       *Result\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-EFI_STATUS\r
-PciIoPollIo (\r
-  IN EFI_PCI_IO_PROTOCOL           *This,\r
-  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN  UINT8                        BarIndex,\r
-  IN  UINT64                       Offset,\r
-  IN  UINT64                       Mask,\r
-  IN  UINT64                       Value,\r
-  IN  UINT64                       Delay,\r
-  OUT UINT64                       *Result\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-EFI_STATUS\r
-PciIoMemRead (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN     UINT8                        BarIndex,\r
-  IN     UINT64                       Offset,\r
-  IN     UINTN                        Count,\r
-  IN OUT VOID                         *Buffer\r
-  )\r
-{\r
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
-\r
-  return PciRootBridgeIoMemRead (&Private->RootBridge.Io,\r
-                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
-                                Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
-                                Count,\r
-                                Buffer\r
-                                );\r
-}\r
-\r
-EFI_STATUS\r
-PciIoMemWrite (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN     UINT8                        BarIndex,\r
-  IN     UINT64                       Offset,\r
-  IN     UINTN                        Count,\r
-  IN OUT VOID                         *Buffer\r
-  )\r
-{\r
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
-\r
-  return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,\r
-                                 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
-                                 Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
-                                 Count,\r
-                                 Buffer\r
-                                 );\r
-}\r
-\r
-EFI_STATUS\r
-PciIoIoRead (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN     UINT8                        BarIndex,\r
-  IN     UINT64                       Offset,\r
-  IN     UINTN                        Count,\r
-  IN OUT VOID                         *Buffer\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-EFI_STATUS\r
-PciIoIoWrite (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN     UINT8                        BarIndex,\r
-  IN     UINT64                       Offset,\r
-  IN     UINTN                        Count,\r
-  IN OUT VOID                         *Buffer\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
-  Enable a PCI driver to read PCI controller registers in PCI configuration space.\r
-\r
-  @param[in]      This    A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
-  @param[in]      Width   Signifies the width of the memory operations.\r
-  @param[in]      Offset  The offset within the PCI configuration space for\r
-                          the PCI controller.\r
-  @param[in]      Count   The number of PCI configuration operations to\r
-                          perform. Bytes moved is Width size * Count,\r
-                          starting at Offset.\r
-\r
-  @param[in out]  Buffer  The destination buffer to store the results.\r
-\r
-  @retval  EFI_SUCCESS            The data was read from the PCI controller.\r
-  @retval  EFI_INVALID_PARAMETER  "Width" is invalid.\r
-  @retval  EFI_INVALID_PARAMETER  "Buffer" is NULL.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoPciRead (\r
-  IN     EFI_PCI_IO_PROTOCOL       *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT32                     Offset,\r
-  IN     UINTN                      Count,\r
-  IN OUT VOID                      *Buffer\r
-  )\r
-{\r
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
-  EFI_STATUS Status;\r
-\r
-  if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  Status = PciRootBridgeIoMemRW (\r
-             (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
-             Count,\r
-             TRUE,\r
-             (PTR)(UINTN)Buffer,\r
-             TRUE,\r
-             (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)  //Fix me ConfigSpace\r
-             );\r
-\r
-  return Status;\r
-}\r
-\r
-/**\r
-  Enable a PCI driver to write PCI controller registers in PCI configuration space.\r
-\r
-  @param[in]      This    A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
-  @param[in]      Width   Signifies the width of the memory operations.\r
-  @param[in]      Offset  The offset within the PCI configuration space for\r
-                          the PCI controller.\r
-  @param[in]      Count   The number of PCI configuration operations to\r
-                          perform. Bytes moved is Width size * Count,\r
-                          starting at Offset.\r
-\r
-  @param[in out]  Buffer  The source buffer to write data from.\r
-\r
-  @retval  EFI_SUCCESS            The data was read from the PCI controller.\r
-  @retval  EFI_INVALID_PARAMETER  "Width" is invalid.\r
-  @retval  EFI_INVALID_PARAMETER  "Buffer" is NULL.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoPciWrite (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN     UINT32                       Offset,\r
-  IN     UINTN                        Count,\r
-  IN OUT VOID                         *Buffer\r
-  )\r
-{\r
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
-\r
-  if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
-                               Count,\r
-                               TRUE,\r
-                               (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),\r
-                               TRUE,\r
-                               (PTR)(UINTN)Buffer\r
-                               );\r
-}\r
-\r
-EFI_STATUS\r
-PciIoCopyMem (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
-  IN     UINT8                        DestBarIndex,\r
-  IN     UINT64                       DestOffset,\r
-  IN     UINT8                        SrcBarIndex,\r
-  IN     UINT64                       SrcOffset,\r
-  IN     UINTN                        Count\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-EFI_STATUS\r
-PciIoMap (\r
-  IN EFI_PCI_IO_PROTOCOL                *This,\r
-  IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,\r
-  IN     VOID                           *HostAddress,\r
-  IN OUT UINTN                          *NumberOfBytes,\r
-  OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,\r
-  OUT    VOID                           **Mapping\r
-  )\r
-{\r
-  DMA_MAP_OPERATION   DmaOperation;\r
-\r
-  if (Operation == EfiPciIoOperationBusMasterRead) {\r
-    DmaOperation = MapOperationBusMasterRead;\r
-  } else if (Operation == EfiPciIoOperationBusMasterWrite) {\r
-    DmaOperation = MapOperationBusMasterWrite;\r
-  } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {\r
-    DmaOperation = MapOperationBusMasterCommonBuffer;\r
-  } else {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-  return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);\r
-}\r

 \r
 \r

-EFI_STATUS\r
-PciIoUnmap (\r
-  IN EFI_PCI_IO_PROTOCOL           *This,\r
-  IN  VOID                         *Mapping\r
-  )\r
-{\r
-  return DmaUnmap (Mapping);\r
-}\r
-\r
-/**\r
-  Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
-  mapping.\r
-\r
-  @param[in]   This         A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
-  @param[in]   Type         This parameter is not used and must be ignored.\r
-  @param[in]   MemoryType   The type of memory to allocate, EfiBootServicesData or\r
-                            EfiRuntimeServicesData.\r
-  @param[in]   Pages        The number of pages to allocate.\r
-  @param[out]  HostAddress  A pointer to store the base system memory address of\r
-                            the allocated range.\r
-  @param[in]   Attributes   The requested bit mask of attributes for the allocated\r
-                            range. Only the attributes,\r
-                            EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and\r
-                            EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this\r
-                            function. If any other bits are set, then EFI_UNSUPPORTED\r
-                            is returned. This function ignores this bit mask.\r
-\r
-  @retval  EFI_SUCCESS            The requested memory pages were allocated.\r
-  @retval  EFI_INVALID_PARAMETER  HostAddress is NULL.\r
-  @retval  EFI_INVALID_PARAMETER  MemoryType is invalid.\r
-  @retval  EFI_UNSUPPORTED        Attributes is unsupported.\r
-  @retval  EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoAllocateBuffer (\r
-  IN EFI_PCI_IO_PROTOCOL  *This,\r
-  IN  EFI_ALLOCATE_TYPE   Type,\r
-  IN  EFI_MEMORY_TYPE     MemoryType,\r
-  IN  UINTN               Pages,\r
-  OUT VOID                **HostAddress,\r
-  IN  UINT64              Attributes\r
-  )\r
-{\r
-  if (Attributes &\r
-      (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |\r
-         EFI_PCI_ATTRIBUTE_MEMORY_CACHED         ))) {\r
-    return EFI_UNSUPPORTED;\r
-  }\r
-\r
-  return DmaAllocateBuffer (MemoryType, Pages, HostAddress);\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciIoFreeBuffer (\r
-  IN EFI_PCI_IO_PROTOCOL           *This,\r
-  IN  UINTN                        Pages,\r
-  IN  VOID                         *HostAddress\r
-  )\r
-{\r
-  return DmaFreeBuffer (Pages, HostAddress);\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciIoFlush (\r
-  IN EFI_PCI_IO_PROTOCOL  *This\r
-  )\r
-{\r

   return EFI_SUCCESS;\r
 }\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r

-/**\r
-  Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
-\r
-  @param[in]   This            A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
-  @param[out]  SegmentNumber   The PCI controller's current PCI segment number.\r
-  @param[out]  BusNumber       The PCI controller's current PCI bus number.\r
-  @param[out]  DeviceNumber    The PCI controller's current PCI device number.\r
-  @param[out]  FunctionNumber  The PCI controller’s current PCI function number.\r
-\r
-  @retval  EFI_SUCCESS            The PCI controller location was returned.\r
-  @retval  EFI_INVALID_PARAMETER  At least one out of the four output parameters is\r
-                                  a NULL pointer.\r
-**/\r
-EFI_STATUS\r
-PciIoGetLocation (\r
-  IN   EFI_PCI_IO_PROTOCOL  *This,\r
-  OUT  UINTN                *SegmentNumber,\r
-  OUT  UINTN                *BusNumber,\r
-  OUT  UINTN                *DeviceNumber,\r
-  OUT  UINTN                *FunctionNumber\r
-  )\r
-{\r
-  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
-\r
-  if ((SegmentNumber == NULL) || (BusNumber      == NULL) ||\r
-      (DeviceNumber  == NULL) || (FunctionNumber == NULL)    ) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  *SegmentNumber  = Private->Segment;\r
-  *BusNumber      = 0xff;\r
-  *DeviceNumber   = 0;\r
-  *FunctionNumber = 0;\r
-\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
-  Performs an operation on the attributes that this PCI controller supports.\r
-\r
-  The operations include getting the set of supported attributes, retrieving\r
-  the current attributes, setting the current attributes, enabling attributes,\r
-  and disabling attributes.\r
-\r
-  @param[in]   This        A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
-  @param[in]   Operation   The operation to perform on the attributes for this\r
-                           PCI controller.\r
-  @param[in]   Attributes  The mask of attributes that are used for Set,\r
-                           Enable and Disable operations.\r
-  @param[out]  Result      A pointer to the result mask of attributes that are\r
-                           returned for the Get and Supported operations. This\r
-                           is an optional parameter that may be NULL for the\r
-                           Set, Enable, and Disable operations.\r
-\r
-  @retval  EFI_SUCCESS            The operation on the PCI controller's\r
-                                  attributes was completed. If the operation\r
-                                  was Get or Supported, then the attribute mask\r
-                                  is returned in Result.\r
-  @retval  EFI_INVALID_PARAMETER  Operation is greater than or equal to\r
-                                  EfiPciIoAttributeOperationMaximum.\r
-  @retval  EFI_INVALID_PARAMETER  Operation is Get and Result is NULL.\r
-  @retval  EFI_INVALID_PARAMETER  Operation is Supported and Result is NULL.\r
-\r
-**/\r
-EFI_STATUS\r
-PciIoAttributes (\r
-  IN EFI_PCI_IO_PROTOCOL                       *This,\r
-  IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,\r
-  IN  UINT64                                   Attributes,\r
-  OUT UINT64                                   *Result OPTIONAL\r
-  )\r
-{\r
-  switch (Operation) {\r
-  case EfiPciIoAttributeOperationGet:\r
-  case EfiPciIoAttributeOperationSupported:\r
-    if (Result == NULL) {\r
-      return EFI_INVALID_PARAMETER;\r
-    }\r
-    //\r
-    // We are not a real PCI device so just say things we kind of do\r
-    //\r
-    *Result = EFI_PCI_DEVICE_ENABLE;\r
-    break;\r
-\r
-  case EfiPciIoAttributeOperationSet:\r
-  case EfiPciIoAttributeOperationEnable:\r
-  case EfiPciIoAttributeOperationDisable:\r
-    if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) {\r
-      return EFI_UNSUPPORTED;\r
-    }\r
-    // Since we are not a real PCI device no enable/set or disable operations exist.\r
-    return EFI_SUCCESS;\r
-\r
-  default:\r
-    return EFI_INVALID_PARAMETER;\r
-  };\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciIoGetBarAttributes (\r
-  IN EFI_PCI_IO_PROTOCOL             *This,\r
-  IN  UINT8                          BarIndex,\r
-  OUT UINT64                         *Supports, OPTIONAL\r
-  OUT VOID                           **Resources OPTIONAL\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-EFI_STATUS\r
-PciIoSetBarAttributes (\r
-  IN EFI_PCI_IO_PROTOCOL              *This,\r
-  IN     UINT64                       Attributes,\r
-  IN     UINT8                        BarIndex,\r
-  IN OUT UINT64                       *Offset,\r
-  IN OUT UINT64                       *Length\r
-  )\r
-{\r
-  ASSERT (FALSE);\r
-  return EFI_UNSUPPORTED;\r
-}\r
-\r
-EFI_PCI_IO_PROTOCOL PciIoTemplate =\r
-{\r
-  PciIoPollMem,\r
-  PciIoPollIo,\r
-  { PciIoMemRead, PciIoMemWrite },\r
-  { PciIoIoRead,  PciIoIoWrite },\r
-  { PciIoPciRead, PciIoPciWrite },\r
-  PciIoCopyMem,\r
-  PciIoMap,\r
-  PciIoUnmap,\r
-  PciIoAllocateBuffer,\r
-  PciIoFreeBuffer,\r
-  PciIoFlush,\r
-  PciIoGetLocation,\r
-  PciIoAttributes,\r
-  PciIoGetBarAttributes,\r
-  PciIoSetBarAttributes,\r
-  0,\r
-  0\r
-};\r
-\r

 EFI_STATUS\r
 EFIAPI\r
 PciEmulationEntryPoint (\r
 EFI_STATUS\r
 EFIAPI\r
 PciEmulationEntryPoint (\r


@@ -558,76 +93,21 @@ PciEmulationEntryPoint (
   IN EFI_SYSTEM_TABLE *SystemTable\r
   )\r
 {\r
   IN EFI_SYSTEM_TABLE *SystemTable\r
   )\r
 {\r

-  EFI_STATUS              Status;\r
-  EFI_HANDLE              Handle;\r
-  EFI_PCI_IO_PRIVATE_DATA *Private;\r

   UINT8                   CapabilityLength;\r
   UINT8                   PhysicalPorts;\r
   UINT8                   CapabilityLength;\r
   UINT8                   PhysicalPorts;\r

-  UINTN                   Count;\r
-\r
-\r
-  //Configure USB host for OMAP3530.\r
-  ConfigureUSBHost();\r
-\r
-  // Create a private structure\r
-  Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));\r
-  if (Private == NULL) {\r
-    Status = EFI_OUT_OF_RESOURCES;\r
-    return Status;\r
-  }\r
-\r
-  Private->Signature              = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE;  // Fill in signature\r
-  Private->RootBridge.Signature   = PCI_ROOT_BRIDGE_SIGNATURE;          // Fake Root Bridge structure needs a signature too\r
-  Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE;                 // Get the USB capability register base\r
-  Private->Segment                = 0;                                  // Default to segment zero\r
-\r
-  // Find out the capability register length and number of physical ports.\r
-  CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);\r
-  PhysicalPorts    = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;\r
-\r
-  // Calculate the total size of the USB registers.\r
-  Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));\r
-\r
-  // Enable Port Power bit in Port status and control registers in EHCI register space.\r
-  // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates\r
-  // host controller implementation includes port power control.\r
-  for (Count = 0; Count < PhysicalPorts; Count++) {\r
-    MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);\r
-  }\r
-\r
-  // Create fake PCI config space.\r
-  Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));\r
-  if (Private->ConfigSpace == NULL) {\r
-    Status = EFI_OUT_OF_RESOURCES;\r
-    FreePool(Private);\r
-    return Status;\r
-  }\r
-\r
-  // Configure PCI config space\r
-  Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device.\r
-  Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid.\r
-  Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;\r
-  Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;\r
-  Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;\r
-  Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;\r
-\r
-  Handle = NULL;\r
-\r
-  // Unique device path.\r
-  CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));\r
-  Private->DevicePath.AcpiDevicePath.UID = 0;\r
-\r
-  // Copy protocol structure\r
-  CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));\r
-\r
-  Status = gBS->InstallMultipleProtocolInterfaces(&Handle,\r
-                                                  &gEfiPciIoProtocolGuid,       &Private->PciIoProtocol,\r
-                                                  &gEfiDevicePathProtocolGuid,  &Private->DevicePath,\r
-                                                  NULL);\r
-  if (EFI_ERROR(Status)) {\r
-    DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));\r
-  }\r
-\r
-  return Status;\r
+  UINTN                   MemorySize;\r
+\r
+  CapabilityLength = MmioRead8 (USB_EHCI_HCCAPBASE);\r
+  PhysicalPorts    = MmioRead32 (USB_EHCI_HCCAPBASE + 0x4) & 0x0000000F;\r
+  MemorySize       = CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE +\r
+                     4 * PhysicalPorts - 1;\r
+\r
+  return RegisterNonDiscoverableMmioDevice (\r
+           NonDiscoverableDeviceTypeEhci,\r
+           NonDiscoverableDeviceDmaTypeNonCoherent,\r
+           ConfigureUSBHost,\r
+           NULL,\r
+           1,\r
+           USB_EHCI_HCCAPBASE, MemorySize\r
+           );\r

 }\r
 }\r

-\r

diff --git a/Omap35xxPkg/PciEmulation/PciEmulation.h b/Omap35xxPkg/PciEmulation/PciEmulation.h
deleted file mode 100644 (file)
index d5ee043..0000000
--- a/Omap35xxPkg/PciEmulation/PciEmulation.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/** @file\r
-\r
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _PCI_ROOT_BRIDGE_H_\r
-#define _PCI_ROOT_BRIDGE_H_\r
-\r
-#include <PiDxe.h>\r
-\r
-#include <TPS65950.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/DxeServicesTableLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/PciLib.h>\r
-#include <Library/UefiLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-#include <Library/OmapDmaLib.h>\r
-#include <Library/DmaLib.h>\r
-\r
-#include <Protocol/EmbeddedExternalDevice.h>\r
-#include <Protocol/DevicePath.h>\r
-#include <Protocol/PciIo.h>\r
-#include <Protocol/PciRootBridgeIo.h>\r
-#include <Protocol/PciHostBridgeResourceAllocation.h>\r
-\r
-#include <IndustryStandard/Pci22.h>\r
-#include <IndustryStandard/Acpi.h>\r
-\r
-#include <Omap3530/Omap3530.h>\r
-\r
-\r
-\r
-#define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL\r
-#define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL\r
-#define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL\r
-\r
-\r
-typedef struct {\r
-  ACPI_HID_DEVICE_PATH      AcpiDevicePath;\r
-  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;\r
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
-\r
-\r
-#define ACPI_CONFIG_IO    0\r
-#define ACPI_CONFIG_MMIO  1\r
-#define ACPI_CONFIG_BUS   2\r
-\r
-typedef struct {\r
-  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];\r
-  EFI_ACPI_END_TAG_DESCRIPTOR       EndDesc;\r
-} ACPI_CONFIG_INFO;\r
-\r
-\r
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')\r
-\r
-typedef struct {\r
-  UINT32                                            Signature;\r
-  EFI_HANDLE                                        Handle;\r
-  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL                   Io;\r
-  EFI_PCI_ROOT_BRIDGE_DEVICE_PATH                   DevicePath;\r
-\r
-  UINT8   StartBus;\r
-  UINT8   EndBus;\r
-  UINT16  Type;\r
-  UINT32  MemoryStart;\r
-  UINT32  MemorySize;\r
-  UINTN   IoOffset;\r
-  UINT32  IoStart;\r
-  UINT32  IoSize;\r
-  UINT64  PciAttributes;\r
-\r
-  ACPI_CONFIG_INFO  *Config;\r
-\r
-} PCI_ROOT_BRIDGE;\r
-\r
-\r
-#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
-\r
-\r
-typedef union {\r
-  UINT8   volatile  *buf;\r
-  UINT8   volatile  *ui8;\r
-  UINT16  volatile  *ui16;\r
-  UINT32  volatile  *ui32;\r
-  UINT64  volatile  *ui64;\r
-  UINTN   volatile  ui;\r
-} PTR;\r
-\r
-\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoPollMem (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN  UINT64                                 Address,\r
-  IN  UINT64                                 Mask,\r
-  IN  UINT64                                 Value,\r
-  IN  UINT64                                 Delay,\r
-  OUT UINT64                                 *Result\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoPollIo (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN  UINT64                                 Address,\r
-  IN  UINT64                                 Mask,\r
-  IN  UINT64                                 Value,\r
-  IN  UINT64                                 Delay,\r
-  OUT UINT64                                 *Result\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoMemRead (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoMemWrite (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoIoRead (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 UserAddress,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *UserBuffer\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoIoWrite (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 UserAddress,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *UserBuffer\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoCopyMem (\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN UINT64                                 DestAddress,\r
-  IN UINT64                                 SrcAddress,\r
-  IN UINTN                                  Count\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoPciRead (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoPciWrite (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoMap (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
-  IN     VOID                                       *HostAddress,\r
-  IN OUT UINTN                                      *NumberOfBytes,\r
-  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
-  OUT    VOID                                       **Mapping\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoUnmap (\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
-  IN VOID                             *Mapping\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoAllocateBuffer (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
-  IN  EFI_ALLOCATE_TYPE                Type,\r
-  IN  EFI_MEMORY_TYPE                  MemoryType,\r
-  IN  UINTN                            Pages,\r
-  OUT VOID                             **HostAddress,\r
-  IN  UINT64                           Attributes\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoFreeBuffer (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
-  IN  UINTN                            Pages,\r
-  OUT VOID                             *HostAddress\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoFlush (\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoGetAttributes (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
-  OUT UINT64                           *Supported,\r
-  OUT UINT64                           *Attributes\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoSetAttributes (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
-  IN     UINT64                           Attributes,\r
-  IN OUT UINT64                           *ResourceBase,\r
-  IN OUT UINT64                           *ResourceLength\r
-  );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoConfiguration (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
-  OUT VOID                             **Resources\r
-  );\r
-\r
-//\r
-// Private Function Prototypes\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoMemRW (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN  UINTN                                  Count,\r
-  IN  BOOLEAN                                InStrideFlag,\r
-  IN  PTR                                    In,\r
-  IN  BOOLEAN                                OutStrideFlag,\r
-  OUT PTR                                    Out\r
-  );\r
-\r
-BOOLEAN\r
-PciIoMemAddressValid (\r
-  IN EFI_PCI_IO_PROTOCOL  *This,\r
-  IN UINT64               Address\r
-  );\r
-\r
-EFI_STATUS\r
-EmulatePciIoForEhci (\r
-  INTN    MvPciIfMaxIf\r
-  );\r
-\r
-#endif\r
-\r

diff --git a/Omap35xxPkg/PciEmulation/PciEmulation.inf b/Omap35xxPkg/PciEmulation/PciEmulation.inf
index 2180bb49898da264cbb7594552a1ce6c0faf8ea2..941060202ce54ae06cb06621cd0071285e9a22e1 100644 (file)
--- a/Omap35xxPkg/PciEmulation/PciEmulation.inf
+++ b/Omap35xxPkg/PciEmulation/PciEmulation.inf
@@ -1,6 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r
 /** @file\r
 \r
   Copyright (c) 2009, Apple Inc. All rights reserved.<BR>\r

+  Copyright (c) 2016, Linaro, Ltd. All rights reserved.<BR>\r

 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r


@@ -22,33 +23,23 @@
   ENTRY_POINT                     = PciEmulationEntryPoint\r
 \r
 [Sources.common]\r
   ENTRY_POINT                     = PciEmulationEntryPoint\r
 \r
 [Sources.common]\r

-  PciRootBridgeIo.c\r

   PciEmulation.c\r
 \r
 [Packages]\r
   MdePkg/MdePkg.dec\r
   MdeModulePkg/MdeModulePkg.dec\r
   PciEmulation.c\r
 \r
 [Packages]\r
   MdePkg/MdePkg.dec\r
   MdeModulePkg/MdeModulePkg.dec\r

-  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
-  ArmPkg/ArmPkg.dec\r

   EmbeddedPkg/EmbeddedPkg.dec\r
   Omap35xxPkg/Omap35xxPkg.dec\r
 \r
 [LibraryClasses]\r
   BaseLib\r
   EmbeddedPkg/EmbeddedPkg.dec\r
   Omap35xxPkg/Omap35xxPkg.dec\r
 \r
 [LibraryClasses]\r
   BaseLib\r

-  DxeServicesTableLib\r
-  UefiLib\r
+  DebugLib\r
+  IoLib\r
+  NonDiscoverableDeviceRegistrationLib\r

   UefiBootServicesTableLib\r
   UefiDriverEntryPoint\r
   UefiBootServicesTableLib\r
   UefiDriverEntryPoint\r

-  UefiRuntimeServicesTableLib\r
-  IoLib\r
-  OmapDmaLib\r
-  DmaLib\r

 \r
 [Protocols]\r
 \r
 [Protocols]\r

-  gEfiPciRootBridgeIoProtocolGuid\r
-  gEfiDevicePathProtocolGuid\r
-  gEfiPciHostBridgeResourceAllocationProtocolGuid\r
-  gEfiPciIoProtocolGuid\r

   gEmbeddedExternalDeviceProtocolGuid\r
 \r
 [Depex]\r
   gEmbeddedExternalDeviceProtocolGuid\r
 \r
 [Depex]\r

diff --git a/Omap35xxPkg/PciEmulation/PciRootBridgeIo.c b/Omap35xxPkg/PciEmulation/PciRootBridgeIo.c
deleted file mode 100644 (file)
index e8635ed..0000000
--- a/Omap35xxPkg/PciEmulation/PciRootBridgeIo.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/** @file\r
-\r
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "PciEmulation.h"\r
-\r
-BOOLEAN\r
-PciRootBridgeMemAddressValid (\r
-  IN PCI_ROOT_BRIDGE  *Private,\r
-  IN UINT64           Address\r
-  )\r
-{\r
-  if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {\r
-    return TRUE;\r
-  }\r
-\r
-  return FALSE;\r
-}\r
-\r
-\r
-EFI_STATUS\r
-PciRootBridgeIoMemRW (\r
-  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN  UINTN                                  Count,\r
-  IN  BOOLEAN                                InStrideFlag,\r
-  IN  PTR                                    In,\r
-  IN  BOOLEAN                                OutStrideFlag,\r
-  OUT PTR                                    Out\r
-  )\r
-{\r
-  UINTN  Stride;\r
-  UINTN  InStride;\r
-  UINTN  OutStride;\r
-\r
-\r
-  Width     = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
-  Stride    = (UINTN)1 << Width;\r
-  InStride  = InStrideFlag  ? Stride : 0;\r
-  OutStride = OutStrideFlag ? Stride : 0;\r
-\r
-  //\r
-  // Loop for each iteration and move the data\r
-  //\r
-  switch (Width) {\r
-  case EfiPciWidthUint8:\r
-    for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {\r
-      *In.ui8 = *Out.ui8;\r
-    }\r
-    break;\r
-  case EfiPciWidthUint16:\r
-    for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {\r
-      *In.ui16 = *Out.ui16;\r
-    }\r
-    break;\r
-  case EfiPciWidthUint32:\r
-    for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {\r
-      *In.ui32 = *Out.ui32;\r
-    }\r
-    break;\r
-  default:\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-PciRootBridgeIoPciRW (\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN BOOLEAN                                Write,\r
-  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN UINT64                                 UserAddress,\r
-  IN UINTN                                  Count,\r
-  IN OUT VOID                               *UserBuffer\r
-  )\r
-{\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-/**\r
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-  @param  Width                 Signifies the width of the memory operations.\r
-  @param  Address               The base address of the memory operations.\r
-  @param  Count                 The number of memory operations to perform.\r
-  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
-                                operations, the source buffer to write data from.\r
-\r
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoMemRead (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  )\r
-{\r
-  PCI_ROOT_BRIDGE   *Private;\r
-  UINTN             AlignMask;\r
-  PTR               In;\r
-  PTR               Out;\r
-\r
-  if ( Buffer == NULL ) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
-\r
-  if (!PciRootBridgeMemAddressValid (Private, Address)) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  AlignMask = (1 << (Width & 0x03)) - 1;\r
-  if (Address & AlignMask) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  In.buf  = Buffer;\r
-  Out.buf = (VOID *)(UINTN) Address;\r
-\r
-  switch (Width) {\r
-  case EfiPciWidthUint8:\r
-  case EfiPciWidthUint16:\r
-  case EfiPciWidthUint32:\r
-  case EfiPciWidthUint64:\r
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);\r
-\r
-  case EfiPciWidthFifoUint8:\r
-  case EfiPciWidthFifoUint16:\r
-  case EfiPciWidthFifoUint32:\r
-  case EfiPciWidthFifoUint64:\r
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);\r
-\r
-  case EfiPciWidthFillUint8:\r
-  case EfiPciWidthFillUint16:\r
-  case EfiPciWidthFillUint32:\r
-  case EfiPciWidthFillUint64:\r
-    return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);\r
-\r
-  default:\r
-    break;\r
-  }\r
-\r
-  return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-\r
-\r
-/**\r
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-  @param  Width                 Signifies the width of the memory operations.\r
-  @param  Address               The base address of the memory operations.\r
-  @param  Count                 The number of memory operations to perform.\r
-  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
-                                operations, the source buffer to write data from.\r
-\r
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoMemWrite (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  )\r
-{\r
-  PCI_ROOT_BRIDGE *Private;\r
-  UINTN  AlignMask;\r
-  PTR    In;\r
-  PTR    Out;\r
-\r
-  if ( Buffer == NULL ) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
-\r
-  if (!PciRootBridgeMemAddressValid (Private, Address)) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  AlignMask = (1 << (Width & 0x03)) - 1;\r
-  if (Address & AlignMask) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  In.buf  = (VOID *)(UINTN) Address;\r
-  Out.buf = Buffer;\r
-\r
-  switch (Width) {\r
-  case EfiPciWidthUint8:\r
-  case EfiPciWidthUint16:\r
-  case EfiPciWidthUint32:\r
-  case EfiPciWidthUint64:\r
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);\r
-\r
-  case EfiPciWidthFifoUint8:\r
-  case EfiPciWidthFifoUint16:\r
-  case EfiPciWidthFifoUint32:\r
-  case EfiPciWidthFifoUint64:\r
-    return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);\r
-\r
-  case EfiPciWidthFillUint8:\r
-  case EfiPciWidthFillUint16:\r
-  case EfiPciWidthFillUint32:\r
-  case EfiPciWidthFillUint64:\r
-    return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);\r
-\r
-  default:\r
-    break;\r
-  }\r
-\r
-  return EFI_INVALID_PARAMETER;\r
-}\r
-\r
-/**\r
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-  @param  Width                 Signifies the width of the memory operations.\r
-  @param  Address               The base address of the memory operations.\r
-  @param  Count                 The number of memory operations to perform.\r
-  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
-                                operations, the source buffer to write data from.\r
-\r
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoPciRead (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  )\r
-{\r
-  if (Buffer == NULL) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
-}\r
-\r
-\r
-\r
-/**\r
-  Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
-\r
-  @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
-  @param  Width                 Signifies the width of the memory operations.\r
-  @param  Address               The base address of the memory operations.\r
-  @param  Count                 The number of memory operations to perform.\r
-  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
-                                operations, the source buffer to write data from.\r
-\r
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.\r
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-PciRootBridgeIoPciWrite (\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
-  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
-  IN     UINT64                                 Address,\r
-  IN     UINTN                                  Count,\r
-  IN OUT VOID                                   *Buffer\r
-  )\r
-{\r
-  if (Buffer == NULL) {\r
-    return EFI_INVALID_PARAMETER;\r
-  }\r
-\r
-  return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
-}\r
-\r
-\r