ArmPlatformPkg: Reformat VE Memory Map code

This change is purely cosmetic, with no functional impact, and only
exists to isolate cosmetic changes from a functional fix.
    Some indentation is adjusted.
    Overlength lines are re-flowed.
    alignment on = is adjusted as some lines exceeded 80 columns.
    if statement converted to conditional assignment.
    Redundant re-calculation of CacheAttributes removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
index 115df246796d23081dadcbda94f743bc63233f56..14541183d1eb6916690823d7e04507fc50639f5f 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
@@ -24,17 +24,19 @@
 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6\r
 \r
 // DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+#define DDR_ATTRIBUTES_CACHED   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
 \r
 /**\r
   Return the Virtual Memory Map of your platform\r
 \r
-  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
+  This Virtual Memory Map is used by MemoryInitPei Module to initialize\r
+  the MMU on your platform.\r
 \r
-  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
-                                    Virtual Memory mapping. This array must be ended by a zero-filled\r
-                                    entry\r
+  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR\r
+                                    describing a Physical-to-Virtual Memory\r
+                                    mapping. This array must be ended by a\r
+                                    zero-filled entry.\r
 \r
 **/\r
 VOID\r
@@ -59,12 +61,12 @@ ArmPlatformGetVirtualMemoryMap (
     HasSparseMemory = TRUE;\r
 \r
     ResourceAttributes =\r
-        EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
-        EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
-        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
-        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
-        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
-        EFI_RESOURCE_ATTRIBUTE_TESTED;\r
+      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+      EFI_RESOURCE_ATTRIBUTE_TESTED;\r
 \r
     // Declared the additional DRAM from 2GB to 4GB\r
     SparseMemoryBase = 0x0880000000;\r
@@ -81,77 +83,66 @@ ArmPlatformGetVirtualMemoryMap (
     SparseMemorySize = 0x0;\r
   }\r
 \r
-  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)\r
+    AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR)\r
+                                      * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
   if (VirtualMemoryTable == NULL) {\r
-      return;\r
+    return;\r
   }\r
 \r
-  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
-      CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
-  } else {\r
-      CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
-  }\r
+  CacheAttributes = (FeaturePcdGet(PcdCacheEnable))\r
+                    ? DDR_ATTRIBUTES_CACHED\r
+                    : DDR_ATTRIBUTES_UNCACHED;\r
 \r
   // ReMap (Either NOR Flash or DRAM)\r
   VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
-  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;\r
-  VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;\r
-\r
-  if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {\r
-    // Map the NOR Flash as Secure Memory\r
-    if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
-      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_CACHED;\r
-    } else {\r
-      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_UNCACHED;\r
-    }\r
-  } else {\r
-    // DRAM mapping\r
-    VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
-  }\r
+  VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
+  VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
+  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
 \r
   // DDR\r
   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
-  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;\r
-  VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;\r
-  VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
+  VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
+  VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
+  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
 \r
   // CPU peripherals. TRM. Manual says not all of them are implemented.\r
   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
-  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_ON_CHIP_PERIPH_BASE;\r
-  VirtualMemoryTable[Index].Length       = ARM_VE_ON_CHIP_PERIPH_SZ;\r
-  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+  VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r
+  VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;\r
+  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
 \r
   // SMB CS0-CS1 - NOR Flash 1 & 2\r
   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
-  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;\r
-  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
-  VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
+  VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
+  VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
+  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
 \r
   // SMB CS2 - SRAM\r
   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
-  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;\r
-  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;\r
-  VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
+  VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
+  VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
+  VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
 \r
   // Peripheral CS2 and CS3\r
   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
-  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;\r
-  VirtualMemoryTable[Index].Length       = 2 * ARM_VE_SMB_PERIPH_SZ;\r
-  VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
+  VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
+  VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r
+  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
 \r
   // Map sparse memory region if present\r
   if (HasSparseMemory) {\r
     VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r
-    VirtualMemoryTable[Index].VirtualBase    = SparseMemoryBase;\r
-    VirtualMemoryTable[Index].Length         = SparseMemorySize;\r
-    VirtualMemoryTable[Index].Attributes     = CacheAttributes;\r
+    VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;\r
+    VirtualMemoryTable[Index].Length = SparseMemorySize;\r
+    VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
   }\r
 \r
   // End of Table\r
   VirtualMemoryTable[++Index].PhysicalBase = 0;\r
-  VirtualMemoryTable[Index].VirtualBase  = 0;\r
-  VirtualMemoryTable[Index].Length       = 0;\r
-  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+  VirtualMemoryTable[Index].VirtualBase = 0;\r
+  VirtualMemoryTable[Index].Length = 0;\r
+  VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
 \r
   *VirtualMemoryMap = VirtualMemoryTable;\r
 }\r