gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
\r
## PL011 UART\r
- gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F\r
- gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020\r
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
+ gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
+ gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
\r
## PL031 RealTimeClock\r
gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
-/** @file
- Serial I/O Port library functions with no library constructor/destructor
-
-
- Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Include/Uefi.h>
-
-#include <Library/IoLib.h>
-
-#include <Drivers/PL011Uart.h>
-
-/*
-
- Programmed hardware of Serial port.
-
- @return Always return EFI_UNSUPPORTED.
-
-**/
-RETURN_STATUS
-EFIAPI
-PL011UartInitialize (
- IN UINTN UartBase,
- IN UINTN BaudRate,
- IN UINTN LineControl
- )
-{
- if (BaudRate == 115200) {
- // Initialize baud rate generator
- MmioWrite32 (UartBase + UARTIBRD, UART_115200_IDIV);
- MmioWrite32 (UartBase + UARTFBRD, UART_115200_FDIV);
- } else if (BaudRate == 38400) {
- // Initialize baud rate generator
- MmioWrite32 (UartBase + UARTIBRD, UART_38400_IDIV);
- MmioWrite32 (UartBase + UARTFBRD, UART_38400_FDIV);
- } else if (BaudRate == 19200) {
- // Initialize baud rate generator
- MmioWrite32 (UartBase + UARTIBRD, UART_19200_IDIV);
- MmioWrite32 (UartBase + UARTFBRD, UART_19200_FDIV);
- } else {
- return EFI_INVALID_PARAMETER;
- }
-
- // No parity, 1 stop, no fifo, 8 data bits
- MmioWrite32 (UartBase + UARTLCR_H, LineControl);
-
- // Clear any pending errors
- MmioWrite32 (UartBase + UARTECR, 0);
-
- // Enable tx, rx, and uart overall
- MmioWrite32 (UartBase + UARTCR, PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);
-
- return EFI_SUCCESS;
-}
-
-/**
- Write data to serial device.
-
- @param Buffer Point of data buffer which need to be written.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Write data failed.
- @retval !0 Actual number of bytes written to serial device.
-
-**/
-UINTN
-EFIAPI
-PL011UartWrite (
- IN UINTN UartBase,
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
- )
-{
- UINTN Count;
-
- for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
- while ((MmioRead32 (UartBase + UARTFR) & UART_TX_EMPTY_FLAG_MASK) == 0);
- MmioWrite8 (UartBase + UARTDR, *Buffer);
- }
-
- return NumberOfBytes;
-}
-
-/**
- Read data from serial device and save the data in buffer.
-
- @param Buffer Point of data buffer which need to be written.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Read data failed.
- @retval !0 Actual number of bytes read from serial device.
-
-**/
-UINTN
-EFIAPI
-PL011UartRead (
- IN UINTN UartBase,
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
- )
-{
- UINTN Count;
-
- for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
- while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);
- *Buffer = MmioRead8 (UartBase + UARTDR);
- }
-
- return NumberOfBytes;
-}
-
-/**
- Check to see if any data is available to be read from the debug device.
-
- @retval EFI_SUCCESS At least one byte of data is available to be read
- @retval EFI_NOT_READY No data is available to be read
- @retval EFI_DEVICE_ERROR The serial device is not functioning properly
-
-**/
-BOOLEAN
-EFIAPI
-PL011UartPoll (
- IN UINTN UartBase
- )
-{
- return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);
-}
+/** @file\r
+ Serial I/O Port library functions with no library constructor/destructor\r
+\r
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r
+ \r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Drivers/PL011Uart.h>\r
+\r
+/*\r
+\r
+ Initialise the serial port to the specified settings.\r
+ All unspecified settings will be set to the default values.\r
+\r
+ @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartInitializePort (\r
+ IN UINTN UartBase,\r
+ IN UINT64 BaudRate,\r
+ IN UINT32 ReceiveFifoDepth,\r
+ IN UINT32 Timeout,\r
+ IN EFI_PARITY_TYPE Parity,\r
+ IN UINT8 DataBits,\r
+ IN EFI_STOP_BITS_TYPE StopBits\r
+ )\r
+{\r
+ UINT32 LineControl;\r
+ UINT32 Divisor;\r
+\r
+ // The BaudRate must be passed\r
+ if (BaudRate == 0) {\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+ \r
+ LineControl = 0;\r
+\r
+ // The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept\r
+ // 1 char buffer as the minimum fifo size. Because everything can be rounded down,\r
+ // there is no maximum fifo size.\r
+ if (ReceiveFifoDepth == 0) {\r
+ LineControl |= PL011_UARTLCR_H_FEN;\r
+ } else if (ReceiveFifoDepth < 32) {\r
+ // Nothing else to do. 1 byte fifo is default.\r
+ } else if (ReceiveFifoDepth >= 32) {\r
+ LineControl |= PL011_UARTLCR_H_FEN;\r
+ }\r
+\r
+ //\r
+ // Parity\r
+ //\r
+ switch (Parity) {\r
+ case DefaultParity:\r
+ case NoParity:\r
+ // Nothing to do. Parity is disabled by default.\r
+ break;\r
+ case EvenParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_EPS);\r
+ break;\r
+ case OddParity:\r
+ LineControl |= PL011_UARTLCR_H_PEN;\r
+ break;\r
+ case MarkParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS | PL011_UARTLCR_H_EPS);\r
+ break;\r
+ case SpaceParity:\r
+ LineControl |= (PL011_UARTLCR_H_PEN | PL011_UARTLCR_H_SPS);\r
+ break;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Data Bits\r
+ //\r
+ switch (DataBits) {\r
+ case 0:\r
+ case 8:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_8;\r
+ break;\r
+ case 7:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_7;\r
+ break;\r
+ case 6:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_6;\r
+ break;\r
+ case 5:\r
+ LineControl |= PL011_UARTLCR_H_WLEN_5;\r
+ break;\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Stop Bits\r
+ //\r
+ switch (StopBits) {\r
+ case DefaultStopBits:\r
+ case OneStopBit:\r
+ // Nothing to do. One stop bit is enabled by default.\r
+ break;\r
+ case TwoStopBits:\r
+ LineControl |= PL011_UARTLCR_H_STP2;\r
+ break;\r
+ case OneFiveStopBits:\r
+ // Only 1 or 2 stops bits are supported\r
+ default:\r
+ return RETURN_INVALID_PARAMETER;\r
+ }\r
+ \r
+ // Don't send the LineControl value to the PL011 yet,\r
+ // wait until after the Baud Rate setting.\r
+ // This ensures we do not mess up the UART settings halfway through\r
+ // in the rare case when there is an error with the Baud Rate.\r
+\r
+ //\r
+ // Baud Rate\r
+ //\r
+ if (PcdGet32(PL011UartInteger) != 0) {\r
+ // Integer and Factional part must be different of 0\r
+ ASSERT(PcdGet32(PL011UartFractional) != 0);\r
+ \r
+ MmioWrite32 (UartBase + UARTIBRD, PcdGet32(PL011UartInteger));\r
+ MmioWrite32 (UartBase + UARTFBRD, PcdGet32(PL011UartFractional));\r
+ } else {\r
+ Divisor = (PcdGet32 (PL011UartClkInHz) * 4) / BaudRate;\r
+ MmioWrite32 (UartBase + UARTIBRD, Divisor >> 6);\r
+ MmioWrite32 (UartBase + UARTFBRD, Divisor & 0x3F);\r
+ }\r
+\r
+ // No parity, 1 stop, no fifo, 8 data bits\r
+ MmioWrite32 (UartBase + UARTLCR_H, LineControl);\r
+\r
+ // Clear any pending errors\r
+ MmioWrite32 (UartBase + UARTECR, 0);\r
+\r
+ // Enable tx, rx, and uart overall\r
+ MmioWrite32 (UartBase + UARTCR, PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN);\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Set the serial device control bits.\r
+\r
+ @param UartBase The base address of the PL011 UART.\r
+ @param Control Control bits which are to be set on the serial device.\r
+\r
+ @retval EFI_SUCCESS The new control bits were set on the serial device.\r
+ @retval EFI_UNSUPPORTED The serial device does not support this operation.\r
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartSetControl (\r
+ IN UINTN UartBase,\r
+ IN UINT32 Control\r
+ )\r
+{\r
+ UINT32 Bits;\r
+ UINT32 ValidControlBits;\r
+\r
+ ValidControlBits = ( EFI_SERIAL_REQUEST_TO_SEND\r
+ | EFI_SERIAL_DATA_TERMINAL_READY\r
+ // | EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE // Not implemented yet.\r
+ // | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE // Not implemented yet.\r
+ | EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE\r
+ );\r
+\r
+ if (Control & (~ValidControlBits)) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ Bits = MmioRead32 (UartBase + UARTCR);\r
+\r
+ if (Control & EFI_SERIAL_REQUEST_TO_SEND) {\r
+ Bits |= PL011_UARTCR_RTS;\r
+ }\r
+\r
+ if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {\r
+ Bits |= PL011_UARTCR_DTR;\r
+ }\r
+\r
+ if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {\r
+ Bits |= PL011_UARTCR_LBE;\r
+ }\r
+\r
+ if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {\r
+ Bits |= (PL011_UARTCR_CTSEN & PL011_UARTCR_RTSEN);\r
+ }\r
+\r
+ MmioWrite32 (UartBase + UARTCR, Bits);\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Get the serial device control bits.\r
+\r
+ @param UartBase The base address of the PL011 UART.\r
+ @param Control Control signals read from the serial device.\r
+\r
+ @retval EFI_SUCCESS The control bits were read from the serial device.\r
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartGetControl (\r
+ IN UINTN UartBase,\r
+ OUT UINT32 *Control\r
+ )\r
+{\r
+ UINT32 FlagRegister;\r
+ UINT32 ControlRegister;\r
+\r
+\r
+ FlagRegister = MmioRead32 (UartBase + UARTFR);\r
+ ControlRegister = MmioRead32 (UartBase + UARTCR);\r
+\r
+ *Control = 0;\r
+\r
+ if ((FlagRegister & PL011_UARTFR_CTS) == PL011_UARTFR_CTS) {\r
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_DSR) == PL011_UARTFR_DSR) {\r
+ *Control |= EFI_SERIAL_DATA_SET_READY;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_RI) == PL011_UARTFR_RI) {\r
+ *Control |= EFI_SERIAL_RING_INDICATE;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_DCD) == PL011_UARTFR_DCD) {\r
+ *Control |= EFI_SERIAL_CARRIER_DETECT;\r
+ }\r
+\r
+ if ((ControlRegister & PL011_UARTCR_RTS) == PL011_UARTCR_RTS) {\r
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;\r
+ }\r
+\r
+ if ((ControlRegister & PL011_UARTCR_DTR) == PL011_UARTCR_DTR) {\r
+ *Control |= EFI_SERIAL_DATA_TERMINAL_READY;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_RXFE) == PL011_UARTFR_RXFE) {\r
+ *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;\r
+ }\r
+\r
+ if ((FlagRegister & PL011_UARTFR_TXFE) == PL011_UARTFR_TXFE) {\r
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;\r
+ }\r
+\r
+ if ((ControlRegister & (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) == (PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN)) {\r
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;\r
+ }\r
+\r
+#ifdef NEVER\r
+ // ToDo: Implement EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE\r
+ if ((ControlRegister & PL011_UARTCR_LBE) == PL011_UARTCR_LBE) {\r
+ *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;\r
+ }\r
+\r
+ // ToDo: Implement EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE\r
+ if (SoftwareLoopbackEnable) {\r
+ *Control |= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE;\r
+ }\r
+#endif\r
+\r
+ return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Write data to serial device.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Write data failed.\r
+ @retval !0 Actual number of bytes written to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PL011UartWrite (\r
+ IN UINTN UartBase,\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
+{\r
+ UINTN Count;\r
+\r
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_TX_EMPTY_FLAG_MASK) == 0);\r
+ MmioWrite8 (UartBase + UARTDR, *Buffer);\r
+ }\r
+\r
+ return NumberOfBytes;\r
+}\r
+\r
+/**\r
+ Read data from serial device and save the data in buffer.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Read data failed.\r
+ @retval !0 Actual number of bytes read from serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PL011UartRead (\r
+ IN UINTN UartBase,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
+{\r
+ UINTN Count;\r
+\r
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {\r
+ while ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) != 0);\r
+ *Buffer = MmioRead8 (UartBase + UARTDR);\r
+ }\r
+\r
+ return NumberOfBytes;\r
+}\r
+\r
+/**\r
+ Check to see if any data is available to be read from the debug device.\r
+\r
+ @retval EFI_SUCCESS At least one byte of data is available to be read\r
+ @retval EFI_NOT_READY No data is available to be read\r
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PL011UartPoll (\r
+ IN UINTN UartBase\r
+ )\r
+{\r
+ return ((MmioRead32 (UartBase + UARTFR) & UART_RX_EMPTY_FLAG_MASK) == 0);\r
+}\r
-#/** @file
-#
-# Component description file for PL011Uart module
-#
-# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PL011Uart
- FILE_GUID = 4ec8b120-8307-11e0-bc91-0002a5d5c51b
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PL011UartLib
-
-[Sources.common]
- PL011Uart.c
-
-[LibraryClasses]
- IoLib
-
-[Packages]
- MdePkg/MdePkg.dec
-# MdeModulePkg/MdeModulePkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[Pcd]
+#/** @file\r
+# \r
+# Component description file for PL011Uart module\r
+# \r
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+# \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL011Uart\r
+ FILE_GUID = 4ec8b120-8307-11e0-bc91-0002a5d5c51b \r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PL011UartLib\r
+\r
+[Sources.common]\r
+ PL011Uart.c\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ IoLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[Pcd]\r
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz\r
+ gArmPlatformTokenSpaceGuid.PL011UartInteger\r
+ gArmPlatformTokenSpaceGuid.PL011UartFractional\r
-/** @file
-*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __PL011_UART_H__
-#define __PL011_UART_H__
-
-// PL011 Registers
-#define UARTDR 0x000
-#define UARTRSR 0x004
-#define UARTECR 0x004
-#define UARTFR 0x018
-#define UARTILPR 0x020
-#define UARTIBRD 0x024
-#define UARTFBRD 0x028
-#define UARTLCR_H 0x02C
-#define UARTCR 0x030
-#define UARTIFLS 0x034
-#define UARTIMSC 0x038
-#define UARTRIS 0x03C
-#define UARTMIS 0x040
-#define UARTICR 0x044
-#define UARTDMACR 0x048
-
-#define UART_115200_IDIV 13 // Integer Part
-#define UART_115200_FDIV 1 // Fractional Part
-#define UART_38400_IDIV 39
-#define UART_38400_FDIV 5
-#define UART_19200_IDIV 12
-#define UART_19200_FDIV 37
-
-// Data status bits
-#define UART_DATA_ERROR_MASK 0x0F00
-
-// Status reg bits
-#define UART_STATUS_ERROR_MASK 0x0F
-
-// Flag reg bits
-#define UART_TX_EMPTY_FLAG_MASK 0x80
-#define UART_RX_FULL_FLAG_MASK 0x40
-#define UART_TX_FULL_FLAG_MASK 0x20
-#define UART_RX_EMPTY_FLAG_MASK 0x10
-#define UART_BUSY_FLAG_MASK 0x08
-
-// Control reg bits
-#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable
-#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable
-#define PL011_UARTCR_RTS (1 << 11) // Request to send
-#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.
-#define PL011_UARTCR_RXE (1 << 9) // Receive enable
-#define PL011_UARTCR_TXE (1 << 8) // Transmit enable
-#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable
-
-// Line Control Register Bits
-#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select
-#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
-#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
-#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
-#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
-#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable
-#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select
-#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select
-#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
-#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
-
-/*
-
- Programmed hardware of Serial port.
-
- @return Always return EFI_UNSUPPORTED.
-
-**/
-RETURN_STATUS
-EFIAPI
-PL011UartInitialize (
- IN UINTN UartBase,
- IN UINTN BaudRate,
- IN UINTN LineControl
- );
-
-/**
- Write data to serial device.
-
- @param Buffer Point of data buffer which need to be writed.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Write data failed.
- @retval !0 Actual number of bytes writed to serial device.
-
-**/
-UINTN
-EFIAPI
-PL011UartWrite (
- IN UINTN UartBase,
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
- );
-
-/**
- Read data from serial device and save the datas in buffer.
-
- @param Buffer Point of data buffer which need to be writed.
- @param NumberOfBytes Number of output bytes which are cached in Buffer.
-
- @retval 0 Read data failed.
- @retval !0 Aactual number of bytes read from serial device.
-
-**/
-UINTN
-EFIAPI
-PL011UartRead (
- IN UINTN UartBase,
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
- );
-
-/**
- Check to see if any data is avaiable to be read from the debug device.
-
- @retval EFI_SUCCESS At least one byte of data is avaiable to be read
- @retval EFI_NOT_READY No data is avaiable to be read
- @retval EFI_DEVICE_ERROR The serial device is not functioning properly
-
-**/
-BOOLEAN
-EFIAPI
-PL011UartPoll (
- IN UINTN UartBase
- );
-
-#endif
+/** @file\r
+*\r
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#ifndef __PL011_UART_H__\r
+#define __PL011_UART_H__\r
+\r
+#include <Uefi.h>\r
+#include <Protocol/SerialIo.h>\r
+\r
+// PL011 Registers\r
+#define UARTDR 0x000\r
+#define UARTRSR 0x004\r
+#define UARTECR 0x004\r
+#define UARTFR 0x018\r
+#define UARTILPR 0x020\r
+#define UARTIBRD 0x024\r
+#define UARTFBRD 0x028\r
+#define UARTLCR_H 0x02C\r
+#define UARTCR 0x030\r
+#define UARTIFLS 0x034\r
+#define UARTIMSC 0x038\r
+#define UARTRIS 0x03C\r
+#define UARTMIS 0x040\r
+#define UARTICR 0x044\r
+#define UARTDMACR 0x048\r
+\r
+// Data status bits\r
+#define UART_DATA_ERROR_MASK 0x0F00\r
+\r
+// Status reg bits\r
+#define UART_STATUS_ERROR_MASK 0x0F\r
+\r
+// Flag reg bits\r
+#define PL011_UARTFR_RI (1 << 8) // Ring indicator\r
+#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
+#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
+#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
+#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
+#define PL011_UARTFR_BUSY (1 << 3) // UART busy\r
+#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
+#define PL011_UARTFR_DSR (1 << 1) // Data set ready\r
+#define PL011_UARTFR_CTS (1 << 0) // Clear to send\r
+\r
+// Flag reg bits - alternative names\r
+#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r
+#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r
+#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r
+#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r
+#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r
+\r
+// Control reg bits\r
+#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r
+#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r
+#define PL011_UARTCR_RTS (1 << 11) // Request to send\r
+#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r
+#define PL011_UARTCR_RXE (1 << 9) // Receive enable\r
+#define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r
+#define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r
+#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r
+\r
+// Line Control Register Bits\r
+#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r
+#define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r
+#define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r
+#define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r
+#define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r
+#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r
+#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r
+#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r
+#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r
+#define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r
+\r
+/*\r
+\r
+ Programmed hardware of Serial port.\r
+\r
+ @return Always return EFI_UNSUPPORTED.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartInitializePort (\r
+ IN UINTN UartBase,\r
+ IN UINT64 BaudRate,\r
+ IN UINT32 ReceiveFifoDepth,\r
+ IN UINT32 Timeout,\r
+ IN EFI_PARITY_TYPE Parity,\r
+ IN UINT8 DataBits,\r
+ IN EFI_STOP_BITS_TYPE StopBits\r
+ );\r
+\r
+/**\r
+ Set the serial device control bits.\r
+\r
+ @param UartBase The base address of the PL011 UART.\r
+ @param Control Control bits which are to be set on the serial device.\r
+\r
+ @retval EFI_SUCCESS The new control bits were set on the serial device.\r
+ @retval EFI_UNSUPPORTED The serial device does not support this operation.\r
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartSetControl (\r
+ IN UINTN UartBase,\r
+ IN UINT32 Control\r
+ );\r
+\r
+/**\r
+ Get the serial device control bits.\r
+\r
+ @param UartBase The base address of the PL011 UART.\r
+ @param Control Control signals read from the serial device.\r
+\r
+ @retval EFI_SUCCESS The control bits were read from the serial device.\r
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PL011UartGetControl (\r
+ IN UINTN UartBase,\r
+ OUT UINT32 *Control\r
+ );\r
+\r
+/**\r
+ Write data to serial device.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Write data failed.\r
+ @retval !0 Actual number of bytes written to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PL011UartWrite (\r
+ IN UINTN UartBase,\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ );\r
+\r
+/**\r
+ Read data from serial device and save the data in buffer.\r
+\r
+ @param Buffer Point of data buffer which need to be written.\r
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.\r
+\r
+ @retval 0 Read data failed.\r
+ @retval !0 Actual number of bytes read from serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PL011UartRead (\r
+ IN UINTN UartBase,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ );\r
+\r
+/**\r
+ Check to see if any data is available to be read from the debug device.\r
+\r
+ @retval EFI_SUCCESS At least one byte of data is available to be read\r
+ @retval EFI_NOT_READY No data is available to be read\r
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PL011UartPoll (\r
+ IN UINTN UartBase\r
+ );\r
+\r
+#endif\r
/** @file
Serial I/O Port library functions with no library constructor/destructor
-
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
**/
-#include <Include/Uefi.h>
+#include <Include/Base.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
Programmed hardware of Serial port.
- @return Always return EFI_UNSUPPORTED.
+ @return Always return RETURN_UNSUPPORTED.
**/
RETURN_STATUS
VOID
)
{
- // No parity, 1 stop, no fifo, 8 data bits
- return PL011UartInitialize (
+ return PL011UartInitializePort (
(UINTN)PcdGet64 (PcdSerialRegisterBase),
(UINTN)PcdGet64 (PcdUartDefaultBaudRate),
- PL011_UARTLCR_H_WLEN_8);
+ 0, // Use the default value for Fifo depth
+ 0, // Use the default value for Timeout,
+ (EFI_PARITY_TYPE)PcdGet8 (PcdUartDefaultParity),
+ PcdGet8 (PcdUartDefaultDataBits),
+ (EFI_STOP_BITS_TYPE) PcdGet8 (PcdUartDefaultStopBits));
}
/**
Write data to serial device.
- @param Buffer Point of data buffer which need to be writed.
+ @param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Write data failed.
- @retval !0 Actual number of bytes writed to serial device.
+ @retval !0 Actual number of bytes written to serial device.
**/
UINTN
}
/**
- Read data from serial device and save the datas in buffer.
+ Read data from serial device and save the data in buffer.
- @param Buffer Point of data buffer which need to be writed.
+ @param Buffer Point of data buffer which need to be written.
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
- @retval !0 Aactual number of bytes read from serial device.
+ @retval !0 Actual number of bytes read from serial device.
**/
UINTN
}
/**
- Check to see if any data is avaiable to be read from the debug device.
+ Check to see if any data is available to be read from the debug device.
- @retval EFI_SUCCESS At least one byte of data is avaiable to be read
- @retval EFI_NOT_READY No data is avaiable to be read
+ @retval EFI_SUCCESS At least one byte of data is available to be read
+ @retval EFI_NOT_READY No data is available to be read
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
**/
-#/** @file
-#
-# Component discription file for NorFlashDxe module
-#
-# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PL011SerialPortLib
- FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SerialPortLib
-
-[Sources.common]
- PL011SerialPortLib.c
-
-[LibraryClasses]
- PL011UartLib
- PcdLib
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+#/** @file\r
+# \r
+# Component description file for PL011SerialPortLib module\r
+# \r
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+# \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL011SerialPortLib\r
+ FILE_GUID = 8ecefc8f-a2c4-4091-b80f-20f7aeb0567f \r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = SerialPortLib\r
+\r
+[Sources.common]\r
+ PL011SerialPortLib.c\r
+\r
+[LibraryClasses]\r
+ PL011UartLib\r
+ PcdLib\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
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