--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Silvermont microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.\r
+\r
+**/\r
+\r
+#ifndef __SILVERMONT_MSR_H__\r
+#define __SILVERMONT_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Shared. Model Specific Platform ID (R).\r
+\r
+ @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
+ ///\r
+ UINT32 MaximumQualifiedRatio:5;\r
+ UINT32 Reserved2:19;\r
+ UINT32 Reserved3:18;\r
+ ///\r
+ /// [Bits 52:50] See Table 35-2.\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ UINT32 Reserved4:11;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
+ processor features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
+ ///\r
+ UINT32 AERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r
+ /// Disabled Always 0.\r
+ ///\r
+ UINT32 BERR_Enable:1;\r
+ UINT32 Reserved2:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 AERR_ObservationEnabled:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
+ /// Always 0.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
+ ///\r
+ UINT32 IntegerBusFrequencyRatio:5;\r
+ UINT32 Reserved9:5;\r
+ UINT32 Reserved10:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Core. SMI Counter (R/O).\r
+\r
+ @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
+ /// RESET.\r
+ ///\r
+ UINT32 SMICount:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_SMI_COUNT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the source instruction for one of the last eight\r
+ branches, exceptions, or interrupts taken by the processor. See also: -\r
+ Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
+ Interrupt, and Exception Recording (Pentium M Processors).".\r
+\r
+ @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
+#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
+#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
+#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
+/// @}\r
+\r
+\r
+/**\r
+ Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the destination instruction for one of the last eight\r
+ branches, exceptions, or interrupts taken by the processor.\r
+\r
+ @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
+#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
+#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
+#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
+/// @}\r
+\r
+\r
+/**\r
+ Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
+ bus clock speed for processors based on Silvermont microarchitecture:.\r
+\r
+ @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Scalable Bus Speed\r
+ ///\r
+ /// Silvermont Processor Family\r
+ /// ---------------------------\r
+ /// 100B: 080.0 MHz\r
+ /// 000B: 083.3 MHz\r
+ /// 001B: 100.0 MHz\r
+ /// 010B: 133.3 MHz\r
+ /// 011B: 116.7 MHz\r
+ ///\r
+ /// Airmont Processor Family\r
+ /// ---------------------------\r
+ /// 0000B: 083.3 MHz\r
+ /// 0001B: 100.0 MHz\r
+ /// 0010B: 133.3 MHz\r
+ /// 0011B: 116.7 MHz\r
+ /// 0100B: 080.0 MHz\r
+ /// 0101B: 093.3 MHz\r
+ /// 0110B: 090.0 MHz\r
+ /// 0111B: 088.9 MHz\r
+ /// 1000B: 087.5 MHz\r
+ ///\r
+ UINT32 ScalableBusSpeed:4;\r
+ UINT32 Reserved1:28;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. C-State Configuration Control (R/W) Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI CStates. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power). for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
+ /// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
+ /// IO_read instructions sent to IO register specified by\r
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
+ /// until next reset.\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:16;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Power Management IO Redirection in C-state (R/W) See\r
+ http://biosbits.org.\r
+\r
+ @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r
+ /// visible to software for IO redirection. If IO MWAIT Redirection is\r
+ /// enabled, reads to this address will be consumed by the power\r
+ /// management logic and decoded to MWAIT instructions. When IO port\r
+ /// address redirection is enabled, this is the IO port address reported\r
+ /// to the OS/software.\r
+ ///\r
+ UINT32 Lvl2Base:16;\r
+ ///\r
+ /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
+ /// maximum C-State code name to be included when IO read to MWAIT\r
+ /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r
+ /// is the max C-State to include 110b - C6 is the max C-State to include\r
+ /// 111b - C7 is the max C-State to include.\r
+ ///\r
+ UINT32 CStateRange:3;\r
+ UINT32 Reserved1:13;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
+ /// Indicates if the L2 is hardware-disabled.\r
+ ///\r
+ UINT32 L2HardwareEnabled:1;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
+ /// Disabled (default) Until this bit is set the processor will not\r
+ /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ UINT32 Reserved2:14;\r
+ ///\r
+ /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
+ ///\r
+ UINT32 L2NotPresent:1;\r
+ UINT32 Reserved3:8;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+ handler to handle unsuccessful read of this MSR.\r
+\r
+ @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
+ /// MSR, the configuration of AES instruction set availability is as\r
+ /// follows: 11b: AES instructions are not available until next RESET.\r
+ /// otherwise, AES instructions are available. Note, AES instruction set\r
+ /// is not available if read is unsuccessful. If the configuration is not\r
+ /// 01b, AES instruction can be mis-configured if a privileged agent\r
+ /// unintentionally writes 11b.\r
+ ///\r
+ UINT32 AESConfiguration:2;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 35-2.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:3;\r
+ ///\r
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table\r
+ /// 35-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved4:3;\r
+ ///\r
+ /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 35-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ UINT32 Reserved6:3;\r
+ ///\r
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:3;\r
+ ///\r
+ /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors\r
+ /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
+ /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
+ /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
+ /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
+ /// the power-on default value is used by BIOS to detect hardware support\r
+ /// of turbo mode. If power-on default value is 1, turbo mode is available\r
+ /// in the processor. If power-on default value is 0, turbo mode is not\r
+ /// available.\r
+ ///\r
+ UINT32 TurboModeDisable:1;\r
+ UINT32 Reserved10:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r
+ /// PROCHOT# activation temperature in degree C, The effective temperature\r
+ /// for thermal throttling or PROCHOT# activation is "Temperature Target"\r
+ /// + "Target Offset".\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r
+ /// adjust the throttling and PROCHOT# activation temperature from the\r
+ /// default target specified in TEMPERATURE_TARGET (bits 23:16).\r
+ ///\r
+ UINT32 TargetOffset:6;\r
+ UINT32 Reserved2:2;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
+\r
+\r
+/**\r
+ Shared. Offcore Response Event Select Register (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode (RW).\r
+\r
+ @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
+ /// limit of 7 core active.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
+ /// limit of 8 core active.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r
+ points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
+\r
+ @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Core. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Core. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
+ Facilities.".\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+\r
+\r
+/**\r
+ Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ (PEBS).".\r
+\r
+ @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 PEBS:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
+ Residency Counter. (R/O) Value since last reset that this package is in\r
+ processor-specific C6 states. Counts at the TSC Frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C6 states. Counts at the TSC Frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_SILVERMONT_MCi_CTL\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_MC3_CTL 0x0000040C\r
+#define MSR_SILVERMONT_MC4_CTL 0x00000410\r
+#define MSR_SILVERMONT_MC5_CTL 0x00000414\r
+/// @}\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_SILVERMONT_MCi_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_MC3_STATUS 0x0000040D\r
+#define MSR_SILVERMONT_MC4_STATUS 0x00000411\r
+#define MSR_SILVERMONT_MC5_STATUS 0x00000415\r
+/// @}\r
+\r
+\r
+/**\r
+ Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register\r
+ is either not implemented or contains no address if the ADDRV flag in the\r
+ MSR_MCi_STATUS register is clear. When not implemented in the processor, all\r
+ reads and writes to this MSR will cause a general-protection exception.\r
+\r
+ @param ECX MSR_SILVERMONT_MCi_ADDR\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_SILVERMONT_MC3_ADDR 0x0000040E\r
+#define MSR_SILVERMONT_MC4_ADDR 0x00000412\r
+#define MSR_SILVERMONT_MC5_ADDR 0x00000416\r
+/// @}\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
+\r
+\r
+/**\r
+ Core. Capability Reporting Register of VM-function Controls (R/O) See Table\r
+ 35-2.\r
+\r
+ @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
+\r
+\r
+/**\r
+ Core. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1\r
+ Residency Counter. (R/O) Value since last reset that this core is in\r
+ processor-specific C1 states. Counts at the TSC frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
+ "RAPL Interfaces.".\r
+\r
+ @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Power Units. Power related information (in milliWatts) is\r
+ /// based on the multiplier, 2^PU; where PU is an unsigned integer\r
+ /// represented by bits 3:0. Default value is 0101b, indicating power unit\r
+ /// is in 32 milliWatts increment.\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Energy Status Units. Energy related information (in\r
+ /// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 00101b,\r
+ /// indicating energy unit is in 32 microJoules increment.\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r
+ /// one second.\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Power Limit Control (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package\r
+ /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+ ///\r
+ UINT32 Limit:15;\r
+ ///\r
+ /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r
+ /// RAPL Domain.".\r
+ ///\r
+ UINT32 Enable:1;\r
+ ///\r
+ /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r
+ /// "Package RAPL Domain.".\r
+ ///\r
+ UINT32 ClampingLimit:1;\r
+ ///\r
+ /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r
+ /// If 0 is specified in bits [23:17], defaults to 1 second window.\r
+ ///\r
+ UINT32 Time:7;\r
+ UINT32 Reserved1:8;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
+ and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
+\r
+\r
+/**\r
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
+ Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+\r
+ @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r
+ policy. Writing a value of 0 disables core level HW demotion policy.\r
+\r
+ @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
+\r
+\r
+/**\r
+ Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r
+ cores sharing the second-level cache) C6 demotion policy. Writing a value of\r
+ 0 disables module level HW demotion policy.\r
+\r
+ @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
+\r
+\r
+/**\r
+ Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI CStates. Time that this module is in module-specific C6 states since\r
+ last reset. Counts at 1 Mhz frequency.\r
+\r
+ @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
+\r
+\r
+/**\r
+ Package. PKG RAPL Parameter (R/0).\r
+\r
+ @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is\r
+ /// the equivalent of thermal specification power of the package domain.\r
+ /// The unit of this field is specified by the "Power Units" field of\r
+ /// MSR_RAPL_POWER_UNIT.\r
+ ///\r
+ UINT32 ThermalSpecPower:15;\r
+ UINT32 Reserved1:17;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Package. PP0 RAPL Power Limit Control (R/W).\r
+\r
+ @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
+ /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.\r
+ ///\r
+ UINT32 Limit:15;\r
+ ///\r
+ /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
+ /// RAPL Domains.".\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r
+ /// duration over which the average power must remain below\r
+ /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time\r
+ /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time\r
+ /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.\r
+ /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35\r
+ /// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r
+ /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r
+ ///\r
+ UINT32 Time:7;\r
+ UINT32 Reserved2:8;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r
+\r
+#endif\r
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