ArmPlatformPkg/PL34xDmc: Remove DMC base address from the DMC configuration

By removing the DMC Base Address from the structure, we can reuse the same DMC
configuration for two similar DMC controllers.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11960 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
index 17d09a605a07f7bbe5cff1f1782fae635c8c034c..644842f6d6ee8bbafe6af6bf2db56eed37995e12 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
@@ -29,16 +29,14 @@
 
 // DDR2 timings
 PL341_DMC_CONFIG DDRTimings = {
-  .base   = ARM_VE_DMC_BASE,
-  .phy_ctrl_base  = 0x0,  //There is no DDR2 PHY controller on CTA9 test chip
   .MaxChip   = 1,
   .IsUserCfg = TRUE,
   .User0Cfg = 0x7C924924,
   .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
   .HasQos    = TRUE,
-  .refresh_prd  = 0x3D0,
-  .cas_latency  = 0x8,
-  .write_latency  = 0x3,
+  .RefreshPeriod  = 0x3D0,
+  .CasLatency  = 0x8,
+  .WriteLatency  = 0x3,
   .t_mrd    = 0x2,
   .t_ras    = 0xA,
   .t_rc   = 0xE,
@@ -153,6 +151,6 @@ ArmPlatformInitializeSystemMemory (
   VOID
   )
 {
-  PL341DmcInit(&DDRTimings);
+  PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
   PL301AxiInit(ARM_VE_FAXI_BASE);
 }

diff --git a/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c b/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c
index ae94def7656189019ecce611cf6af1d89aa825b2..95f59eb6619f7602477a2f1c86d5e02b7c455544 100644 (file)
--- a/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c
+++ b/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c
@@ -12,8 +12,11 @@
 *\r
 **/\r
 \r
+#include <Uefi.h>\r
+\r
 #include <Library/IoLib.h>\r
 #include <Library/DebugLib.h>\r
+\r
 #include <Drivers/PL341Dmc.h>\r
 \r
 // Macros for writing to DDR2 controller.\r
@@ -27,15 +30,13 @@
 // Initialise PL341 Dynamic Memory Controller\r
 VOID\r
 PL341DmcInit (\r
-  IN  PL341_DMC_CONFIG *DmcConfig\r
+  IN  UINTN             DmcBase,\r
+  IN  PL341_DMC_CONFIG* DmcConfig\r
   )\r
 {\r
-  UINTN DmcBase;\r
   UINTN Index;\r
   UINT32 Chip;\r
 \r
-  DmcBase = DmcConfig->base;\r
-\r
   // Set config mode\r
   DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r
 \r
@@ -67,9 +68,9 @@ PL341DmcInit (
   //\r
   // Initialise memory controlller\r
   //\r
-  DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);\r
-  DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);\r
-  DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);\r
+  DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->RefreshPeriod);\r
+  DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->CasLatency);\r
+  DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->WriteLatency);\r
   DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r
   DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r
   DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r
@@ -96,6 +97,9 @@ PL341DmcInit (
   // Set PL341 Memory Config 2\r
   DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r
 \r
+  // Set PL341 Memory Config 3\r
+  DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
+\r
   // Set PL341 Chip Select <n>\r
   DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r
   DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r
@@ -107,9 +111,6 @@ PL341DmcInit (
     DmcReadReg(DMC_STATUS_REG);\r
   }\r
 \r
-  // Set PL341 Memory Config 3\r
-  DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
-\r
   if (DmcConfig->IsUserCfg) {\r
     //\r
     // Set Test Chip PHY Registers via PL341 User Config Reg\r
@@ -210,6 +211,11 @@ PL341DmcInit (
     // Set (EMR) extended mode register - OCD Exit\r
     DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
         (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
+\r
+    // Delay\r
+    for (Index = 0; Index < 10; Index++) {\r
+      DmcReadReg(DMC_STATUS_REG);\r
+    }\r
   }\r
 \r
   // Move DDR2 Controller to Ready state by issueing GO command\r

diff --git a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h
index 461ec16cc2b2a3bb4d970e7f323ecceda36fdc8b..0227ced45420b45efbfa1cc0eb5a61614a423612 100644 (file)
--- a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h
+++ b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h
@@ -17,16 +17,14 @@
 
 
 typedef struct  {
-    UINTN      base;           // base address for the controller
-    UINTN      phy_ctrl_base;  // DDR2 Phy control base
     UINTN      HasQos;        // has QoS registers
     UINTN      MaxChip;       // number of memory chips accessible
     BOOLEAN  IsUserCfg;
     UINT32  User0Cfg;
     UINT32  User2Cfg;
-    UINT32     refresh_prd;
-    UINT32     cas_latency;
-    UINT32     write_latency;
+    UINT32     RefreshPeriod;
+    UINT32     CasLatency;
+    UINT32     WriteLatency;
     UINT32     t_mrd;
     UINT32     t_ras;
     UINT32     t_rc;
@@ -245,16 +243,6 @@ typedef struct  {
 #define PHY_PTM_REFCLK_DIV_200_400MHz          0x0
 #define PHY_PTM_REFCLK_DIV_400_800MHz          0x1
 
-
-// PHY Reset in SCC
-
-#define SCC_PHY_RST_REG_OFF                            0xA0
-#define SCC_REMAP_REG_OFF                      0x00
-#define SCC_PHY_RST0_MASK                                      1               // Active LOW PHY0 reset
-#define SCC_PHY_RST0_SHFT                                      0               // Active LOW PHY0 reset
-#define SCC_PHY_RST1_MASK                                      0x100   // Active LOW PHY1 reset
-#define SCC_PHY_RST1_SHFT                                      8               // Active LOW PHY1 reset
-
 #define TC_UIOLHNC_MASK                         0x000003C0
 #define TC_UIOLHNC_SHIFT                        0x6
 #define TC_UIOLHPC_MASK                         0x0000003F
@@ -331,8 +319,10 @@ typedef struct  {
 #define DDR2_MR_WR_CYCLES_6        (5 << 9)
 
 
-VOID PL341DmcInit (
-  IN PL341_DMC_CONFIG *config
+VOID
+PL341DmcInit (
+  IN  UINTN             DmcBase,
+  IN  PL341_DMC_CONFIG* DmcConfig
   );
 
 VOID PL341DmcPhyInit (