*Mapping = Map;\r
\r
if ((((UINTN)HostAddress & (gCacheAlignment - 1)) != 0) ||\r
- ((*NumberOfBytes % gCacheAlignment) != 0)) {\r
+ ((*NumberOfBytes & (gCacheAlignment - 1)) != 0)) {\r
\r
// Get the cacheability of the region\r
Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);\r
}\r
\r
// If the mapped buffer is not an uncached buffer\r
- if ( (GcdDescriptor.Attributes != EFI_MEMORY_WC) &&\r
- (GcdDescriptor.Attributes != EFI_MEMORY_UC) )\r
- {\r
+ if ((GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) != 0) {\r
+ //\r
+ // Operations of type MapOperationBusMasterCommonBuffer are only allowed\r
+ // on uncached buffers.\r
+ //\r
+ if (Operation == MapOperationBusMasterCommonBuffer) {\r
+ DEBUG ((EFI_D_ERROR,\r
+ "%a: Operation type 'MapOperationBusMasterCommonBuffer' is only supported\n"\r
+ "on memory regions that were allocated using DmaAllocateBuffer ()\n",\r
+ __FUNCTION__));\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
//\r
// If the buffer does not fill entire cache lines we must double buffer into\r
// uncached memory. Device (PCI) address becomes uncached page.\r
return Status;\r
}\r
\r
- if ((Operation == MapOperationBusMasterRead) || (Operation == MapOperationBusMasterCommonBuffer)) {\r
+ if (Operation == MapOperationBusMasterRead) {\r
CopyMem (Buffer, HostAddress, *NumberOfBytes);\r
}\r
\r
} else {\r
Map->DoubleBuffer = FALSE;\r
\r
+ DEBUG_CODE_BEGIN ();\r
+\r
+ //\r
+ // The operation type check above only executes if the buffer happens to be\r
+ // misaligned with respect to CWG, but even if it is aligned, we should not\r
+ // allow arbitrary buffers to be used for creating consistent mappings.\r
+ // So duplicate the check here when running in DEBUG mode, just to assert\r
+ // that we are not trying to create a consistent mapping for cached memory.\r
+ //\r
+ Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ ASSERT (Operation != MapOperationBusMasterCommonBuffer ||\r
+ (GcdDescriptor.Attributes & (EFI_MEMORY_WB | EFI_MEMORY_WT)) == 0);\r
+\r
+ DEBUG_CODE_END ();\r
+\r
// Flush the Data Cache (should not have any effect if the memory region is uncached)\r
gCpu->FlushDataCache (gCpu, *DeviceAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);\r
-\r
- if ((Operation == MapOperationBusMasterRead) || (Operation == MapOperationBusMasterCommonBuffer)) {\r
- // In case the buffer is used for instance to send command to a PCI controller, we must ensure the memory is uncached\r
- Status = gDS->SetMemorySpaceAttributes (*DeviceAddress & ~(BASE_4KB - 1), ALIGN_VALUE (*NumberOfBytes, BASE_4KB), EFI_MEMORY_WC);\r
- ASSERT_EFI_ERROR (Status);\r
- }\r
}\r
\r
Map->HostAddress = (UINTN)HostAddress;\r
\r
@retval EFI_SUCCESS The range was unmapped.\r
@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
+ @retval EFI_INVALID_PARAMETER An inconsistency was detected between the mapping type\r
+ and the DoubleBuffer field\r
\r
**/\r
EFI_STATUS\r
)\r
{\r
MAP_INFO_INSTANCE *Map;\r
+ EFI_STATUS Status;\r
\r
if (Mapping == NULL) {\r
ASSERT (FALSE);\r
\r
Map = (MAP_INFO_INSTANCE *)Mapping;\r
\r
+ Status = EFI_SUCCESS;\r
if (Map->DoubleBuffer) {\r
- if ((Map->Operation == MapOperationBusMasterWrite) || (Map->Operation == MapOperationBusMasterCommonBuffer)) {\r
+ ASSERT (Map->Operation != MapOperationBusMasterCommonBuffer);\r
+\r
+ if (Map->Operation == MapOperationBusMasterCommonBuffer) {\r
+ Status = EFI_INVALID_PARAMETER;\r
+ } else if (Map->Operation == MapOperationBusMasterWrite) {\r
CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes);\r
}\r
\r
\r
FreePool (Map);\r
\r
- return EFI_SUCCESS;\r
+ return Status;\r
}\r
\r
/**\r
OUT VOID **HostAddress\r
)\r
{\r
+ VOID *Allocation;\r
+\r
if (HostAddress == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
// We used uncached memory to keep coherency\r
//\r
if (MemoryType == EfiBootServicesData) {\r
- *HostAddress = UncachedAllocatePages (Pages);\r
+ Allocation = UncachedAllocatePages (Pages);\r
} else if (MemoryType == EfiRuntimeServicesData) {\r
- *HostAddress = UncachedAllocateRuntimePages (Pages);\r
+ Allocation = UncachedAllocateRuntimePages (Pages);\r
} else {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
+ if (Allocation == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ *HostAddress = Allocation;\r
+\r
return EFI_SUCCESS;\r
}\r
\r
\r
// Convert the block entry attributes into Table descriptor attributes\r
TableAttributes = TT_TABLE_AP_NO_PERMISSION;\r
- if (Attributes & TT_PXN_MASK) {\r
- TableAttributes = TT_TABLE_PXN;\r
- }\r
- // XN maps to UXN in the EL1&0 translation regime\r
- if (Attributes & TT_XN_MASK) {\r
- TableAttributes = TT_TABLE_XN;\r
- }\r
if (Attributes & TT_NS) {\r
TableAttributes = TT_TABLE_NS;\r
}\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4007c000\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800\r
\r
# Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
\r
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x4007c000\r
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800\r
\r
# Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
UINT32 max_entries;\r
UINT32 num_entries;\r
UINT32 flags;\r
- UINT32 entry_align; \r
+ UINT32 entry_align;
UINT32 max_offset;\r
struct imd_entry entries[0];\r
};\r
UINT32 type;\r
UINT32 baseaddr;\r
UINT32 baud;\r
+ UINT32 regwidth;
+
+ // Crystal or input frequency to the chip containing the UART.
+ // Provide the board specific details to allow the payload to
+ // initialize the chip containing the UART and make independent
+ // decisions as to which dividers to select and their values
+ // to eventually arrive at the desired console baud-rate.
+ UINT32 input_hertz;
+
+ // UART PCI address: bus, device, function
+ // 1 << 31 - Valid bit, PCI UART in use
+ // Bus << 20
+ // Device << 15
+ // Function << 12
+ UINT32 uart_pci_addr;
};\r
\r
#define CB_TAG_CONSOLE 0x00010\r
IN UINT64* pLowMemorySize,\r
IN UINT64* pHighMemorySize\r
);\r
- \r
+
/**\r
Acquire the coreboot memory table with the given table id\r
\r
**/\r
RETURN_STATUS\r
CbParseCbMemTable (\r
- IN UINT32 TableId, \r
+ IN UINT32 TableId,
IN VOID** pMemTable,\r
IN UINT32* pMemTableSize\r
);\r
- \r
+
/**\r
Acquire the acpi table from coreboot\r
\r
IN VOID** pMemTable,\r
IN UINT32* pMemTableSize\r
);\r
- \r
+
/**\r
Acquire the smbios table from coreboot\r
\r
IN VOID** pMemTable,\r
IN UINT32* pMemTableSize\r
);\r
- \r
+
/**\r
Find the required fadt information\r
\r
IN UINTN* pPmEvtReg,\r
IN UINTN* pPmGpeEnReg\r
);\r
- \r
+
/**\r
Find the serial port information\r
\r
@param pRegBase Pointer to the base address of serial port registers\r
@param pRegAccessType Pointer to the access type of serial port registers\r
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate\r
+ @param pInputHertz Pointer to the input clock frequency
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address
\r
@retval RETURN_SUCCESS Successfully find the serial port information.\r
@retval RETURN_NOT_FOUND Failed to find the serial port information .\r
**/\r
RETURN_STATUS\r
CbParseSerialInfo (\r
- IN UINT32* pRegBase,\r
- IN UINT32* pRegAccessType,\r
- IN UINT32* pBaudrate\r
+ OUT UINT32 *pRegBase,
+ OUT UINT32 *pRegAccessType,
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pUartPciAddr
);\r
\r
/**\r
IN UINTN Level,\r
IN VOID** HeaderPtr\r
);\r
- \r
+
/**\r
Find the video frame buffer information\r
\r
--- /dev/null
+/** @file
+ 16550 UART Serial Port library functions
+
+ (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/SerialPortLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/PlatformHookLib.h>
+#include <Library/BaseLib.h>
+
+//
+// PCI Defintions.
+//
+#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0
+#define R_UART_TXBUF 0
+#define R_UART_BAUD_LOW 0
+#define R_UART_BAUD_HIGH 1
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE BIT0
+#define B_UART_FCR_FIFO64 BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLAB BIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_DTRC BIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY BIT0
+#define B_UART_LSR_TXRDY BIT5
+#define B_UART_LSR_TEMT BIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI BIT6
+#define B_UART_MSR_DCD BIT7
+
+//
+// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
+//
+typedef struct {
+ UINT8 Device;
+ UINT8 Function;
+ UINT16 PowerManagementStatusAndControlRegister;
+} PCI_UART_DEVICE_INFO;
+
+/**
+ Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
+ parameter Offset is added to the base address of the 16550 registers that is specified
+ by PcdSerialRegisterBase.
+
+ @param Base The base address register of UART device.
+ @param Offset The offset of the 16550 register to read.
+
+ @return The value read from the 16550 register.
+
+**/
+UINT8
+SerialPortReadRegister (
+ UINTN Base,
+ UINTN Offset
+ )
+{
+ if (PcdGetBool (PcdSerialUseMmio)) {
+ return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+ } else {
+ return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+ }
+}
+
+/**
+ Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
+ parameter Offset is added to the base address of the 16550 registers that is specified
+ by PcdSerialRegisterBase.
+
+ @param Base The base address register of UART device.
+ @param Offset The offset of the 16550 register to write.
+ @param Value The value to write to the 16550 register specified by Offset.
+
+ @return The value written to the 16550 register.
+
+**/
+UINT8
+SerialPortWriteRegister (
+ UINTN Base,
+ UINTN Offset,
+ UINT8 Value
+ )
+{
+ if (PcdGetBool (PcdSerialUseMmio)) {
+ return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
+ } else {
+ return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);
+ }
+}
+
+/**
+ Update the value of an 16-bit PCI configuration register in a PCI device. If the
+ PCI Configuration register specified by PciAddress is already programmed with a
+ non-zero value, then return the current value. Otherwise update the PCI configuration
+ register specified by PciAddress with the value specified by Value and return the
+ value programmed into the PCI configuration register. All values must be masked
+ using the bitmask specified by Mask.
+
+ @param PciAddress PCI Library address of the PCI Configuration register to update.
+ @param Value The value to program into the PCI Configuration Register.
+ @param Mask Bitmask of the bits to check and update in the PCI configuration register.
+
+**/
+UINT16
+SerialPortLibUpdatePciRegister16 (
+ UINTN PciAddress,
+ UINT16 Value,
+ UINT16 Mask
+ )
+{
+ UINT16 CurrentValue;
+
+ CurrentValue = PciRead16 (PciAddress) & Mask;
+ if (CurrentValue != 0) {
+ return CurrentValue;
+ }
+ return PciWrite16 (PciAddress, Value & Mask);
+}
+
+/**
+ Update the value of an 32-bit PCI configuration register in a PCI device. If the
+ PCI Configuration register specified by PciAddress is already programmed with a
+ non-zero value, then return the current value. Otherwise update the PCI configuration
+ register specified by PciAddress with the value specified by Value and return the
+ value programmed into the PCI configuration register. All values must be masked
+ using the bitmask specified by Mask.
+
+ @param PciAddress PCI Library address of the PCI Configuration register to update.
+ @param Value The value to program into the PCI Configuration Register.
+ @param Mask Bitmask of the bits to check and update in the PCI configuration register.
+
+ @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
+
+**/
+UINT32
+SerialPortLibUpdatePciRegister32 (
+ UINTN PciAddress,
+ UINT32 Value,
+ UINT32 Mask
+ )
+{
+ UINT32 CurrentValue;
+
+ CurrentValue = PciRead32 (PciAddress) & Mask;
+ if (CurrentValue != 0) {
+ return CurrentValue;
+ }
+ return PciWrite32 (PciAddress, Value & Mask);
+}
+
+/**
+ Retrieve the I/O or MMIO base address register for the PCI UART device.
+
+ This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
+ Device if they are not already enabled.
+
+ @return The base address register of the UART device.
+
+**/
+UINTN
+GetSerialRegisterBase (
+ VOID
+ )
+{
+ UINTN PciLibAddress;
+ UINTN BusNumber;
+ UINTN SubordinateBusNumber;
+ UINT32 ParentIoBase;
+ UINT32 ParentIoLimit;
+ UINT16 ParentMemoryBase;
+ UINT16 ParentMemoryLimit;
+ UINT32 IoBase;
+ UINT32 IoLimit;
+ UINT16 MemoryBase;
+ UINT16 MemoryLimit;
+ UINTN SerialRegisterBase;
+ UINTN BarIndex;
+ UINT32 RegisterBaseMask;
+ PCI_UART_DEVICE_INFO *DeviceInfo;
+
+ //
+ // Get PCI Device Info
+ //
+ DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
+
+ //
+ // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
+ //
+ if (DeviceInfo->Device == 0xff) {
+ return (UINTN)PcdGet64 (PcdSerialRegisterBase);
+ }
+
+ //
+ // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
+ //
+ ParentMemoryBase = 0 >> 16;
+ ParentMemoryLimit = 0xfff00000 >> 16;
+ ParentIoBase = 0 >> 12;
+ ParentIoLimit = 0xf000 >> 12;
+
+ //
+ // Enable I/O and MMIO in PCI Bridge
+ // Assume Root Bus Numer is Zero.
+ //
+ for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
+ //
+ // Compute PCI Lib Address to PCI to PCI Bridge
+ //
+ PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
+
+ //
+ // Retrieve and verify the bus numbers in the PCI to PCI Bridge
+ //
+ BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
+ if (BusNumber == 0 || BusNumber > SubordinateBusNumber) {
+ return 0;
+ }
+
+ //
+ // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
+ //
+ if (PcdGetBool (PcdSerialUseMmio)) {
+ MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
+ MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0;
+
+ //
+ // If PCI Bridge MMIO window is disabled, then return 0
+ //
+ if (MemoryLimit < MemoryBase) {
+ return 0;
+ }
+
+ //
+ // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
+ //
+ if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) {
+ return 0;
+ }
+ ParentMemoryBase = MemoryBase;
+ ParentMemoryLimit = MemoryLimit;
+ } else {
+ IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
+ if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
+ IoLimit = IoLimit >> 4;
+ } else {
+ IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
+ }
+ IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
+ if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
+ IoBase = IoBase >> 4;
+ } else {
+ IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
+ }
+
+ //
+ // If PCI Bridge I/O window is disabled, then return 0
+ //
+ if (IoLimit < IoBase) {
+ return 0;
+ }
+
+ //
+ // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
+ //
+ if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {
+ return 0;
+ }
+ ParentIoBase = IoBase;
+ ParentIoLimit = IoLimit;
+ }
+ }
+
+ //
+ // Compute PCI Lib Address to PCI UART
+ //
+ PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
+
+ //
+ // Find the first IO or MMIO BAR
+ //
+ RegisterBaseMask = 0xFFFFFFF0;
+ for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) {
+ SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);
+ if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {
+ //
+ // MMIO BAR is found
+ //
+ RegisterBaseMask = 0xFFFFFFF0;
+ break;
+ }
+
+ if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {
+ //
+ // IO BAR is found
+ //
+ RegisterBaseMask = 0xFFFFFFF8;
+ break;
+ }
+ }
+
+ //
+ // MMIO or IO BAR is not found.
+ //
+ if (BarIndex == PCI_MAX_BAR) {
+ return 0;
+ }
+
+ //
+ // Program UART BAR
+ //
+ SerialRegisterBase = SerialPortLibUpdatePciRegister32 (
+ PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,
+ (UINT32)PcdGet64 (PcdSerialRegisterBase),
+ RegisterBaseMask
+ );
+
+ //
+ // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
+ //
+ if (PcdGetBool (PcdSerialUseMmio)) {
+ if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) {
+ return 0;
+ }
+ } else {
+ if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) {
+ return 0;
+ }
+ }
+
+ //
+ // Enable I/O and MMIO in PCI UART Device if they are not already enabled
+ //
+ PciOr16 (
+ PciLibAddress + PCI_COMMAND_OFFSET,
+ PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
+ );
+
+ //
+ // Force D0 state if a Power Management and Status Register is specified
+ //
+ if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
+ if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
+ PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
+ //
+ // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
+ }
+ }
+
+ //
+ // Get PCI Device Info
+ //
+ DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);
+
+ //
+ // Enable I/O or MMIO in PCI Bridge
+ // Assume Root Bus Numer is Zero.
+ //
+ for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {
+ //
+ // Compute PCI Lib Address to PCI to PCI Bridge
+ //
+ PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);
+
+ //
+ // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
+ //
+ PciOr16 (
+ PciLibAddress + PCI_COMMAND_OFFSET,
+ PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE
+ );
+
+ //
+ // Force D0 state if a Power Management and Status Register is specified
+ //
+ if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {
+ if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {
+ PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));
+ }
+ }
+
+ BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
+ }
+
+ return SerialRegisterBase;
+}
+
+/**
+ Return whether the hardware flow control signal allows writing.
+
+ @param SerialRegisterBase The base address register of UART device.
+
+ @retval TRUE The serial port is writable.
+ @retval FALSE The serial port is not writable.
+**/
+BOOLEAN
+SerialPortWritable (
+ UINTN SerialRegisterBase
+ )
+{
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ if (PcdGetBool (PcdSerialDetectCable)) {
+ //
+ // Wait for both DSR and CTS to be set
+ // DSR is set if a cable is connected.
+ // CTS is set if it is ok to transmit data
+ //
+ // DSR CTS Description Action
+ // === === ======================================== ========
+ // 0 0 No cable connected. Wait
+ // 0 1 No cable connected. Wait
+ // 1 0 Cable connected, but not clear to send. Wait
+ // 1 1 Cable connected, and clear to send. Transmit
+ //
+ return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));
+ } else {
+ //
+ // Wait for both DSR and CTS to be set OR for DSR to be clear.
+ // DSR is set if a cable is connected.
+ // CTS is set if it is ok to transmit data
+ //
+ // DSR CTS Description Action
+ // === === ======================================== ========
+ // 0 0 No cable connected. Transmit
+ // 0 1 No cable connected. Transmit
+ // 1 0 Cable connected, but not clear to send. Wait
+ // 1 1 Cable connected, and clar to send. Transmit
+ //
+ return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));
+ }
+ }
+
+ return TRUE;
+}
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfully initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ RETURN_STATUS Status;
+ UINTN SerialRegisterBase;
+ UINT32 Divisor;
+ UINT32 CurrentDivisor;
+ BOOLEAN Initialized;
+
+ //
+ // Perform platform specific initialization required to enable use of the 16550 device
+ // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
+ //
+ Status = PlatformHookSerialPortInitialize ();
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Calculate divisor for baud generator
+ // Ref_Clk_Rate / Baud_Rate / 16
+ //
+ Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);
+ if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {
+ Divisor++;
+ }
+
+ //
+ // Get the base address of the serial port in either I/O or MMIO space
+ //
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_DEVICE_ERROR;
+ }
+
+ //
+ // See if the serial port is already initialized
+ //
+ Initialized = TRUE;
+ if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {
+ Initialized = FALSE;
+ }
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));
+ CurrentDivisor = SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;
+ CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));
+ if (CurrentDivisor != Divisor) {
+ Initialized = FALSE;
+ }
+ if (Initialized) {
+ return RETURN_SUCCESS;
+ }
+
+ //
+ // Wait for the serial port to be ready.
+ // Verify that both the transmit FIFO and the shift register are empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
+ //
+ // Configure baud rate
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
+
+ //
+ // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
+ // Strip reserved bits from PcdSerialLineControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));
+
+ //
+ // Enable and reset FIFOs
+ // Strip reserved bits from PcdSerialFifoControl
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));
+
+ //
+ // Set RTS and DTR in Modem Control Register(MCR)
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR,
+ EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+
+ If Buffer is NULL, then ASSERT().
+
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the write operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN SerialRegisterBase;
+ UINTN Result;
+ UINTN Index;
+ UINTN FifoSize;
+
+ if (Buffer == NULL) {
+ return 0;
+ }
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return 0;
+ }
+
+ if (NumberOfBytes == 0) {
+ //
+ // Flush the hardware
+ //
+
+ //
+ // Wait for both the transmit FIFO and shift register empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
+
+ //
+ // Wait for the hardware flow control signal
+ //
+ while (!SerialPortWritable (SerialRegisterBase));
+ return 0;
+ }
+
+ //
+ // Compute the maximum size of the Tx FIFO
+ //
+ FifoSize = 1;
+ if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {
+ if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {
+ FifoSize = 16;
+ } else {
+ FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);
+ }
+ }
+
+ Result = NumberOfBytes;
+ while (NumberOfBytes != 0) {
+ //
+ // Wait for the serial port to be ready, to make sure both the transmit FIFO
+ // and shift register empty.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
+
+ //
+ // Fill then entire Tx FIFO
+ //
+ for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {
+ //
+ // Wait for the hardware flow control signal
+ //
+ while (!SerialPortWritable (SerialRegisterBase));
+
+ //
+ // Write byte to the transmit buffer.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);
+ }
+ }
+ return Result;
+}
+
+/**
+ Reads data from a serial device into a buffer.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes to read from the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes read from the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN SerialRegisterBase;
+ UINTN Result;
+ UINT8 Mcr;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return 0;
+ }
+
+ Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);
+
+ for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {
+ //
+ // Wait for the serial port to have some data.
+ //
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Set RTS to let the peer send some data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));
+ }
+ }
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Clear RTS to prevent peer from sending data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
+ }
+
+ //
+ // Read byte from the receive buffer.
+ //
+ *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);
+ }
+
+ return Result;
+}
+
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls aserial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ UINTN SerialRegisterBase;
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return FALSE;
+ }
+
+ //
+ // Read the serial port status
+ //
+ if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Clear RTS to prevent peer from sending data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));
+ }
+ return TRUE;
+ }
+
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ //
+ // Set RTS to let the peer send some data
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));
+ }
+
+ return FALSE;
+}
+
+/**
+ Sets the control bits on a serial device.
+
+ @param Control Sets the bits of Control that are settable.
+
+ @retval RETURN_SUCCESS The new control bits were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT8 Mcr;
+
+ //
+ // First determine the parameter is invalid.
+ //
+ if ((Control & (~(EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY |
+ EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE))) != 0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Read the Modem Control Register.
+ //
+ Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
+ Mcr &= (~(B_UART_MCR_DTRC | B_UART_MCR_RTS));
+
+ if ((Control & EFI_SERIAL_DATA_TERMINAL_READY) == EFI_SERIAL_DATA_TERMINAL_READY) {
+ Mcr |= B_UART_MCR_DTRC;
+ }
+
+ if ((Control & EFI_SERIAL_REQUEST_TO_SEND) == EFI_SERIAL_REQUEST_TO_SEND) {
+ Mcr |= B_UART_MCR_RTS;
+ }
+
+ //
+ // Write the Modem Control Register.
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param Control A pointer to return the current control signals from the serial device.
+
+ @retval RETURN_SUCCESS The control bits were read from the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT8 Msr;
+ UINT8 Mcr;
+ UINT8 Lsr;
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ *Control = 0;
+
+ //
+ // Read the Modem Status Register.
+ //
+ Msr = SerialPortReadRegister (SerialRegisterBase, R_UART_MSR);
+
+ if ((Msr & B_UART_MSR_CTS) == B_UART_MSR_CTS) {
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+ }
+
+ if ((Msr & B_UART_MSR_DSR) == B_UART_MSR_DSR) {
+ *Control |= EFI_SERIAL_DATA_SET_READY;
+ }
+
+ if ((Msr & B_UART_MSR_RI) == B_UART_MSR_RI) {
+ *Control |= EFI_SERIAL_RING_INDICATE;
+ }
+
+ if ((Msr & B_UART_MSR_DCD) == B_UART_MSR_DCD) {
+ *Control |= EFI_SERIAL_CARRIER_DETECT;
+ }
+
+ //
+ // Read the Modem Control Register.
+ //
+ Mcr = SerialPortReadRegister (SerialRegisterBase, R_UART_MCR);
+
+ if ((Mcr & B_UART_MCR_DTRC) == B_UART_MCR_DTRC) {
+ *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
+ }
+
+ if ((Mcr & B_UART_MCR_RTS) == B_UART_MCR_RTS) {
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+ }
+
+ if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+ }
+
+ //
+ // Read the Line Status Register.
+ //
+ Lsr = SerialPortReadRegister (SerialRegisterBase, R_UART_LSR);
+
+ if ((Lsr & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) == (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) {
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+
+ if ((Lsr & B_UART_LSR_RXRDY) == 0) {
+ *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
+ data bits, and stop bits on a serial device.
+
+ @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
+ device's default interface speed.
+ On output, the value actually set.
+ @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
+ serial interface. A ReceiveFifoDepth value of 0 will use
+ the device's default FIFO depth.
+ On output, the value actually set.
+ @param Timeout The requested time out for a single character in microseconds.
+ This timeout applies to both the transmit and receive side of the
+ interface. A Timeout value of 0 will use the device's default time
+ out value.
+ On output, the value actually set.
+ @param Parity The type of parity to use on this serial device. A Parity value of
+ DefaultParity will use the device's default parity value.
+ On output, the value actually set.
+ @param DataBits The number of data bits to use on the serial device. A DataBits
+ vaule of 0 will use the device's default data bit setting.
+ On output, the value actually set.
+ @param StopBits The number of stop bits to use on this serial device. A StopBits
+ value of DefaultStopBits will use the device's default number of
+ stop bits.
+ On output, the value actually set.
+
+ @retval RETURN_SUCCESS The new attributes were set on the serial device.
+ @retval RETURN_UNSUPPORTED The serial device does not support this operation.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
+ @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ UINTN SerialRegisterBase;
+ UINT32 SerialBaudRate;
+ UINTN Divisor;
+ UINT8 Lcr;
+ UINT8 LcrData;
+ UINT8 LcrParity;
+ UINT8 LcrStop;
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+ if (SerialRegisterBase ==0) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ //
+ // Check for default settings and fill in actual values.
+ //
+ if (*BaudRate == 0) {
+ *BaudRate = PcdGet32 (PcdSerialBaudRate);
+ }
+ SerialBaudRate = (UINT32) *BaudRate;
+
+ if (*DataBits == 0) {
+ LcrData = (UINT8) (PcdGet8 (PcdSerialLineControl) & 0x3);
+ *DataBits = LcrData + 5;
+ } else {
+ if ((*DataBits < 5) || (*DataBits > 8)) {
+ return RETURN_INVALID_PARAMETER;
+ }
+ //
+ // Map 5..8 to 0..3
+ //
+ LcrData = (UINT8) (*DataBits - (UINT8) 5);
+ }
+
+ if (*Parity == DefaultParity) {
+ LcrParity = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 3) & 0x7);
+ switch (LcrParity) {
+ case 0:
+ *Parity = NoParity;
+ break;
+
+ case 3:
+ *Parity = EvenParity;
+ break;
+
+ case 1:
+ *Parity = OddParity;
+ break;
+
+ case 7:
+ *Parity = SpaceParity;
+ break;
+
+ case 5:
+ *Parity = MarkParity;
+ break;
+
+ default:
+ break;
+ }
+ } else {
+ switch (*Parity) {
+ case NoParity:
+ LcrParity = 0;
+ break;
+
+ case EvenParity:
+ LcrParity = 3;
+ break;
+
+ case OddParity:
+ LcrParity = 1;
+ break;
+
+ case SpaceParity:
+ LcrParity = 7;
+ break;
+
+ case MarkParity:
+ LcrParity = 5;
+ break;
+
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+ }
+
+ if (*StopBits == DefaultStopBits) {
+ LcrStop = (UINT8) ((PcdGet8 (PcdSerialLineControl) >> 2) & 0x1);
+ switch (LcrStop) {
+ case 0:
+ *StopBits = OneStopBit;
+ break;
+
+ case 1:
+ if (*DataBits == 5) {
+ *StopBits = OneFiveStopBits;
+ } else {
+ *StopBits = TwoStopBits;
+ }
+ break;
+
+ default:
+ break;
+ }
+ } else {
+ switch (*StopBits) {
+ case OneStopBit:
+ LcrStop = 0;
+ break;
+
+ case OneFiveStopBits:
+ case TwoStopBits:
+ LcrStop = 1;
+ break;
+
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+ }
+
+ //
+ // Calculate divisor for baud generator
+ // Ref_Clk_Rate / Baud_Rate / 16
+ //
+ Divisor = PcdGet32 (PcdSerialClockRate) / (SerialBaudRate * 16);
+ if ((PcdGet32 (PcdSerialClockRate) % (SerialBaudRate * 16)) >= SerialBaudRate * 8) {
+ Divisor++;
+ }
+
+ //
+ // Configure baud rate
+ //
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));
+
+ //
+ // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
+ // Strip reserved bits from line control value
+ //
+ Lcr = (UINT8) ((LcrParity << 3) | (LcrStop << 2) | LcrData);
+ SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8) (Lcr & 0x3F));
+
+ return RETURN_SUCCESS;
+}
+
--- /dev/null
+## @file
+# SerialPortLib instance for 16550 UART.
+#
+# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSerialPortLib16550
+ MODULE_UNI_FILE = BaseSerialPortLib16550.uni
+ FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.1
+ LIBRARY_CLASS = SerialPortLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ PcdLib
+ IoLib
+ PlatformHookLib
+ PciLib
+
+[Sources]
+ BaseSerialPortLib16550.c
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMETIMES_CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSUMES
--- /dev/null
+// /** @file
+// SerialPortLib instance for 16550 UART.
+//
+// SerialPortLib instance for 16550 UART.
+//
+// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib instance for 16550 UART"
+
+#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib instance for 16550 UART."
+
@return the UNIT64 value after convertion.\r
\r
**/\r
-UINT64 \r
+UINT64
cb_unpack64 (\r
IN struct cbuint64 val\r
)\r
}\r
DEBUG ((EFI_D_INFO, "Reset Value 0x%x\n", Fadt->ResetValue));\r
\r
- if (pPmEvtReg != NULL) { \r
+ if (pPmEvtReg != NULL) {
*pPmEvtReg = Fadt->Pm1aEvtBlk;\r
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));\r
}\r
\r
- if (pPmGpeEnReg != NULL) { \r
+ if (pPmGpeEnReg != NULL) {
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));\r
}\r
*pResetValue = Fadt->ResetValue;\r
DEBUG ((EFI_D_ERROR, "Reset Value 0x%x\n", Fadt->ResetValue));\r
\r
- if (pPmEvtReg != NULL) { \r
+ if (pPmEvtReg != NULL) {
*pPmEvtReg = Fadt->Pm1aEvtBlk;\r
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));\r
}\r
\r
- if (pPmGpeEnReg != NULL) { \r
+ if (pPmGpeEnReg != NULL) {
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;\r
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));\r
- } \r
+ }
return RETURN_SUCCESS;\r
}\r
}\r
\r
@param pRegBase Pointer to the base address of serial port registers\r
@param pRegAccessType Pointer to the access type of serial port registers\r
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate\r
+ @param pInputHertz Pointer to the input clock frequency
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address
\r
@retval RETURN_SUCCESS Successfully find the serial port information.\r
@retval RETURN_NOT_FOUND Failed to find the serial port information .\r
CbParseSerialInfo (\r
OUT UINT32 *pRegBase,\r
OUT UINT32 *pRegAccessType,\r
- OUT UINT32 *pBaudrate\r
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pUartPciAddr
)\r
{\r
struct cb_serial *CbSerial;\r
*pRegBase = CbSerial->baseaddr;\r
}\r
\r
+ if (pRegWidth != NULL) {
+ *pRegWidth = CbSerial->regwidth;
+ }
+
if (pRegAccessType != NULL) {\r
*pRegAccessType = CbSerial->type;\r
}\r
*pBaudrate = CbSerial->baud;\r
}\r
\r
+ if (pInputHertz != NULL) {
+ *pInputHertz = CbSerial->input_hertz;
+ }
+
+ if (pUartPciAddr != NULL) {
+ *pUartPciAddr = CbSerial->uart_pci_addr;
+ }
+
return RETURN_SUCCESS;\r
}\r
\r
Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciEnumeratorSupport.c
-
+
Abstract:
PCI Bus Driver
#include "PciBus.h"
-EFI_STATUS
+EFI_STATUS
InitializePPB (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
-EFI_STATUS
+EFI_STATUS
InitializeP2C (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
-PCI_IO_DEVICE*
+PCI_IO_DEVICE*
CreatePciIoDevice (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
);
-EFI_STATUS
+EFI_STATUS
DetermineDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice
);
-EFI_STATUS
+EFI_STATUS
BarExisted (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
EFI_DEVICE_PATH_PROTOCOL*
CreatePciDevicePath(
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
-PCI_IO_DEVICE*
+PCI_IO_DEVICE*
GatherDeviceInfo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
UINT8 Func
);
-PCI_IO_DEVICE*
+PCI_IO_DEVICE*
GatherPPBInfo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
if (!EFI_ERROR (Status)) {
+ //
+ // Skip non-bridge devices which are not enabled
+ //
+ if (((Pci.Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE
+ | EFI_PCI_COMMAND_MEMORY_SPACE)) == 0)
+ && (!(IS_PCI_BRIDGE (&Pci) || IS_CARDBUS_BRIDGE (&Pci)))) {
+ continue;
+ }
+
//
// Collect all the information about the PCI device discovered
//
if (EFI_ERROR (Status)) {
return Status;
}
-
+
//
// If the PCI bridge is initialized then enumerate the next level bus
//
if (!PciIoDevice) {
return EFI_OUT_OF_RESOURCES;
}
-
+
//
// Create a device path for this PCI device and store it into its private data
//
CreatePciDevicePath(
Bridge->DevicePath,
- PciIoDevice
+ PciIoDevice
);
-
+
//
// Detect this function has option rom
//
}
ResetPowerManagementFeature (PciIoDevice);
-
- }
+
+ }
else {
PciRomGetRomResourceFromPciOptionRomTable (
&gPciBusDriverBinding,
);
}
-
+
//
// Insert it into a global tree for future reference
//
if (!PciIoDevice) {
return NULL;
}
-
+
if (gFullEnumeration) {
PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
--*/
{
PCI_IO_DEVICE *PciIoDevice;
-
+
PciIoDevice = CreatePciIoDevice (
PciRootBridgeIo,
Pci,
// P2C only has one bar that is in 0x10
//
PciParseBar(PciIoDevice, 0x10, 0);
-
+
PciIoDevice->Decodes = EFI_BRIDGE_MEM32_DECODE_SUPPORTED |
EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
EFI_BRIDGE_IO32_DECODE_SUPPORTED;
/*++
Routine Description:
-
+
Determine the related attributes of all devices under a Root Bridge
Arguments:
PciReadCommandRegister(PciIoDevice, &Command);
-
+
if (Command & EFI_PCI_COMMAND_IO_SPACE) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_IO;
}
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_BUS_MASTER;
}
- if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) ||
+ if (IS_PCI_BRIDGE (&(PciIoDevice->Pci)) ||
IS_CARDBUS_BRIDGE (&(PciIoDevice->Pci))){
//
//
// Determine whether the ISA bit is set
// If ISA Enable on Bridge is set, the PPB
- // will block forwarding 0x100-0x3ff for each 1KB in the
+ // will block forwarding 0x100-0x3ff for each 1KB in the
// first 64KB I/O range.
//
if ((BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA) != 0) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_ISA_IO;
- }
+ }
//
// Determine whether the VGA bit is set
}
//
- // if the palette snoop bit is set, then the brige is set to
+ // if the palette snoop bit is set, then the brige is set to
// decode palette IO write
//
if (Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) {
PciIoDevice->Attributes |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
}
- }
+ }
return EFI_SUCCESS;
}
//
// Fix the length to support some spefic 64 bit BAR
//
- Value |= ((UINT32)(-1) << HighBitSet32 (Value));
+ Value |= ((UINT32)(-1) << HighBitSet32 (Value));
//
// Calculate the size of 64bit bar
break;
}
}
-
+
//
// Check the length again so as to keep compatible with some special bars
//
PciIoDevice->PciBar[BarIndex].BaseAddress = 0;
PciIoDevice->PciBar[BarIndex].Alignment = 0;
}
-
+
//
// Increment number of bar
//
Routine Description:
- This routine is used to enumerate entire pci bus system
+ This routine is used to enumerate entire pci bus system
in a given platform
Arguments:
// Open the IO Abstraction(s) needed to perform the supported test
//
Status = gBS->OpenProtocol (
- Controller ,
- &gEfiDevicePathProtocolGuid,
+ Controller ,
+ &gEfiDevicePathProtocolGuid,
(VOID **)&ParentDevicePath,
- gPciBusDriverBinding.DriverBindingHandle,
- Controller,
+ gPciBusDriverBinding.DriverBindingHandle,
+ Controller,
EFI_OPEN_PROTOCOL_BY_DRIVER
);
if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {
}
//
- // Load all EFI Drivers from all PCI Option ROMs behind the PCI Root Bridge
+ // Load all EFI Drivers from all PCI Option ROMs behind the PCI Root Bridge
//
Status = PciRomLoadEfiDriversFromOptionRomTable (&gPciBusDriverBinding, PciRootBridgeIo);
MinBus - The min bus.
MaxBus - The max bus.
BusRange - The bus range.
-
+
Returns:
-
+
Status Code.
--*/
VOID\r
)\r
{\r
+ gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
+ gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
+ gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity);
+ gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
}\r
\r
\r
\r
DEBUG ((EFI_D_INFO, "PlatformBdsPolicyBehavior\n"));\r
\r
+ PlatformBdsInit();
ConnectRootBridge ();\r
\r
//\r
DebugLib\r
PcdLib\r
GenericBdsLib\r
+ PlatformHookLib
+
[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut\r
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
\r
#include <Base.h>\r
#include <Uefi/UefiBaseType.h>\r
+#include <Library/PciLib.h>
#include <Library/PlatformHookLib.h>\r
#include <Library/CbParseLib.h>\r
#include <Library/PcdLib.h>\r
\r
+typedef struct {
+ UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
+ UINT16 DeviceId; ///< Device ID to match the PCI device
+ UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
+ UINT64 Offset; ///< The byte offset into to the BAR
+ UINT8 BarIndex; ///< Which BAR to get the UART base address
+ UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
+ UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
+ UINT8 Reserved[2];
+} PCI_SERIAL_PARAMETER;
+
/**\r
Performs platform specific initialization required for the CPU to access\r
the hardware associated with a SerialPortLib instance. This function does\r
RETURN_STATUS Status;\r
UINT32 SerialRegBase;\r
UINT32 SerialRegAccessType;\r
+ UINT32 BaudRate;
+ UINT32 RegWidth;
+ UINT32 InputHertz;
+ UINT32 PayloadParam;
+ UINT32 DeviceVendor;
+ PCI_SERIAL_PARAMETER *SerialParam;
\r
- Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, NULL);\r
+ Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType,
+ &RegWidth, &BaudRate, &InputHertz,
+ &PayloadParam);
if (RETURN_ERROR (Status)) {\r
return Status;\r
}\r
return Status;\r
}\r
\r
+ Status = PcdSet32S (PcdSerialRegisterStride, RegWidth);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet32S (PcdSerialBaudRate, BaudRate);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = PcdSet32S (PcdSerialClockRate, InputHertz);
+ if (RETURN_ERROR (Status)) {
+ return Status;
+ }
+
+ if (PayloadParam >= 0x80000000) {
+ DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000);
+ SerialParam = PcdGetPtr(PcdPciSerialParameters);
+ SerialParam->VendorId = (UINT16)DeviceVendor;
+ SerialParam->DeviceId = DeviceVendor >> 16;
+ SerialParam->ClockRate = InputHertz;
+ SerialParam->RegisterStride = (UINT8)RegWidth;
+ }
+
return RETURN_SUCCESS;\r
}\r
-\r
MODULE_TYPE = BASE\r
VERSION_STRING = 1.0\r
LIBRARY_CLASS = PlatformHookLib\r
+ CONSTRUCTOR = PlatformHookSerialPortInitialize
\r
[Sources]\r
PlatformHookLib.c\r
[LibraryClasses]\r
CbParseLib\r
PcdLib\r
+ PciLib
\r
[Packages]\r
MdePkg/MdePkg.dec\r
CorebootModulePkg/CorebootModulePkg.dec\r
\r
[Pcd]\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES\r
-\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES
}\r
\r
// Read the PM register\r
- PmConf = MmioRead32 (LAN9118_PMT_CTRL);\r
+ PmConf = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
\r
// MPTCTRL_WOL_EN: Allow Wake-On-Lan to detect wake up frames or magic packets\r
// MPTCTRL_ED_EN: Allow energy detection to allow lowest power consumption mode\r
PmConf |= (MPTCTRL_WOL_EN | MPTCTRL_ED_EN | MPTCTRL_PME_EN);\r
\r
// Write the current configuration to the register\r
- MmioWrite32 (LAN9118_PMT_CTRL, PmConf);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf);\r
\r
// Configure GPIO and HW\r
Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);\r
}\r
\r
// Now acknowledge all interrupts\r
- MmioWrite32 (LAN9118_INT_STS, ~0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, ~0);\r
\r
// Declare the driver as initialized\r
Snp->Mode->State = EfiSimpleNetworkInitialized;\r
}\r
\r
// Read the PM register\r
- PmConf = MmioRead32 (LAN9118_PMT_CTRL);\r
+ PmConf = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
\r
// MPTCTRL_WOL_EN: Allow Wake-On-Lan to detect wake up frames or magic packets\r
// MPTCTRL_ED_EN: Allow energy detection to allow lowest power consumption mode\r
PmConf |= (MPTCTRL_WOL_EN | MPTCTRL_ED_EN | MPTCTRL_PME_EN);\r
\r
// Write the current configuration to the register\r
- MmioWrite32 (LAN9118_PMT_CTRL, PmConf);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_PMT_CTRL, PmConf);\r
\r
// Reactivate the LEDs\r
Status = ConfigureHardware (HW_CONF_USE_LEDS, Snp);\r
\r
// Check that a buffer size was specified in SnpInitialize\r
if (gTxBuffer != 0) {\r
- HwConf = MmioRead32 (LAN9118_HW_CFG); // Read the HW register\r
+ HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG); // Read the HW register\r
HwConf &= ~HW_CFG_TX_FIFO_SIZE_MASK; // Clear buffer bits first\r
HwConf |= HW_CFG_TX_FIFO_SIZE(gTxBuffer); // assign size chosen in SnpInitialize\r
\r
- MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf); // Write the conf\r
}\r
\r
// Enable the receiver and transmitter and clear their contents\r
StartTx (START_TX_MAC | START_TX_CFG | START_TX_CLEAR, Snp);\r
\r
// Now acknowledge all interrupts\r
- MmioWrite32 (LAN9118_INT_STS, ~0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, ~0);\r
\r
return EFI_SUCCESS;\r
}\r
// Write the options to the MAC_CSR\r
//\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCSRValue);\r
- MemoryFence();\r
\r
//\r
// If we have to retrieve something, start packet reception.\r
// consumer of SNP does not call GetStatus.)\r
// TODO will we lose TxStatuses if this happens? Maybe in SnpTransmit we\r
// should check for it and dump the TX Status FIFO.\r
- FifoInt = MmioRead32 (LAN9118_FIFO_INT);\r
+ FifoInt = Lan9118MmioRead32 (LAN9118_FIFO_INT);\r
\r
// Clear the TX Status FIFO Overflow\r
if ((FifoInt & INSTS_TXSO) == 0) {\r
FifoInt |= INSTS_TXSO;\r
- MmioWrite32 (LAN9118_FIFO_INT, FifoInt);\r
+ Lan9118MmioWrite32 (LAN9118_FIFO_INT, FifoInt);\r
}\r
\r
// Read interrupt status if IrqStat is not NULL\r
*IrqStat = 0;\r
\r
// Check for receive interrupt\r
- if (MmioRead32 (LAN9118_INT_STS) & INSTS_RSFL) { // Data moved from rx FIFO\r
+ if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_RSFL) { // Data moved from rx FIFO\r
*IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;\r
- MmioWrite32 (LAN9118_INT_STS,INSTS_RSFL);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_RSFL);\r
}\r
\r
// Check for transmit interrupt\r
- if (MmioRead32 (LAN9118_INT_STS) & INSTS_TSFL) {\r
+ if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_TSFL) {\r
*IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;\r
- MmioWrite32 (LAN9118_INT_STS,INSTS_TSFL);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_TSFL);\r
}\r
\r
// Check for software interrupt\r
- if (MmioRead32 (LAN9118_INT_STS) & INSTS_SW_INT) {\r
+ if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_SW_INT) {\r
*IrqStat |= EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT;\r
- MmioWrite32 (LAN9118_INT_STS,INSTS_SW_INT);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS,INSTS_SW_INT);\r
}\r
}\r
\r
// Check Status of transmitted packets\r
// (We ignore TXSTATUS_NO_CA has it might happen in Full Duplex)\r
\r
- NumTxStatusEntries = MmioRead32(LAN9118_TX_FIFO_INF) & TXFIFOINF_TXSUSED_MASK;\r
+ NumTxStatusEntries = Lan9118MmioRead32(LAN9118_TX_FIFO_INF) & TXFIFOINF_TXSUSED_MASK;\r
if (NumTxStatusEntries > 0) {\r
- TxStatus = MmioRead32 (LAN9118_TX_STATUS);\r
+ TxStatus = Lan9118MmioRead32 (LAN9118_TX_STATUS);\r
PacketTag = TxStatus >> 16;\r
TxStatus = TxStatus & 0xFFFF;\r
if ((TxStatus & TXSTATUS_ES) && (TxStatus != (TXSTATUS_ES | TXSTATUS_NO_CA))) {\r
}\r
\r
// Check for a TX Error interrupt\r
- Interrupts = MmioRead32 (LAN9118_INT_STS);\r
+ Interrupts = Lan9118MmioRead32 (LAN9118_INT_STS);\r
if (Interrupts & INSTS_TXE) {\r
DEBUG ((EFI_D_ERROR, "LAN9118: Transmitter error. Restarting..."));\r
\r
CommandB = TX_CMD_B_PACKET_TAG (PacketTag) | TX_CMD_B_PACKET_LENGTH (BuffSize);\r
\r
// Write the commands first\r
- MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
- MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
\r
// Write the destination address\r
- MmioWrite32 (LAN9118_TX_DATA,\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA,\r
(DstAddr->Addr[0]) |\r
(DstAddr->Addr[1] << 8) |\r
(DstAddr->Addr[2] << 16) |\r
(DstAddr->Addr[3] << 24)\r
);\r
\r
- MmioWrite32 (LAN9118_TX_DATA,\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA,\r
(DstAddr->Addr[4]) |\r
(DstAddr->Addr[5] << 8) |\r
(SrcAddr->Addr[0] << 16) | // Write the Source Address\r
(SrcAddr->Addr[1] << 24)\r
);\r
\r
- MmioWrite32 (LAN9118_TX_DATA,\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA,\r
(SrcAddr->Addr[2]) |\r
(SrcAddr->Addr[3] << 8) |\r
(SrcAddr->Addr[4] << 16) |\r
);\r
\r
// Write the Protocol\r
- MmioWrite32 (LAN9118_TX_DATA, (UINT32)(HTONS (LocalProtocol)));\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, (UINT32)(HTONS (LocalProtocol)));\r
\r
// Next buffer is the payload\r
CommandA = TX_CMD_A_LAST_SEGMENT | TX_CMD_A_BUFF_SIZE (BuffSize - HdrSize) | TX_CMD_A_COMPLETION_INT | TX_CMD_A_DATA_START_OFFSET (2); // 2 bytes beginning offset\r
\r
// Write the commands\r
- MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
- MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
\r
// Write the payload\r
for (Count = 0; Count < ((BuffSize + 3) >> 2) - 3; Count++) {\r
- MmioWrite32 (LAN9118_TX_DATA, LocalData[Count + 3]);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, LocalData[Count + 3]);\r
}\r
} else {\r
// Format pointer\r
CommandB = TX_CMD_B_PACKET_TAG (PacketTag) | TX_CMD_B_PACKET_LENGTH (BuffSize);\r
\r
// Write the commands first\r
- MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
- MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandA);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, CommandB);\r
\r
// Write all the data\r
for (Count = 0; Count < ((BuffSize + 3) >> 2); Count++) {\r
- MmioWrite32 (LAN9118_TX_DATA, LocalData[Count]);\r
+ Lan9118MmioWrite32 (LAN9118_TX_DATA, LocalData[Count]);\r
}\r
}\r
\r
// explain those errors has been found so far and everything seems to\r
// work perfectly when they are just ignored.\r
//\r
- IntSts = MmioRead32 (LAN9118_INT_STS);\r
+ IntSts = Lan9118MmioRead32 (LAN9118_INT_STS);\r
if ((IntSts & INSTS_RXE) && (!(IntSts & INSTS_RSFF))) {\r
- MmioWrite32 (LAN9118_INT_STS, INSTS_RXE);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, INSTS_RXE);\r
}\r
\r
// Count dropped frames\r
- DroppedFrames = MmioRead32 (LAN9118_RX_DROP);\r
+ DroppedFrames = Lan9118MmioRead32 (LAN9118_RX_DROP);\r
LanDriver->Stats.RxDroppedFrames += DroppedFrames;\r
\r
NumPackets = RxStatusUsedSpace (0, Snp) / 4;\r
}\r
\r
// Read Rx Status (only if not empty)\r
- RxFifoStatus = MmioRead32 (LAN9118_RX_STATUS);\r
+ RxFifoStatus = Lan9118MmioRead32 (LAN9118_RX_STATUS);\r
LanDriver->Stats.RxTotalFrames += 1;\r
\r
// First check for errors\r
\r
// Set the amount of data to be transfered out of FIFO for THIS packet\r
// This can be used to trigger an interrupt, and status can be checked\r
- RxCfgValue = MmioRead32 (LAN9118_RX_CFG);\r
+ RxCfgValue = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
RxCfgValue &= ~(RXCFG_RX_DMA_CNT_MASK);\r
RxCfgValue |= RXCFG_RX_DMA_CNT (ReadLimit);\r
\r
// Set end alignment to 4-bytes\r
RxCfgValue &= ~(RXCFG_RX_END_ALIGN_MASK);\r
- MmioWrite32 (LAN9118_RX_CFG, RxCfgValue);\r
+ Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfgValue);\r
\r
// Update buffer size\r
*BuffSize = PLength; // -4 bytes may be needed: Received in buffer as\r
\r
// Read Rx Packet\r
for (Count = 0; Count < ReadLimit; Count++) {\r
- RawData[Count] = MmioRead32 (LAN9118_RX_DATA);\r
+ RawData[Count] = Lan9118MmioRead32 (LAN9118_RX_DATA);\r
}\r
\r
// Get the destination address\r
}\r
\r
// Check for Rx errors (worst possible error)\r
- if (MmioRead32 (LAN9118_INT_STS) & INSTS_RXE) {\r
+ if (Lan9118MmioRead32 (LAN9118_INT_STS) & INSTS_RXE) {\r
DEBUG ((EFI_D_WARN, "Warning: Receiver Error. Restarting...\n"));\r
\r
// Software reset, the RXE interrupt is cleared by the reset.\r
#define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command\r
#define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data\r
\r
+/*\r
+ * Required delays following write cycles (number of BYTE_TEST reads)\r
+ * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
+ * Where no delay listed, 0 has been assumed.\r
+ */\r
+#define LAN9118_RX_DATA_WR_DELAY 0\r
+#define LAN9118_RX_STATUS_WR_DELAY 0\r
+#define LAN9118_RX_STATUS_PEEK_WR_DELAY 0\r
+#define LAN9118_TX_DATA_WR_DELAY 0\r
+#define LAN9118_TX_STATUS_WR_DELAY 0\r
+#define LAN9118_TX_STATUS_PEEK_WR_DELAY 0\r
+#define LAN9118_ID_REV_WR_DELAY 0\r
+#define LAN9118_IRQ_CFG_WR_DELAY 3\r
+#define LAN9118_INT_STS_WR_DELAY 2\r
+#define LAN9118_INT_EN_WR_DELAY 1\r
+#define LAN9118_BYTE_TEST_WR_DELAY 0\r
+#define LAN9118_FIFO_INT_WR_DELAY 1\r
+#define LAN9118_RX_CFG_WR_DELAY 1\r
+#define LAN9118_TX_CFG_WR_DELAY 1\r
+#define LAN9118_HW_CFG_WR_DELAY 1\r
+#define LAN9118_RX_DP_CTL_WR_DELAY 1\r
+#define LAN9118_RX_FIFO_INF_WR_DELAY 0\r
+#define LAN9118_TX_FIFO_INF_WR_DELAY 3\r
+#define LAN9118_PMT_CTRL_WR_DELAY 7\r
+#define LAN9118_GPIO_CFG_WR_DELAY 1\r
+#define LAN9118_GPT_CFG_WR_DELAY 1\r
+#define LAN9118_GPT_CNT_WR_DELAY 3\r
+#define LAN9118_WORD_SWAP_WR_DELAY 1\r
+#define LAN9118_FREE_RUN_WR_DELAY 4\r
+#define LAN9118_RX_DROP_WR_DELAY 0\r
+#define LAN9118_MAC_CSR_CMD_WR_DELAY 1\r
+#define LAN9118_MAC_CSR_DATA_WR_DELAY 1\r
+#define LAN9118_AFC_CFG_WR_DELAY 1\r
+#define LAN9118_E2P_CMD_WR_DELAY 1\r
+#define LAN9118_E2P_DATA_WR_DELAY 1\r
+\r
+/*\r
+ * Required delays following read cycles (number of BYTE_TEST reads)\r
+ * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet.\r
+ * Where no delay listed, 0 has been assumed.\r
+ */\r
+#define LAN9118_RX_DATA_RD_DELAY 3\r
+#define LAN9118_RX_STATUS_RD_DELAY 3\r
+#define LAN9118_RX_STATUS_PEEK_RD_DELAY 0\r
+#define LAN9118_TX_DATA_RD_DELAY 0\r
+#define LAN9118_TX_STATUS_RD_DELAY 3\r
+#define LAN9118_TX_STATUS_PEEK_RD_DELAY 0\r
+#define LAN9118_ID_REV_RD_DELAY 0\r
+#define LAN9118_IRQ_CFG_RD_DELAY 0\r
+#define LAN9118_INT_STS_RD_DELAY 0\r
+#define LAN9118_INT_EN_RD_DELAY 0\r
+#define LAN9118_BYTE_TEST_RD_DELAY 0\r
+#define LAN9118_FIFO_INT_RD_DELAY 0\r
+#define LAN9118_RX_CFG_RD_DELAY 0\r
+#define LAN9118_TX_CFG_RD_DELAY 0\r
+#define LAN9118_HW_CFG_RD_DELAY 0\r
+#define LAN9118_RX_DP_CTL_RD_DELAY 0\r
+#define LAN9118_RX_FIFO_INF_RD_DELAY 0\r
+#define LAN9118_TX_FIFO_INF_RD_DELAY 0\r
+#define LAN9118_PMT_CTRL_RD_DELAY 0\r
+#define LAN9118_GPIO_CFG_RD_DELAY 0\r
+#define LAN9118_GPT_CFG_RD_DELAY 0\r
+#define LAN9118_GPT_CNT_RD_DELAY 0\r
+#define LAN9118_WORD_SWAP_RD_DELAY 0\r
+#define LAN9118_FREE_RUN_RD_DELAY 0\r
+#define LAN9118_RX_DROP_RD_DELAY 4\r
+#define LAN9118_MAC_CSR_CMD_RD_DELAY 0\r
+#define LAN9118_MAC_CSR_DATA_RD_DELAY 0\r
+#define LAN9118_AFC_CFG_RD_DELAY 0\r
+#define LAN9118_E2P_CMD_RD_DELAY 0\r
+#define LAN9118_E2P_DATA_RD_DELAY 0\r
\r
// Receiver Status bits\r
#define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error\r
#define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for)\r
\r
// ID_REV register bits\r
-#define IDREV_ID ((MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)\r
-#define IDREV_REV (MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)\r
+#define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16)\r
+#define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF)\r
\r
// Interrupt Config Register bits\r
#define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type\r
ASSERT(Index <= 12);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
// Set CSR busy bit to ensure read will occur\r
// Set the R/W bit to indicate we are reading\r
MacCSR = MAC_CSR_BUSY | MAC_CSR_READ | MAC_CSR_ADDR(Index);\r
\r
// Write to the register\r
- MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
+ Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
// Now read from data register to get read value\r
- return MmioRead32 (LAN9118_MAC_CSR_DATA);\r
+ return Lan9118MmioRead32 (LAN9118_MAC_CSR_DATA);\r
+}\r
+\r
+/*\r
+ * LAN9118 chips have special restrictions on some back-to-back Write/Read or\r
+ * Read/Read pairs of accesses. After a read or write that changes the state of\r
+ * the device, there is a period in which stale values may be returned in\r
+ * response to a read. This period is dependent on the registers accessed.\r
+ *\r
+ * We must delay prior reads by this period. This can either be achieved by\r
+ * timer-based delays, or by performing dummy reads of the BYTE_TEST register,\r
+ * for which the recommended number of reads is described in the LAN9118 data\r
+ * sheet. This is required in addition to any memory barriers.\r
+ *\r
+ * This function performs a number of dummy reads of the BYTE_TEST register, as\r
+ * a building block for the above.\r
+ */\r
+VOID\r
+WaitDummyReads (\r
+ UINTN Count\r
+ )\r
+{\r
+ while (Count--)\r
+ MmioRead32(LAN9118_BYTE_TEST);\r
+}\r
+\r
+UINT32\r
+Lan9118RawMmioRead32(\r
+ UINTN Address,\r
+ UINTN Delay\r
+ )\r
+{\r
+ UINT32 Value;\r
+\r
+ Value = MmioRead32(Address);\r
+ WaitDummyReads(Delay);\r
+ return Value;\r
+}\r
+\r
+UINT32\r
+Lan9118RawMmioWrite32(\r
+ UINTN Address,\r
+ UINT32 Value,\r
+ UINTN Delay\r
+ )\r
+{\r
+ MmioWrite32(Address, Value);\r
+ WaitDummyReads(Delay);\r
+ return Value;\r
}\r
\r
// Function to write to MAC indirect registers\r
ASSERT(Index <= 12);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
// Set CSR busy bit to ensure read will occur\r
// Set the R/W bit to indicate we are writing\r
MacCSR = MAC_CSR_BUSY | MAC_CSR_WRITE | MAC_CSR_ADDR(Index);\r
\r
// Now write the value to the register before issuing the write command\r
- ValueWritten = MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
+ ValueWritten = Lan9118MmioWrite32 (LAN9118_MAC_CSR_DATA, Value);\r
\r
// Write the config to the register\r
- MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
+ Lan9118MmioWrite32 (LAN9118_MAC_CSR_CMD, MacCSR);\r
\r
// Wait until CSR busy bit is cleared\r
- while ((MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
+ while ((Lan9118MmioRead32 (LAN9118_MAC_CSR_CMD) & MAC_CSR_BUSY) == MAC_CSR_BUSY);\r
\r
return ValueWritten;\r
}\r
EepromCmd |= E2P_EPC_ADDRESS(Index);\r
\r
// Write to Eeprom command register\r
- MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Check that operation didn't time out\r
- if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
+ if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Read command on index %x\n",Index));\r
return 0;\r
}\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Finally read the value\r
- return MmioRead32 (LAN9118_E2P_DATA);\r
+ return Lan9118MmioRead32 (LAN9118_E2P_DATA);\r
}\r
\r
// Function to write to EEPROM memory\r
ValueWritten = 0;\r
\r
// Read the EEPROM Command register\r
- EepromCmd = MmioRead32 (LAN9118_E2P_CMD);\r
+ EepromCmd = Lan9118MmioRead32 (LAN9118_E2P_CMD);\r
\r
// Set the busy bit to ensure read will occur\r
EepromCmd |= ((UINT32)1 << 31);\r
EepromCmd |= (Index & 0xF);\r
\r
// Write the value to the data register first\r
- ValueWritten = MmioWrite32 (LAN9118_E2P_DATA, Value);\r
+ ValueWritten = Lan9118MmioWrite32 (LAN9118_E2P_DATA, Value);\r
\r
// Write to Eeprom command register\r
- MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_E2P_CMD, EepromCmd);\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Check that operation didn't time out\r
- if (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
+ if (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_TIMEOUT) {\r
DEBUG ((EFI_D_ERROR, "EEPROM Operation Timed out: Write command at memloc 0x%x, with value 0x%x\n",Index, Value));\r
return 0;\r
}\r
\r
// Wait until operation has completed\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
return ValueWritten;\r
}\r
UINT64 DefaultMacAddress;\r
\r
// Attempt to wake-up the device if it is in a lower power state\r
- if (((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
+ if (((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PM_MODE_MASK) >> 12) != 0) {\r
DEBUG ((DEBUG_NET, "Waking from reduced power state.\n"));\r
- MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_BYTE_TEST, 0xFFFFFFFF);\r
}\r
\r
// Check that device is active\r
Retries = 20;\r
- while ((MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {\r
+ while ((Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_READY) == 0 && --Retries) {\r
gBS->Stall (LAN9118_STALL);\r
- MemoryFence();\r
}\r
if (!Retries) {\r
return EFI_TIMEOUT;\r
\r
// Check that EEPROM isn't active\r
Retries = 20;\r
- while ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){\r
+ while ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY) && --Retries){\r
gBS->Stall (LAN9118_STALL);\r
- MemoryFence();\r
}\r
if (!Retries) {\r
return EFI_TIMEOUT;\r
\r
// Check if a MAC address was loaded from EEPROM, and if it was, set it as the\r
// current address.\r
- if ((MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
+ if ((Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_MAC_ADDRESS_LOADED) == 0) {\r
DEBUG ((EFI_D_ERROR, "Warning: There was an error detecting EEPROM or loading the MAC Address.\n"));\r
\r
// If we had an address before (set by StationAddess), continue to use it\r
}\r
\r
// Clear and acknowledge interrupts\r
- MmioWrite32 (LAN9118_INT_EN, 0);\r
- MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
+ Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
+ Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
\r
// Do self tests here?\r
\r
StopRx (STOP_RX_CLEAR, Snp); // Clear receiver FIFO\r
\r
// Issue the reset\r
- HwConf = MmioRead32 (LAN9118_HW_CFG);\r
+ HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
HwConf |= 1;\r
\r
// Set the Must Be One (MBO) bit\r
}\r
\r
// Check that EEPROM isn't active\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// Write the configuration\r
- MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
\r
// Wait for reset to complete\r
- while (MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
+ while (Lan9118MmioRead32 (LAN9118_HW_CFG) & HWCFG_SRST) {\r
\r
- MemoryFence();\r
gBS->Stall (LAN9118_STALL);\r
ResetTime += 1;\r
\r
}\r
\r
// Check that EEPROM isn't active\r
- while (MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
+ while (Lan9118MmioRead32 (LAN9118_E2P_CMD) & E2P_EPC_BUSY);\r
\r
// TODO we probably need to re-set the mac address here.\r
\r
// Clear and acknowledge all interrupts\r
if (Flags & SOFT_RESET_CLEAR_INT) {\r
- MmioWrite32 (LAN9118_INT_EN, 0);\r
- MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
+ Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
+ Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
}\r
\r
// Do self tests here?\r
\r
// PMT PHY reset takes precedence over BCR\r
if (Flags & PHY_RESET_PMT) {\r
- PmtCtrl = MmioRead32 (LAN9118_PMT_CTRL);\r
+ PmtCtrl = Lan9118MmioRead32 (LAN9118_PMT_CTRL);\r
PmtCtrl |= MPTCTRL_PHY_RST;\r
- MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
+ Lan9118MmioWrite32 (LAN9118_PMT_CTRL,PmtCtrl);\r
\r
// Wait for completion\r
- while (MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
- MemoryFence();\r
+ while (Lan9118MmioRead32 (LAN9118_PMT_CTRL) & MPTCTRL_PHY_RST) {\r
+ gBS->Stall (LAN9118_STALL);\r
}\r
// PHY Basic Control Register reset\r
} else if (Flags & PHY_RESET_BCR) {\r
\r
// Wait for completion\r
while (IndirectPHYRead32 (PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) {\r
- MemoryFence();\r
+ gBS->Stall (LAN9118_STALL);\r
}\r
}\r
\r
// Clear and acknowledge all interrupts\r
if (Flags & PHY_SOFT_RESET_CLEAR_INT) {\r
- MmioWrite32 (LAN9118_INT_EN, 0);\r
- MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
- MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
+ Lan9118MmioWrite32 (LAN9118_INT_EN, 0);\r
+ Lan9118MmioWrite32 (LAN9118_IRQ_CFG, 0);\r
+ Lan9118MmioWrite32 (LAN9118_INT_STS, 0xFFFFFFFF);\r
}\r
\r
return EFI_SUCCESS;\r
\r
// Check if we want to use LEDs on GPIO\r
if (Flags & HW_CONF_USE_LEDS) {\r
- GpioConf = MmioRead32 (LAN9118_GPIO_CFG);\r
+ GpioConf = Lan9118MmioRead32 (LAN9118_GPIO_CFG);\r
\r
// Enable GPIO as LEDs and Config as Push-Pull driver\r
GpioConf |= GPIO_GPIO0_PUSH_PULL | GPIO_GPIO1_PUSH_PULL | GPIO_GPIO2_PUSH_PULL |\r
GPIO_LED1_ENABLE | GPIO_LED2_ENABLE | GPIO_LED3_ENABLE;\r
\r
// Write the configuration\r
- MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_GPIO_CFG, GpioConf);\r
}\r
\r
return EFI_SUCCESS;\r
// Wait until it is up or until Time Out\r
Retries = FixedPcdGet32 (PcdLan9118DefaultNegotiationTimeout) / LAN9118_STALL;\r
while ((IndirectPHYRead32 (PHY_INDEX_BASIC_STATUS) & PHYSTS_LINK_STS) == 0) {\r
- MemoryFence();\r
gBS->Stall (LAN9118_STALL);\r
Retries--;\r
if (!Retries) {\r
\r
// Check if we want to clear tx\r
if (Flags & STOP_TX_CLEAR) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
}\r
\r
// Check if already stopped\r
}\r
\r
if (Flags & STOP_TX_CFG) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
\r
if (TxCfg & TXCFG_TX_ON) {\r
TxCfg |= TXCFG_STOP_TX;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
\r
// Wait for Tx to finish transmitting\r
- while (MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
+ while (Lan9118MmioRead32 (LAN9118_TX_CFG) & TXCFG_STOP_TX);\r
}\r
}\r
\r
\r
// Check if we want to clear receiver FIFOs\r
if (Flags & STOP_RX_CLEAR) {\r
- RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
+ RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
RxCfg |= RXCFG_RX_DUMP;\r
- MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
\r
- while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
+ while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
}\r
\r
return EFI_SUCCESS;\r
\r
// Check if we want to clear tx\r
if (Flags & START_TX_CLEAR) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
TxCfg |= TXCFG_TXS_DUMP | TXCFG_TXD_DUMP;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
}\r
\r
// Check if tx was started from MAC and enable if not\r
if (Flags & START_TX_MAC) {\r
MacCsr = IndirectMACRead32 (INDIRECT_MAC_INDEX_CR);\r
- MemoryFence();\r
if ((MacCsr & MACCR_TX_EN) == 0) {\r
MacCsr |= MACCR_TX_EN;\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- MemoryFence();\r
}\r
}\r
\r
// Check if tx was started from TX_CFG and enable if not\r
if (Flags & START_TX_CFG) {\r
- TxCfg = MmioRead32 (LAN9118_TX_CFG);\r
- MemoryFence();\r
+ TxCfg = Lan9118MmioRead32 (LAN9118_TX_CFG);\r
if ((TxCfg & TXCFG_TX_ON) == 0) {\r
TxCfg |= TXCFG_TX_ON;\r
- MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_TX_CFG, TxCfg);\r
}\r
}\r
\r
if ((MacCsr & MACCR_RX_EN) == 0) {\r
// Check if we want to clear receiver FIFOs before starting\r
if (Flags & START_RX_CLEAR) {\r
- RxCfg = MmioRead32 (LAN9118_RX_CFG);\r
+ RxCfg = Lan9118MmioRead32 (LAN9118_RX_CFG);\r
RxCfg |= RXCFG_RX_DUMP;\r
- MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_RX_CFG, RxCfg);\r
\r
- while (MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
+ while (Lan9118MmioRead32 (LAN9118_RX_CFG) & RXCFG_RX_DUMP);\r
}\r
\r
MacCsr |= MACCR_RX_EN;\r
IndirectMACWrite32 (INDIRECT_MAC_INDEX_CR, MacCsr);\r
- MemoryFence();\r
}\r
\r
return EFI_SUCCESS;\r
UINT32 FreeSpace;\r
\r
// Get the amount of free space from information register\r
- TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r
+ TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
FreeSpace = (TxInf & TXFIFOINF_TDFREE_MASK);\r
\r
return FreeSpace; // Value in bytes\r
UINT32 UsedSpace;\r
\r
// Get the amount of used space from information register\r
- TxInf = MmioRead32 (LAN9118_TX_FIFO_INF);\r
+ TxInf = Lan9118MmioRead32 (LAN9118_TX_FIFO_INF);\r
UsedSpace = (TxInf & TXFIFOINF_TXSUSED_MASK) >> 16;\r
\r
return UsedSpace << 2; // Value in bytes\r
UINT32 UsedSpace;\r
\r
// Get the amount of used space from information register\r
- RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r
+ RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
UsedSpace = (RxInf & RXFIFOINF_RXDUSED_MASK);\r
\r
return UsedSpace; // Value in bytes (rounded up to nearest DWORD)\r
UINT32 UsedSpace;\r
\r
// Get the amount of used space from information register\r
- RxInf = MmioRead32 (LAN9118_RX_FIFO_INF);\r
+ RxInf = Lan9118MmioRead32 (LAN9118_RX_FIFO_INF);\r
UsedSpace = (RxInf & RXFIFOINF_RXSUSED_MASK) >> 16;\r
\r
return UsedSpace << 2; // Value in bytes\r
// If we use the FIFOs (always use this first)\r
if (Flags & ALLOC_USE_FIFOS) {\r
// Read the current value of allocation\r
- HwConf = MmioRead32 (LAN9118_HW_CFG);\r
+ HwConf = Lan9118MmioRead32 (LAN9118_HW_CFG);\r
TxFifoOption = (HwConf >> 16) & 0xF;\r
\r
// Choose the correct size (always use larger than requested if possible)\r
// Clear and assign the new size option\r
HwConf &= ~(0xF0000);\r
HwConf |= ((TxFifoOption & 0xF) << 16);\r
- MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
- MemoryFence();\r
+ Lan9118MmioWrite32 (LAN9118_HW_CFG, HwConf);\r
\r
return EFI_SUCCESS;\r
}\r
IN UINT32 AddrLen\r
);\r
\r
+UINT32\r
+Lan9118RawMmioRead32(\r
+ UINTN Address,\r
+ UINTN Delay\r
+ );\r
+#define Lan9118MmioRead32(a) \\r
+ Lan9118RawMmioRead32(a, a ## _RD_DELAY)\r
+\r
+UINT32\r
+Lan9118RawMmioWrite32(\r
+ UINTN Address,\r
+ UINT32 Value,\r
+ UINTN Delay\r
+ );\r
+#define Lan9118MmioWrite32(a, v) \\r
+ Lan9118RawMmioWrite32(a, v, a ## _WR_DELAY)\r
+\r
/* ------------------ MAC CSR Access ------------------- */\r
\r
// Read from MAC indirect registers\r
UINTN Index;\r
PCI_ROOT_BRIDGE_APERTURE *MemApertures[4];\r
UINTN MemApertureIndex;\r
+ BOOLEAN ResourceAssigned;\r
+ LIST_ENTRY *Link;\r
\r
RootBridges = PciHostBridgeGetRootBridges (&RootBridgeCount);\r
if ((RootBridges == NULL) || (RootBridgeCount == 0)) {\r
HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;\r
HostBridge->CanRestarted = TRUE;\r
InitializeListHead (&HostBridge->RootBridges);\r
-\r
- HostBridge->ResAlloc.NotifyPhase = NotifyPhase;\r
- HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;\r
- HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;\r
- HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;\r
- HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;\r
- HostBridge->ResAlloc.SubmitResources = SubmitResources;\r
- HostBridge->ResAlloc.GetProposedResources = GetProposedResources;\r
- HostBridge->ResAlloc.PreprocessController = PreprocessController;\r
-\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &HostBridge->Handle,\r
- &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r
- NULL\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
- if (EFI_ERROR (Status)) {\r
- FreePool (HostBridge);\r
- PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);\r
- return Status;\r
- }\r
+ ResourceAssigned = FALSE;\r
\r
//\r
// Create Root Bridge Device Handle in this Host Bridge\r
//\r
// Create Root Bridge Handle Instance\r
//\r
- RootBridge = CreateRootBridge (&RootBridges[Index], HostBridge->Handle);\r
+ RootBridge = CreateRootBridge (&RootBridges[Index]);\r
ASSERT (RootBridge != NULL);\r
if (RootBridge == NULL) {\r
continue;\r
}\r
\r
- if (RootBridges[Index].Io.Limit > RootBridges[Index].Io.Base) {\r
+ //\r
+ // Make sure all root bridges share the same ResourceAssigned value.\r
+ //\r
+ if (Index == 0) {\r
+ ResourceAssigned = RootBridges[Index].ResourceAssigned;\r
+ } else {\r
+ ASSERT (ResourceAssigned == RootBridges[Index].ResourceAssigned);\r
+ }\r
+\r
+ if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) {\r
Status = AddIoSpace (\r
RootBridges[Index].Io.Base,\r
RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1\r
);\r
ASSERT_EFI_ERROR (Status);\r
+ if (ResourceAssigned) {\r
+ Status = gDS->AllocateIoSpace (\r
+ EfiGcdAllocateAddress,\r
+ EfiGcdIoTypeIo,\r
+ 0,\r
+ RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1,\r
+ &RootBridges[Index].Io.Base,\r
+ gImageHandle,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
}\r
\r
//\r
MemApertures[3] = &RootBridges[Index].PMemAbove4G;\r
\r
for (MemApertureIndex = 0; MemApertureIndex < sizeof (MemApertures) / sizeof (MemApertures[0]); MemApertureIndex++) {\r
- if (MemApertures[MemApertureIndex]->Limit > MemApertures[MemApertureIndex]->Base) {\r
+ if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) {\r
Status = AddMemoryMappedIoSpace (\r
MemApertures[MemApertureIndex]->Base,\r
MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,\r
if (EFI_ERROR (Status)) {\r
DEBUG ((DEBUG_WARN, "PciHostBridge driver failed to set EFI_MEMORY_UC to MMIO aperture - %r.\n", Status));\r
}\r
+ if (ResourceAssigned) {\r
+ Status = gDS->AllocateMemorySpace (\r
+ EfiGcdAllocateAddress,\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ 0,\r
+ MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,\r
+ &MemApertures[MemApertureIndex]->Base,\r
+ gImageHandle,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
}\r
}\r
//\r
// Insert Root Bridge Handle Instance\r
//\r
+ InsertTailList (&HostBridge->RootBridges, &RootBridge->Link);\r
+ }\r
+\r
+ //\r
+ // When resources were assigned, it's not needed to expose\r
+ // PciHostBridgeResourceAllocation protocol.\r
+ //\r
+ if (!ResourceAssigned) {\r
+ HostBridge->ResAlloc.NotifyPhase = NotifyPhase;\r
+ HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;\r
+ HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;\r
+ HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;\r
+ HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;\r
+ HostBridge->ResAlloc.SubmitResources = SubmitResources;\r
+ HostBridge->ResAlloc.GetProposedResources = GetProposedResources;\r
+ HostBridge->ResAlloc.PreprocessController = PreprocessController;\r
+\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &HostBridge->Handle,\r
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ for (Link = GetFirstNode (&HostBridge->RootBridges)\r
+ ; !IsNull (&HostBridge->RootBridges, Link)\r
+ ; Link = GetNextNode (&HostBridge->RootBridges, Link)\r
+ ) {\r
+ RootBridge = ROOT_BRIDGE_FROM_LINK (Link);\r
+ RootBridge->RootBridgeIo.ParentHandle = HostBridge->Handle;\r
+\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&RootBridge->Handle,\r
&gEfiDevicePathProtocolGuid, RootBridge->DevicePath,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
- InsertTailList (&HostBridge->RootBridges, &RootBridge->Link);\r
}\r
PciHostBridgeFreeRootBridges (RootBridges, RootBridgeCount);\r
return Status;\r
Construct the Pci Root Bridge instance.\r
\r
@param Bridge The root bridge instance.\r
- @param HostBridgeHandle Handle to the HostBridge.\r
\r
@return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created\r
or NULL if creation fails.\r
**/\r
PCI_ROOT_BRIDGE_INSTANCE *\r
CreateRootBridge (\r
- IN PCI_ROOT_BRIDGE *Bridge,\r
- IN EFI_HANDLE HostBridgeHandle\r
+ IN PCI_ROOT_BRIDGE *Bridge\r
);\r
\r
//\r
Construct the Pci Root Bridge instance.\r
\r
@param Bridge The root bridge instance.\r
- @param HostBridgeHandle Handle to the HostBridge.\r
\r
@return The pointer to PCI_ROOT_BRIDGE_INSTANCE just created\r
or NULL if creation fails.\r
**/\r
PCI_ROOT_BRIDGE_INSTANCE *\r
CreateRootBridge (\r
- IN PCI_ROOT_BRIDGE *Bridge,\r
- IN EFI_HANDLE HostBridgeHandle\r
+ IN PCI_ROOT_BRIDGE *Bridge\r
)\r
{\r
PCI_ROOT_BRIDGE_INSTANCE *RootBridge;\r
PCI_RESOURCE_TYPE Index;\r
CHAR16 *DevicePathStr;\r
+ PCI_ROOT_BRIDGE_APERTURE *Aperture;\r
\r
DevicePathStr = NULL;\r
\r
//\r
// Make sure Mem and MemAbove4G apertures are valid\r
//\r
- if (Bridge->Mem.Base < Bridge->Mem.Limit) {\r
+ if (Bridge->Mem.Base <= Bridge->Mem.Limit) {\r
ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r
if (Bridge->Mem.Limit >= SIZE_4GB) {\r
return NULL;\r
}\r
}\r
- if (Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) {\r
+ if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {\r
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r
if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r
return NULL;\r
}\r
}\r
- if (Bridge->PMem.Base < Bridge->PMem.Limit) {\r
+ if (Bridge->PMem.Base <= Bridge->PMem.Limit) {\r
ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r
if (Bridge->PMem.Limit >= SIZE_4GB) {\r
return NULL;\r
}\r
}\r
- if (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) {\r
+ if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {\r
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r
if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r
return NULL;\r
}\r
}\r
\r
- if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
- //\r
- // If this bit is set, then the PCI Root Bridge does not\r
- // support separate windows for Non-prefetchable and Prefetchable\r
- // memory.\r
- //\r
- ASSERT (Bridge->PMem.Base >= Bridge->PMem.Limit);\r
- ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);\r
- if ((Bridge->PMem.Base < Bridge->PMem.Limit) ||\r
- (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)\r
- ) {\r
- return NULL;\r
+ //\r
+ // Ignore AllocationAttributes when resources were already assigned.\r
+ //\r
+ if (!Bridge->ResourceAssigned) {\r
+ if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0) {\r
+ //\r
+ // If this bit is set, then the PCI Root Bridge does not\r
+ // support separate windows for Non-prefetchable and Prefetchable\r
+ // memory.\r
+ //\r
+ ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
+ ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+ if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
+ (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
+ ) {\r
+ return NULL;\r
+ }\r
}\r
- }\r
\r
- if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r
- //\r
- // If this bit is not set, then the PCI Root Bridge does not support\r
- // 64 bit memory windows.\r
- //\r
- ASSERT (Bridge->MemAbove4G.Base >= Bridge->MemAbove4G.Limit);\r
- ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);\r
- if ((Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) ||\r
- (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)\r
- ) {\r
- return NULL;\r
+ if ((Bridge->AllocationAttributes & EFI_PCI_HOST_BRIDGE_MEM64_DECODE) == 0) {\r
+ //\r
+ // If this bit is not set, then the PCI Root Bridge does not support\r
+ // 64 bit memory windows.\r
+ //\r
+ ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
+ ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+ if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
+ (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
+ ) {\r
+ return NULL;\r
+ }\r
}\r
}\r
\r
CopyMem (&RootBridge->Io, &Bridge->Io, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
CopyMem (&RootBridge->Mem, &Bridge->Mem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
CopyMem (&RootBridge->MemAbove4G, &Bridge->MemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
-\r
+ CopyMem (&RootBridge->PMem, &Bridge->PMem, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
+ CopyMem (&RootBridge->PMemAbove4G, &Bridge->PMemAbove4G, sizeof (PCI_ROOT_BRIDGE_APERTURE));\r
\r
for (Index = TypeIo; Index < TypeMax; Index++) {\r
- RootBridge->ResAllocNode[Index].Type = Index;\r
- RootBridge->ResAllocNode[Index].Base = 0;\r
- RootBridge->ResAllocNode[Index].Length = 0;\r
- RootBridge->ResAllocNode[Index].Status = ResNone;\r
+ switch (Index) {\r
+ case TypeBus:\r
+ Aperture = &RootBridge->Bus;\r
+ break;\r
+ case TypeIo:\r
+ Aperture = &RootBridge->Io;\r
+ break;\r
+ case TypeMem32:\r
+ Aperture = &RootBridge->Mem;\r
+ break;\r
+ case TypeMem64:\r
+ Aperture = &RootBridge->MemAbove4G;\r
+ break;\r
+ case TypePMem32:\r
+ Aperture = &RootBridge->PMem;\r
+ break;\r
+ case TypePMem64:\r
+ Aperture = &RootBridge->PMemAbove4G;\r
+ break;\r
+ default:\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ RootBridge->ResAllocNode[Index].Type = Index;\r
+ if (Bridge->ResourceAssigned && (Aperture->Limit >= Aperture->Base)) {\r
+ RootBridge->ResAllocNode[Index].Base = Aperture->Base;\r
+ RootBridge->ResAllocNode[Index].Length = Aperture->Limit - Aperture->Base + 1;\r
+ RootBridge->ResAllocNode[Index].Status = ResAllocated;\r
+ } else {\r
+ RootBridge->ResAllocNode[Index].Base = 0;\r
+ RootBridge->ResAllocNode[Index].Length = 0;\r
+ RootBridge->ResAllocNode[Index].Status = ResNone;\r
+ }\r
}\r
\r
RootBridge->RootBridgeIo.SegmentNumber = Bridge->Segment;\r
- RootBridge->RootBridgeIo.ParentHandle = HostBridgeHandle;\r
RootBridge->RootBridgeIo.PollMem = RootBridgeIoPollMem;\r
RootBridge->RootBridgeIo.PollIo = RootBridgeIoPollIo;\r
RootBridge->RootBridgeIo.Mem.Read = RootBridgeIoMemRead;\r
/** @file\r
SerialIo implementation for PCI or SIO UARTs.\r
\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
return EFI_SUCCESS;\r
}\r
\r
-/**\r
- Flush the serial hardware transmit FIFO and shift register.\r
-\r
- @param SerialDevice The device to flush.\r
-**/\r
-VOID\r
-SerialFlushTransmitFifo (\r
- SERIAL_DEV *SerialDevice\r
- )\r
-{\r
- SERIAL_PORT_LSR Lsr;\r
-\r
- //\r
- // Wait for the serial port to be ready, to make sure both the transmit FIFO\r
- // and shift register empty.\r
- //\r
- do {\r
- Lsr.Data = READ_LSR (SerialDevice);\r
- } while (Lsr.Bits.Temt == 0);\r
-}\r
-\r
//\r
// Interface Functions\r
//\r
\r
Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
\r
- SerialFlushTransmitFifo (SerialDevice);\r
-\r
//\r
// Make sure DLAB is 0.\r
//\r
\r
Tpl = gBS->RaiseTPL (TPL_NOTIFY);\r
\r
- SerialFlushTransmitFifo (SerialDevice);\r
-\r
//\r
// Put serial port on Divisor Latch Mode\r
//\r
///< Extended (4096-byte) Configuration Space.\r
///< When TRUE, the root bridge supports\r
///< 256-byte Configuration Space only.\r
+ BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.\r
+ ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.\r
UINT64 AllocationAttributes; ///< Allocation attributes.\r
///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r
///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r
--- /dev/null
+/** @file\r
+ Header file of OVMF instance of PciHostBridgeLib.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+ UINTN *NumberOfRootBridges\r
+);\r
+\r
+/**\r
+ Initialize a PCI_ROOT_BRIDGE structure.\r
+\r
+ @param[in] Supports Supported attributes.\r
+\r
+ @param[in] Attributes Initial attributes.\r
+\r
+ @param[in] AllocAttributes Allocation attributes.\r
+\r
+ @param[in] RootBusNumber The bus number to store in RootBus.\r
+\r
+ @param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
+ assigned to any subordinate bus found behind any\r
+ PCI bridge hanging off this root bus.\r
+\r
+ The caller is repsonsible for ensuring that\r
+ RootBusNumber <= MaxSubBusNumber. If\r
+ RootBusNumber equals MaxSubBusNumber, then the\r
+ root bus has no room for subordinate buses.\r
+\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+\r
+ @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
+ caller) that should be filled in by this\r
+ function.\r
+\r
+ @retval EFI_SUCCESS Initialization successful. A device path\r
+ consisting of an ACPI device path node, with\r
+ UID = RootBusNumber, has been allocated and\r
+ linked into RootBus.\r
+\r
+ @retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
+**/\r
+EFI_STATUS\r
+InitRootBridge (\r
+ IN UINT64 Supports,\r
+ IN UINT64 Attributes,\r
+ IN UINT64 AllocAttributes,\r
+ IN UINT8 RootBusNumber,\r
+ IN UINT8 MaxSubBusNumber,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
+ OUT PCI_ROOT_BRIDGE *RootBus\r
+ );\r
#include <Library/PciHostBridgeLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
+#include "PciHostBridge.h"\r
\r
\r
#pragma pack(1)\r
}\r
};\r
\r
+STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r
\r
/**\r
Initialize a PCI_ROOT_BRIDGE structure.\r
\r
- param[in] RootBusNumber The bus number to store in RootBus.\r
+ @param[in] Supports Supported attributes.\r
\r
- param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
+ @param[in] Attributes Initial attributes.\r
+\r
+ @param[in] AllocAttributes Allocation attributes.\r
+\r
+ @param[in] RootBusNumber The bus number to store in RootBus.\r
+\r
+ @param[in] MaxSubBusNumber The inclusive maximum bus number that can be\r
assigned to any subordinate bus found behind any\r
PCI bridge hanging off this root bus.\r
\r
RootBusNumber equals MaxSubBusNumber, then the\r
root bus has no room for subordinate buses.\r
\r
- param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
+ @param[in] Io IO aperture.\r
+\r
+ @param[in] Mem MMIO aperture.\r
+\r
+ @param[in] MemAbove4G MMIO aperture above 4G.\r
+\r
+ @param[in] PMem Prefetchable MMIO aperture.\r
+\r
+ @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
+\r
+ @param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the\r
caller) that should be filled in by this\r
function.\r
\r
\r
@retval EFI_OUT_OF_RESOURCES Memory allocation failed.\r
**/\r
-STATIC\r
EFI_STATUS\r
InitRootBridge (\r
- IN UINT8 RootBusNumber,\r
- IN UINT8 MaxSubBusNumber,\r
- OUT PCI_ROOT_BRIDGE *RootBus\r
+ IN UINT64 Supports,\r
+ IN UINT64 Attributes,\r
+ IN UINT64 AllocAttributes,\r
+ IN UINT8 RootBusNumber,\r
+ IN UINT8 MaxSubBusNumber,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,\r
+ OUT PCI_ROOT_BRIDGE *RootBus\r
)\r
{\r
OVMF_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;\r
\r
RootBus->Segment = 0;\r
\r
- RootBus->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
- EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
- EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
- EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
- EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
- EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
- RootBus->Attributes = RootBus->Supports;\r
+ RootBus->Supports = Supports;\r
+ RootBus->Attributes = Attributes;\r
\r
RootBus->DmaAbove4G = FALSE;\r
\r
- RootBus->AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
- RootBus->PMem.Base = 0;\r
- RootBus->PMem.Limit = 0;\r
- RootBus->PMemAbove4G.Base = 0;\r
- RootBus->PMemAbove4G.Limit = 0;\r
- RootBus->MemAbove4G.Base = 0;\r
- RootBus->MemAbove4G.Limit = 0;\r
-\r
- if (PcdGet64 (PcdPciMmio64Size) > 0) {\r
- RootBus->AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
- RootBus->MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r
- RootBus->MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r
- (PcdGet64 (PcdPciMmio64Size) - 1);\r
- }\r
-\r
+ RootBus->AllocationAttributes = AllocAttributes;\r
RootBus->Bus.Base = RootBusNumber;\r
RootBus->Bus.Limit = MaxSubBusNumber;\r
- RootBus->Io.Base = PcdGet64 (PcdPciIoBase);\r
- RootBus->Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
- RootBus->Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
- RootBus->Mem.Limit = PcdGet64 (PcdPciMmio32Base) +\r
- (PcdGet64 (PcdPciMmio32Size) - 1);\r
+ CopyMem (&RootBus->Io, Io, sizeof (*Io));\r
+ CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));\r
+ CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));\r
+ CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));\r
+ CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));\r
\r
RootBus->NoExtendedConfigSpace = (PcdGet16 (PcdOvmfHostBridgePciDevId) !=\r
INTEL_Q35_MCH_DEVICE_ID);\r
UINTN Initialized;\r
UINTN LastRootBridgeNumber;\r
UINTN RootBridgeNumber;\r
+ UINT64 Attributes;\r
+ UINT64 AllocationAttributes;\r
+ PCI_ROOT_BRIDGE_APERTURE Io;\r
+ PCI_ROOT_BRIDGE_APERTURE Mem;\r
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r
+\r
+ if (PcdGetBool (PcdPciDisableBusEnumeration)) {\r
+ return ScanForRootBridges (Count);\r
+ }\r
+\r
+ Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+\r
+ AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r
+ if (PcdGet64 (PcdPciMmio64Size) > 0) {\r
+ AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
+ MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r
+ MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r
+ PcdGet64 (PcdPciMmio64Size) - 1;\r
+ } else {\r
+ CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));\r
+ }\r
+\r
+ Io.Base = PcdGet64 (PcdPciIoBase);\r
+ Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r
+ Mem.Base = PcdGet64 (PcdPciMmio32Base);\r
+ Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);\r
\r
*Count = 0;\r
\r
// because now we know how big a bus number range *that* one has, for any\r
// subordinate buses that might exist behind PCI bridges hanging off it.\r
//\r
- Status = InitRootBridge ((UINT8)LastRootBridgeNumber,\r
- (UINT8)(RootBridgeNumber - 1), &Bridges[Initialized]);\r
+ Status = InitRootBridge (\r
+ Attributes,\r
+ Attributes,\r
+ AllocationAttributes,\r
+ (UINT8) LastRootBridgeNumber,\r
+ (UINT8) (RootBridgeNumber - 1),\r
+ &Io,\r
+ &Mem,\r
+ &MemAbove4G,\r
+ &mNonExistAperture,\r
+ &mNonExistAperture,\r
+ &Bridges[Initialized]\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto FreeBridges;\r
}\r
// Install the last root bus (which might be the only, ie. main, root bus, if\r
// we've found no extra root buses).\r
//\r
- Status = InitRootBridge ((UINT8)LastRootBridgeNumber, PCI_MAX_BUS,\r
- &Bridges[Initialized]);\r
+ Status = InitRootBridge (\r
+ Attributes,\r
+ Attributes,\r
+ AllocationAttributes,\r
+ (UINT8) LastRootBridgeNumber,\r
+ PCI_MAX_BUS,\r
+ &Io,\r
+ &Mem,\r
+ &MemAbove4G,\r
+ &mNonExistAperture,\r
+ &mNonExistAperture,\r
+ &Bridges[Initialized]\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto FreeBridges;\r
}\r
\r
[Sources]\r
PciHostBridgeLib.c\r
+ XenSupport.c\r
+ PciHostBridge.h\r
\r
[Packages]\r
MdeModulePkg/MdeModulePkg.dec\r
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base\r
gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration\r
--- /dev/null
+/** @file\r
+ Scan the entire PCI bus for root bridges to support OVMF above Xen.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available\r
+ under the terms and conditions of the BSD License which accompanies this\r
+ distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/Q35MchIch9.h>\r
+\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciHostBridgeLib.h>\r
+#include <Library/PciLib.h>\r
+#include "PciHostBridge.h"\r
+\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeBarExisted (\r
+ IN UINT64 Address,\r
+ OUT UINT32 *OriginalValue,\r
+ OUT UINT32 *Value\r
+ )\r
+{\r
+ //\r
+ // Preserve the original value\r
+ //\r
+ *OriginalValue = PciRead32 (Address);\r
+\r
+ //\r
+ // Disable timer interrupt while the BAR is probed\r
+ //\r
+ DisableInterrupts ();\r
+\r
+ PciWrite32 (Address, 0xFFFFFFFF);\r
+ *Value = PciRead32 (Address);\r
+ PciWrite32 (Address, *OriginalValue);\r
+\r
+ //\r
+ // Enable interrupt\r
+ //\r
+ EnableInterrupts ();\r
+}\r
+\r
+STATIC\r
+VOID\r
+PcatPciRootBridgeParseBars (\r
+ IN UINT16 Command,\r
+ IN UINTN Bus,\r
+ IN UINTN Device,\r
+ IN UINTN Function,\r
+ IN UINTN BarOffsetBase,\r
+ IN UINTN BarOffsetEnd,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
+\r
+)\r
+{\r
+ UINT32 OriginalValue;\r
+ UINT32 Value;\r
+ UINT32 OriginalUpperValue;\r
+ UINT32 UpperValue;\r
+ UINT64 Mask;\r
+ UINTN Offset;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Limit;\r
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
+\r
+ for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalValue, &Value\r
+ );\r
+ if (Value == 0) {\r
+ continue;\r
+ }\r
+ if ((Value & BIT0) == BIT0) {\r
+ //\r
+ // IO Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
+ Mask = 0xfffffffc;\r
+ Base = OriginalValue & Mask;\r
+ Length = ((~(Value & Mask)) & Mask) + 0x04;\r
+ if (!(Value & 0xFFFF0000)) {\r
+ Length &= 0x0000FFFF;\r
+ }\r
+ Limit = Base + Length - 1;\r
+\r
+ if (Base < Limit) {\r
+ if (Io->Base > Base) {\r
+ Io->Base = Base;\r
+ }\r
+ if (Io->Limit < Limit) {\r
+ Io->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ } else {\r
+ //\r
+ // Mem Bar\r
+ //\r
+ if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
+\r
+ Mask = 0xfffffff0;\r
+ Base = OriginalValue & Mask;\r
+ Length = Value & Mask;\r
+\r
+ if ((Value & (BIT1 | BIT2)) == 0) {\r
+ //\r
+ // 32bit\r
+ //\r
+ Length = ((~Length) + 1) & 0xffffffff;\r
+\r
+ if ((Value & BIT3) == BIT3) {\r
+ MemAperture = PMem;\r
+ } else {\r
+ MemAperture = Mem;\r
+ }\r
+ } else {\r
+ //\r
+ // 64bit\r
+ //\r
+ Offset += 4;\r
+ PcatPciRootBridgeBarExisted (\r
+ PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
+ &OriginalUpperValue,\r
+ &UpperValue\r
+ );\r
+\r
+ Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
+ Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
+ Length = (~Length) + 1;\r
+\r
+ if ((Value & BIT3) == BIT3) {\r
+ MemAperture = PMemAbove4G;\r
+ } else {\r
+ MemAperture = MemAbove4G;\r
+ }\r
+ }\r
+\r
+ Limit = Base + Length - 1;\r
+ if (Base < Limit) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+PCI_ROOT_BRIDGE *\r
+ScanForRootBridges (\r
+ UINTN *NumberOfRootBridges\r
+ )\r
+{\r
+ UINTN PrimaryBus;\r
+ UINTN SubBus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINTN NumberOfDevices;\r
+ UINT64 Address;\r
+ PCI_TYPE01 Pci;\r
+ UINT64 Attributes;\r
+ UINT64 Base;\r
+ UINT64 Limit;\r
+ UINT64 Value;\r
+ PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
+ PCI_ROOT_BRIDGE *RootBridges;\r
+ UINTN BarOffsetEnd;\r
+\r
+\r
+ *NumberOfRootBridges = 0;\r
+ RootBridges = NULL;\r
+\r
+ //\r
+ // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
+ // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
+ // root bridge's subordinate bus number + 1.\r
+ //\r
+ for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
+ SubBus = PrimaryBus;\r
+ Attributes = 0;\r
+ Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
+ Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
+ //\r
+ // Scan all the PCI devices on the primary bus of the PCI root bridge\r
+ //\r
+ for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
+\r
+ for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
+\r
+ //\r
+ // Compute the PCI configuration address of the PCI device to probe\r
+ //\r
+ Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
+\r
+ //\r
+ // Read the Vendor ID from the PCI Configuration Header\r
+ //\r
+ if (PciRead16 (Address) == MAX_UINT16) {\r
+ if (Function == 0) {\r
+ //\r
+ // If the PCI Configuration Read fails, or a PCI device does not\r
+ // exist, then skip this entire PCI device\r
+ //\r
+ break;\r
+ } else {\r
+ //\r
+ // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
+ // PCI function.\r
+ //\r
+ continue;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Read the entire PCI Configuration Header\r
+ //\r
+ PciReadBuffer (Address, sizeof (Pci), &Pci);\r
+\r
+ //\r
+ // Increment the number of PCI device found on the primary bus of the\r
+ // PCI root bridge\r
+ //\r
+ NumberOfDevices++;\r
+\r
+ //\r
+ // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
+ // register of the PCI Config Header\r
+ //\r
+ if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ }\r
+\r
+ BarOffsetEnd = 0;\r
+\r
+ //\r
+ // PCI-PCI Bridge\r
+ //\r
+ if (IS_PCI_BRIDGE (&Pci)) {\r
+ //\r
+ // Get the Bus range that the PPB is decoding\r
+ //\r
+ if (Pci.Bridge.SubordinateBus > SubBus) {\r
+ //\r
+ // If the suborinate bus number of the PCI-PCI bridge is greater\r
+ // than the PCI root bridge's current subordinate bus number,\r
+ // then update the PCI root bridge's subordinate bus number\r
+ //\r
+ SubBus = Pci.Bridge.SubordinateBus;\r
+ }\r
+\r
+ //\r
+ // Get the I/O range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.IoBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
+ Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
+ if (Value == BIT0) {\r
+ Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
+ Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
+ }\r
+ if (Base < Limit) {\r
+ if (Io.Base > Base) {\r
+ Io.Base = Base;\r
+ }\r
+ if (Io.Limit < Limit) {\r
+ Io.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Memory range that the PPB is decoding\r
+ //\r
+ Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
+ if (Base < Limit) {\r
+ if (Mem.Base > Base) {\r
+ Mem.Base = Base;\r
+ }\r
+ if (Mem.Limit < Limit) {\r
+ Mem.Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Get the Prefetchable Memory range that the PPB is decoding\r
+ //\r
+ Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
+ Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
+ Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
+ << 16) | 0xfffff;\r
+ MemAperture = &PMem;\r
+ if (Value == BIT0) {\r
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
+ MemAperture = &PMemAbove4G;\r
+ }\r
+ if (Base < Limit) {\r
+ if (MemAperture->Base > Base) {\r
+ MemAperture->Base = Base;\r
+ }\r
+ if (MemAperture->Limit < Limit) {\r
+ MemAperture->Limit = Limit;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Look at the PPB Configuration for legacy decoding attributes\r
+ //\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
+ == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
+ == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
+ != 0) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+ }\r
+\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
+ } else {\r
+ //\r
+ // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
+ // Ranges, and Prefetchable Memory Ranges the device is decoding\r
+ //\r
+ if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
+ BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
+ }\r
+ }\r
+\r
+ PcatPciRootBridgeParseBars (\r
+ Pci.Hdr.Command,\r
+ PrimaryBus,\r
+ Device,\r
+ Function,\r
+ OFFSET_OF (PCI_TYPE00, Device.Bar),\r
+ BarOffsetEnd,\r
+ &Io,\r
+ &Mem, &MemAbove4G,\r
+ &PMem, &PMemAbove4G\r
+ );\r
+\r
+ //\r
+ // See if the PCI device is an IDE controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
+ PCI_CLASS_MASS_STORAGE_IDE)) {\r
+ if (Pci.Hdr.ClassCode[0] & 0x80) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x01) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
+ }\r
+ if (Pci.Hdr.ClassCode[0] & 0x04) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // See if the PCI device is a legacy VGA controller or\r
+ // a standard VGA controller\r
+ //\r
+ if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
+ IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
+ ) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+ }\r
+\r
+ //\r
+ // See if the PCI Device is a PCI - ISA or PCI - EISA\r
+ // or ISA_POSITIVIE_DECODE Bridge device\r
+ //\r
+ if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
+ if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
+ Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
+ Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
+ }\r
+ }\r
+\r
+ //\r
+ // If this device is not a multi function device, then skip the rest\r
+ // of this PCI device\r
+ //\r
+ if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If at least one PCI device was found on the primary bus of this PCI\r
+ // root bridge, then the PCI root bridge exists.\r
+ //\r
+ if (NumberOfDevices > 0) {\r
+ RootBridges = ReallocatePool (\r
+ (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
+ (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
+ RootBridges\r
+ );\r
+ ASSERT (RootBridges != NULL);\r
+ InitRootBridge (\r
+ Attributes, Attributes, 0,\r
+ (UINT8) PrimaryBus, (UINT8) SubBus,\r
+ &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
+ &RootBridges[*NumberOfRootBridges]\r
+ );\r
+ RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
+ //\r
+ // Increment the index for the next PCI Root Bridge\r
+ //\r
+ (*NumberOfRootBridges)++;\r
+ }\r
+ }\r
+\r
+ return RootBridges;\r
+}\r
projects / mirror_edk2.git / commitdiff