Synchronize interface function comment from declaration in library class header file...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6957 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.c b/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.c
index 5517c4a4e11d32c8ac7ab5addc0dbe52c6ff30fe..72f793237c9d01a2b61227bf8b196eecdd6ed76c 100644 (file)
--- a/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.c
+++ b/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.c
@@ -68,7 +68,7 @@ SmbusLibConstructor (
   @param  Status          Return status for the executed command.\r
                           This is an optional parameter and may be NULL.\r
 \r
-  @return The actual number of bytes that are executed for this operation..\r
+  @return The actual number of bytes that are executed for this operation.\r
 \r
 **/\r
 UINTN\r

diff --git a/MdePkg/Library/UefiDriverEntryPoint/DriverEntryPoint.c b/MdePkg/Library/UefiDriverEntryPoint/DriverEntryPoint.c
index 02d7160588c0d3a4f7a54250f4c383f7c3cf7f8f..68d6a4bb94a348df51b261e61d0342387bb1ac90 100644 (file)
--- a/MdePkg/Library/UefiDriverEntryPoint/DriverEntryPoint.c
+++ b/MdePkg/Library/UefiDriverEntryPoint/DriverEntryPoint.c
@@ -79,7 +79,8 @@ _DriverUnloadHandler (
   @param  ImageHandle  ImageHandle of the loaded driver.\r
   @param  SystemTable  Pointer to the EFI System Table.\r
 \r
-  @retval  EFI_SUCCESS               One or more of the drivers returned a success code.\r
+  @retval  EFI_SUCCESS               The DXE Driver, DXE Runtime Driver, DXE SMM Driver,\r
+                                     or UEFI Driver exited normally.\r
   @retval  EFI_INCOMPATIBLE_VERSION  _gUefiDriverRevision is greater than SystemTable->Hdr.Revision.\r
   @retval  Other                     Return value from ProcessModuleEntryPointList().\r
 \r

diff --git a/MdePkg/Library/UefiLib/UefiLib.c b/MdePkg/Library/UefiLib/UefiLib.c
index e263a06f89b223095c13da3ec4ee2af536251161..e7d8a5089ec04258636083f4d7ff486689c5a839 100644 (file)
--- a/MdePkg/Library/UefiLib/UefiLib.c
+++ b/MdePkg/Library/UefiLib/UefiLib.c
@@ -689,7 +689,6 @@ LookupUnicodeString (
 \r
 **/\r
 EFI_STATUS\r
-\r
 EFIAPI\r
 LookupUnicodeString2 (\r
   IN CONST CHAR8                     *Language,\r

diff --git a/MdePkg/Library/UefiLib/UefiNotTiano.c b/MdePkg/Library/UefiLib/UefiNotTiano.c
index dcf2b860985cc02893559e11f0eb6bed6b9da171..a00b3d19feae708933ee4bcaee417cd8267162e6 100644 (file)
--- a/MdePkg/Library/UefiLib/UefiNotTiano.c
+++ b/MdePkg/Library/UefiLib/UefiNotTiano.c
@@ -75,8 +75,8 @@ EfiCreateEventLegacyBoot (
 \r
 /**\r
   Create an EFI event in the Legacy Boot Event Group and allows\r
-  the caller to specify a notification function.\r
-\r
+  the caller to specify a notification function.  \r
+  \r
   This function abstracts the creation of the Legacy Boot Event.\r
   The Framework moved from a proprietary to UEFI 2.0 based mechanism.\r
   This library abstracts the caller from how this event is created to prevent\r
@@ -160,8 +160,8 @@ EfiCreateEventReadyToBoot (
 \r
 /**\r
   Create an EFI event in the Ready To Boot Event Group and allows\r
-  the caller to specify a notification function.\r
-\r
+  the caller to specify a notification function.  \r
+  \r
   This function abstracts the creation of the Ready to Boot Event.\r
   The Framework moved from a proprietary to UEFI 2.0 based mechanism.\r
   This library abstracts the caller from how this event is created to prevent\r
@@ -282,17 +282,17 @@ EfiSignalEventLegacyBoot (
   @retval Other             FvDevicePathNode is valid and pointer to NameGuid was returned.\r
 \r
 **/\r
-EFI_GUID*\r
+EFI_GUID *\r
 EFIAPI\r
 EfiGetNameGuidFromFwVolDevicePathNode (\r
-  IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH  *FvFileDevicePathNode\r
+  IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH  *FvDevicePathNode\r
   )\r
 {\r
-  ASSERT (FvFileDevicePathNode != NULL);\r
+  ASSERT (FvDevicePathNode != NULL);\r
 \r
-  if (DevicePathType (&FvFileDevicePathNode->Header) == MEDIA_DEVICE_PATH &&\r
-      DevicePathSubType (&FvFileDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) {\r
-    return (EFI_GUID *) &FvFileDevicePathNode->FvFileName;\r
+  if (DevicePathType (&FvDevicePathNode->Header) == MEDIA_DEVICE_PATH &&\r
+      DevicePathSubType (&FvDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) {\r
+    return (EFI_GUID *) &FvDevicePathNode->FvFileName;\r
   }\r
 \r
   return NULL;\r
@@ -318,20 +318,20 @@ EfiGetNameGuidFromFwVolDevicePathNode (
 VOID\r
 EFIAPI\r
 EfiInitializeFwVolDevicepathNode (\r
-  IN OUT    MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileDevicePathNode,\r
-  IN CONST  EFI_GUID                          *NameGuid\r
+  IN OUT MEDIA_FW_VOL_FILEPATH_DEVICE_PATH  *FvDevicePathNode,\r
+  IN CONST EFI_GUID                         *NameGuid\r
   )\r
 {\r
-  ASSERT (FvFileDevicePathNode  != NULL);\r
+  ASSERT (FvDevicePathNode != NULL);\r
   ASSERT (NameGuid          != NULL);\r
 \r
   //\r
   // Use the new Device path that does not conflict with the UEFI\r
   //\r
-  FvFileDevicePathNode->Header.Type     = MEDIA_DEVICE_PATH;\r
-  FvFileDevicePathNode->Header.SubType  = MEDIA_PIWG_FW_FILE_DP;\r
-  SetDevicePathNodeLength (&FvFileDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH));\r
+  FvDevicePathNode->Header.Type     = MEDIA_DEVICE_PATH;\r
+  FvDevicePathNode->Header.SubType  = MEDIA_PIWG_FW_FILE_DP;\r
+  SetDevicePathNodeLength (&FvDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH));\r
 \r
-  CopyGuid (&FvFileDevicePathNode->FvFileName, NameGuid);\r
+  CopyGuid (&FvDevicePathNode->FvFileName, NameGuid);\r
 }\r
 \r

diff --git a/MdePkg/Library/UefiMemoryLib/CompareMemWrapper.c b/MdePkg/Library/UefiMemoryLib/CompareMemWrapper.c
index 641259d507f04c9fa676d1a19eaff207822d53ba..27da96d56b08f56c8d012a723d616a9c0d34b598 100644 (file)
--- a/MdePkg/Library/UefiMemoryLib/CompareMemWrapper.c
+++ b/MdePkg/Library/UefiMemoryLib/CompareMemWrapper.c
@@ -31,7 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   If all Length bytes of the two buffers are identical, then 0 is returned.  Otherwise, the\r
   value returned is the first mismatched byte in SourceBuffer subtracted from the first\r
   mismatched byte in DestinationBuffer.\r
-\r
+  \r
   If Length > 0 and DestinationBuffer is NULL, then ASSERT().\r
   If Length > 0 and SourceBuffer is NULL, then ASSERT().\r
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().\r
@@ -44,7 +44,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @return 0                 All Length bytes of the two buffers are identical.\r
   @retval Non-zero          The first mismatched byte in SourceBuffer subtracted from the first\r
                             mismatched byte in DestinationBuffer.\r
-                                                       \r
+                            \r
 **/\r
 INTN\r
 EFIAPI\r

diff --git a/MdePkg/Library/UefiMemoryLib/MemLibInternals.h b/MdePkg/Library/UefiMemoryLib/MemLibInternals.h
index 27c3c71851f36158c5f56e1b1459b1411b483442..4f3a7f700ea1916664d2e7ddff23152eb3b164b1 100644 (file)
--- a/MdePkg/Library/UefiMemoryLib/MemLibInternals.h
+++ b/MdePkg/Library/UefiMemoryLib/MemLibInternals.h
@@ -36,38 +36,42 @@
 #include <Library/BaseLib.h>\r
 \r
 /**\r
-  Copy Length bytes from Source to Destination.\r
+  Copies a source buffer to a destination buffer, and returns the destination buffer.\r
 \r
-  @param  DestinationBuffer Target of copy\r
-  @param  SourceBuffer Place to copy from\r
-  @param  Length Number of bytes to copy\r
+  This function wraps the gBS->CopyMem().\r
 \r
-  @return Destination\r
+  @param  DestinationBuffer   Pointer to the destination buffer of the memory copy.\r
+  @param  SourceBuffer        Pointer to the source buffer of the memory copy.\r
+  @param  Length              Number of bytes to copy from SourceBuffer to DestinationBuffer.\r
+\r
+  @return DestinationBuffer.\r
 \r
 **/\r
 VOID *\r
 EFIAPI\r
 InternalMemCopyMem (\r
-  OUT     VOID                      *DestinationBuffer,\r
-  IN      CONST VOID                *SourceBuffer,\r
+  OUT     VOID                      *Destination,\r
+  IN      CONST VOID                *Source,\r
   IN      UINTN                     Length\r
   );\r
 \r
 /**\r
-  Set Buffer to Value for Size bytes.\r
+  Fills a target buffer with a byte value, and returns the target buffer.\r
 \r
-  @param  Buffer Memory to set.\r
-  @param  Length Number of bytes to set\r
-  @param  Value Value of the set operation.\r
+  This function wraps the gBS->SetMem().\r
 \r
-  @return Buffer\r
+  @param  Buffer    Memory to set.\r
+  @param  Size      Number of bytes to set.\r
+  @param  Value     Value of the set operation.\r
+\r
+  @return Buffer.\r
 \r
 **/\r
 VOID *\r
 EFIAPI\r
 InternalMemSetMem (\r
   OUT     VOID                      *Buffer,\r
-  IN      UINTN                     Length,\r
+  IN      UINTN                     Size,\r
   IN      UINT8                     Value\r
   );\r
 \r

diff --git a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
index 5a43f66f860786ab5d28db3c6ee32adb39896841..ff95ec7862a49119b2dcaf46357ac53fef281fac 100644 (file)
--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
@@ -143,9 +143,12 @@ DxePciLibPciRootBridgeIoWriteWorker (
 }\r
 \r
 /**\r
-  Register a PCI device so PCI configuration registers may be accessed after \r
+  Registers a PCI device so PCI configuration registers may be accessed after \r
   SetVirtualAddressMap().\r
   \r
+  Registers the PCI device specified by Address so all the PCI configuration registers \r
+  associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r
+  \r
   If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
@@ -181,7 +184,7 @@ PciRegisterForRuntimeAccess (
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
 \r
-  @return The value read from the PCI configuration register.\r
+  @return The read value from the PCI configuration register.\r
 \r
 **/\r
 UINT8\r
@@ -206,7 +209,7 @@ PciRead8 (
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
-  @param  Data    The value to write.\r
+  @param  Value   The value to write.\r
 \r
   @return The value written to the PCI configuration register.\r
 \r
@@ -215,12 +218,12 @@ UINT8
 EFIAPI\r
 PciWrite8 (\r
   IN      UINTN                     Address,\r
-  IN      UINT8                     Data\r
+  IN      UINT8                     Value\r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
 \r
-  return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);\r
+  return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
 }\r
 \r
 /**\r
@@ -526,7 +529,7 @@ PciBitFieldAndThenOr8 (
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
 \r
-  @return The value read from the PCI configuration register.\r
+  @return The read value from the PCI configuration register.\r
 \r
 **/\r
 UINT16\r
@@ -552,7 +555,7 @@ PciRead16 (
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
-  @param  Data    The value to write.\r
+  @param  Value   The value to write.\r
 \r
   @return The value written to the PCI configuration register.\r
 \r
@@ -561,12 +564,12 @@ UINT16
 EFIAPI\r
 PciWrite16 (\r
   IN      UINTN                     Address,\r
-  IN      UINT16                    Data\r
+  IN      UINT16                    Value\r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
 \r
-  return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);\r
+  return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
 }\r
 \r
 /**\r
@@ -880,7 +883,7 @@ PciBitFieldAndThenOr16 (
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
 \r
-  @return The value read from the PCI configuration register.\r
+  @return The read value from the PCI configuration register.\r
 \r
 **/\r
 UINT32\r
@@ -906,7 +909,7 @@ PciRead32 (
 \r
   @param  Address Address that encodes the PCI Bus, Device, Function and\r
                   Register.\r
-  @param  Data    The value to write.\r
+  @param  Value   The value to write.\r
 \r
   @return The value written to the PCI configuration register.\r
 \r
@@ -915,12 +918,12 @@ UINT32
 EFIAPI\r
 PciWrite32 (\r
   IN      UINTN                     Address,\r
-  IN      UINT32                    Data\r
+  IN      UINT32                    Value\r
   )\r
 {\r
   ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
 \r
-  return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);\r
+  return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);\r
 }\r
 \r
 /**\r
@@ -1339,7 +1342,7 @@ PciReadBuffer (
   @param  Size          Size in bytes of the transfer.\r
   @param  Buffer        Pointer to a buffer containing the data to write.\r
 \r
-  @return Size\r
+  @return Size written to StartAddress.\r
 \r
 **/\r
 UINTN\r

diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
index bb8779d9e0493536370cd5d0be6f5622e0ad0813..beb8b64adfd11146c80a970d099073907395ba68 100644 (file)
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
@@ -271,21 +271,19 @@ PciSegmentRegisterForRuntimeAccess (
   Reads an 8-bit PCI configuration register.\r
 \r
   Reads and returns the 8-bit PCI configuration register specified by Address.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
-\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  \r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-\r
-  @return The value read from the PCI configuration register.\r
+  @return The 8-bit PCI configuration register specified by Address.\r
 \r
 **/\r
 UINT8\r
 EFIAPI\r
 PciSegmentRead8 (\r
-  IN      UINT64                    Address\r
+  IN UINT64                    Address\r
   )\r
 {\r
   ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
@@ -296,15 +294,13 @@ PciSegmentRead8 (
 /**\r
   Writes an 8-bit PCI configuration register.\r
 \r
-  Writes the 8-bit PCI configuration register specified by Address with the\r
-  value specified by Value. Value is returned. This function must guarantee\r
-  that all PCI read and write operations are serialized.\r
-\r
-  If any reserved bits in Address are set, then ASSERT().\r
+  Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
+  If Address > 0x0FFFFFFF, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  Data    The value to write.\r
+  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  Value       The value to write.\r
 \r
   @return The value written to the PCI configuration register.\r
 \r
@@ -312,103 +308,94 @@ PciSegmentRead8 (
 UINT8\r
 EFIAPI\r
 PciSegmentWrite8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT8                     Data\r
+  IN UINT64                    Address,\r
+  IN UINT8                     Value\r
   )\r
 {\r
   ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
 \r
-  return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);\r
+  return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
 }\r
 \r
 /**\r
-  Performs a bitwise OR of an 8-bit PCI configuration register with\r
-  an 8-bit value.\r
-\r
-  Reads the 8-bit PCI configuration register specified by Address, performs a\r
-  bitwise OR between the read result and the value specified by\r
-  OrData, and writes the result to the 8-bit PCI configuration register\r
-  specified by Address. The value written to the PCI configuration register is\r
-  returned. This function must guarantee that all PCI read and write operations\r
-  are serialized.\r
+  Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
 \r
+  Reads the 8-bit PCI configuration register specified by Address,\r
+  performs a bitwise OR between the read result and the value specified by OrData,\r
+  and writes the result to the 8-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  OrData  The value to OR with the PCI configuration register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT8\r
 EFIAPI\r
 PciSegmentOr8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT8                     OrData\r
+  IN UINT64                    Address,\r
+  IN UINT8                     OrData\r
   )\r
 {\r
   return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
 }\r
 \r
 /**\r
-  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
-  value.\r
-\r
-  Reads the 8-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 8-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
 \r
+  Reads the 8-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  and writes the result to the 8-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
   If any reserved bits in Address are set, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT8\r
 EFIAPI\r
 PciSegmentAnd8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT8                     AndData\r
+  IN UINT64                    Address,\r
+  IN UINT8                     AndData\r
   )\r
 {\r
   return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
 }\r
 \r
 /**\r
-  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
-  value, followed a  bitwise OR with another 8-bit value.\r
-\r
-  Reads the 8-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData,\r
-  performs a bitwise OR between the result of the AND operation and\r
-  the value specified by OrData, and writes the result to the 8-bit PCI\r
-  configuration register specified by Address. The value written to the PCI\r
-  configuration register is returned. This function must guarantee that all PCI\r
-  read and write operations are serialized.\r
-\r
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
+  followed a  bitwise OR with another 8-bit value.\r
+  \r
+  Reads the 8-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 8-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-  @param  OrData  The value to OR with the result of the AND operation.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData    The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT8\r
 EFIAPI\r
 PciSegmentAndThenOr8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN UINT64                    Address,\r
+  IN UINT8                     AndData,\r
+  IN UINT8                     OrData\r
   )\r
 {\r
   return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
@@ -438,9 +425,9 @@ PciSegmentAndThenOr8 (
 UINT8\r
 EFIAPI\r
 PciSegmentBitFieldRead8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit\r
   )\r
 {\r
   return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
@@ -472,10 +459,10 @@ PciSegmentBitFieldRead8 (
 UINT8\r
 EFIAPI\r
 PciSegmentBitFieldWrite8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     Value\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT8                     Value\r
   )\r
 {\r
   return PciSegmentWrite8 (\r
@@ -513,10 +500,10 @@ PciSegmentBitFieldWrite8 (
 UINT8\r
 EFIAPI\r
 PciSegmentBitFieldOr8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     OrData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT8                     OrData\r
   )\r
 {\r
   return PciSegmentWrite8 (\r
@@ -554,10 +541,10 @@ PciSegmentBitFieldOr8 (
 UINT8\r
 EFIAPI\r
 PciSegmentBitFieldAnd8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT8                     AndData\r
   )\r
 {\r
   return PciSegmentWrite8 (\r
@@ -598,11 +585,11 @@ PciSegmentBitFieldAnd8 (
 UINT8\r
 EFIAPI\r
 PciSegmentBitFieldAndThenOr8 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT8                     AndData,\r
-  IN      UINT8                     OrData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT8                     AndData,\r
+  IN UINT8                     OrData\r
   )\r
 {\r
   return PciSegmentWrite8 (\r
@@ -615,21 +602,20 @@ PciSegmentBitFieldAndThenOr8 (
   Reads a 16-bit PCI configuration register.\r
 \r
   Reads and returns the 16-bit PCI configuration register specified by Address.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
-\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  \r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-\r
-  @return The value read from the PCI configuration register.\r
+  @return The 16-bit PCI configuration register specified by Address.\r
 \r
 **/\r
 UINT16\r
 EFIAPI\r
 PciSegmentRead16 (\r
-  IN      UINT64                    Address\r
+  IN UINT64                    Address\r
   )\r
 {\r
   ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
@@ -640,29 +626,28 @@ PciSegmentRead16 (
 /**\r
   Writes a 16-bit PCI configuration register.\r
 \r
-  Writes the 16-bit PCI configuration register specified by Address with the\r
-  value specified by Value. Value is returned. This function must guarantee\r
-  that all PCI read and write operations are serialized.\r
-\r
+  Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  Data    The value to write.\r
+  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  Value       The value to write.\r
 \r
-  @return The value written to the PCI configuration register.\r
+  @return The parameter of Value.\r
 \r
 **/\r
 UINT16\r
 EFIAPI\r
 PciSegmentWrite16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT16                    Data\r
+  IN UINT64                    Address,\r
+  IN UINT16                    Value\r
   )\r
 {\r
   ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
 \r
-  return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);\r
+  return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
 }\r
 \r
 /**\r
@@ -677,6 +662,7 @@ PciSegmentWrite16 (
   are serialized.\r
 \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
   @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
                   Register.\r
@@ -688,71 +674,68 @@ PciSegmentWrite16 (
 UINT16\r
 EFIAPI\r
 PciSegmentOr16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT16                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINT16                    OrData\r
   )\r
 {\r
   return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
-  value.\r
-\r
-  Reads the 16-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 16-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
 \r
+  Reads the 16-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  and writes the result to the 16-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  \r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-\r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT16\r
 EFIAPI\r
 PciSegmentAnd16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT16                    AndData\r
+  IN UINT64                    Address,\r
+  IN UINT16                    AndData\r
   )\r
 {\r
   return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
-  value, followed a  bitwise OR with another 16-bit value.\r
-\r
-  Reads the 16-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData,\r
-  performs a bitwise OR between the result of the AND operation and\r
-  the value specified by OrData, and writes the result to the 16-bit PCI\r
-  configuration register specified by Address. The value written to the PCI\r
-  configuration register is returned. This function must guarantee that all PCI\r
-  read and write operations are serialized.\r
-\r
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
+  followed a  bitwise OR with another 16-bit value.\r
+  \r
+  Reads the 16-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 16-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-  @param  OrData  The value to OR with the result of the AND operation.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData    The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT16\r
 EFIAPI\r
 PciSegmentAndThenOr16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINT16                    AndData,\r
+  IN UINT16                    OrData\r
   )\r
 {\r
   return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
@@ -766,6 +749,7 @@ PciSegmentAndThenOr16 (
   returned.\r
 \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -782,9 +766,9 @@ PciSegmentAndThenOr16 (
 UINT16\r
 EFIAPI\r
 PciSegmentBitFieldRead16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit\r
   )\r
 {\r
   return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
@@ -799,6 +783,7 @@ PciSegmentBitFieldRead16 (
   16-bit register is returned.\r
 \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -816,10 +801,10 @@ PciSegmentBitFieldRead16 (
 UINT16\r
 EFIAPI\r
 PciSegmentBitFieldWrite16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    Value\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT16                    Value\r
   )\r
 {\r
   return PciSegmentWrite16 (\r
@@ -829,17 +814,12 @@ PciSegmentBitFieldWrite16 (
 }\r
 \r
 /**\r
-  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
-  writes the result back to the bit field in the 16-bit port.\r
-\r
-  Reads the 16-bit PCI configuration register specified by Address, performs a\r
-  bitwise OR between the read result and the value specified by\r
-  OrData, and writes the result to the 16-bit PCI configuration register\r
-  specified by Address. The value written to the PCI configuration register is\r
-  returned. This function must guarantee that all PCI read and write operations\r
-  are serialized. Extra left bits in OrData are stripped.\r
+  Reads the 16-bit PCI configuration register specified by Address,\r
+  performs a bitwise OR between the read result and the value specified by OrData,\r
+  and writes the result to the 16-bit PCI configuration register specified by Address. \r
 \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
   If StartBit is greater than 15, then ASSERT().\r
   If EndBit is greater than 15, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -857,10 +837,10 @@ PciSegmentBitFieldWrite16 (
 UINT16\r
 EFIAPI\r
 PciSegmentBitFieldOr16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT16                    OrData\r
   )\r
 {\r
   return PciSegmentWrite16 (\r
@@ -870,38 +850,39 @@ PciSegmentBitFieldOr16 (
 }\r
 \r
 /**\r
-  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
-  AND, and writes the result back to the bit field in the 16-bit register.\r
-\r
-  Reads the 16-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 16-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized. Extra left bits in AndData are stripped.\r
-\r
+  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r
+  and writes the result back to the bit field in the 16-bit port.\r
+\r
+  Reads the 16-bit PCI configuration register specified by Address,\r
+  performs a bitwise OR between the read result and the value specified by OrData,\r
+  and writes the result to the 16-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  Extra left bits in OrData are stripped.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
-  If StartBit is greater than 15, then ASSERT().\r
-  If EndBit is greater than 15, then ASSERT().\r
+  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+  If StartBit is greater than 7, then ASSERT().\r
+  If EndBit is greater than 7, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
 \r
-  @param  Address   PCI configuration register to write.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
-                    Range 0..15.\r
+                    The ordinal of the least significant bit in a byte is bit 0.\r
   @param  EndBit    The ordinal of the most significant bit in the bit field.\r
-                    Range 0..15.\r
-  @param  AndData   The value to AND with the PCI configuration register.\r
+                    The ordinal of the most significant bit in a byte is bit 7.\r
+  @param  AndData   The value to AND with the read value from the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT16\r
 EFIAPI\r
 PciSegmentBitFieldAnd16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT16                    AndData\r
   )\r
 {\r
   return PciSegmentWrite16 (\r
@@ -942,11 +923,11 @@ PciSegmentBitFieldAnd16 (
 UINT16\r
 EFIAPI\r
 PciSegmentBitFieldAndThenOr16 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT16                    AndData,\r
-  IN      UINT16                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT16                    AndData,\r
+  IN UINT16                    OrData\r
   )\r
 {\r
   return PciSegmentWrite16 (\r
@@ -959,21 +940,20 @@ PciSegmentBitFieldAndThenOr16 (
   Reads a 32-bit PCI configuration register.\r
 \r
   Reads and returns the 32-bit PCI configuration register specified by Address.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
-\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
 \r
-  @return The value read from the PCI configuration register.\r
+  @return The 32-bit PCI configuration register specified by Address.\r
 \r
 **/\r
 UINT32\r
 EFIAPI\r
 PciSegmentRead32 (\r
-  IN      UINT64                    Address\r
+  IN UINT64                    Address\r
   )\r
 {\r
   ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
@@ -984,119 +964,113 @@ PciSegmentRead32 (
 /**\r
   Writes a 32-bit PCI configuration register.\r
 \r
-  Writes the 32-bit PCI configuration register specified by Address with the\r
-  value specified by Value. Value is returned. This function must guarantee\r
-  that all PCI read and write operations are serialized.\r
-\r
+  Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  Data    The value to write.\r
+  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  Value       The value to write.\r
 \r
-  @return The value written to the PCI configuration register.\r
+  @return The parameter of Value.\r
 \r
 **/\r
 UINT32\r
 EFIAPI\r
 PciSegmentWrite32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT32                    Data\r
+  IN UINT64                    Address,\r
+  IN UINT32                    Value\r
   )\r
 {\r
   ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
 \r
-  return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);\r
+  return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);\r
 }\r
 \r
 /**\r
-  Performs a bitwise OR of a 32-bit PCI configuration register with\r
-  a 32-bit value.\r
-\r
-  Reads the 32-bit PCI configuration register specified by Address, performs a\r
-  bitwise OR between the read result and the value specified by\r
-  OrData, and writes the result to the 32-bit PCI configuration register\r
-  specified by Address. The value written to the PCI configuration register is\r
-  returned. This function must guarantee that all PCI read and write operations\r
-  are serialized.\r
+  Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
 \r
+  Reads the 32-bit PCI configuration register specified by Address,\r
+  performs a bitwise OR between the read result and the value specified by OrData,\r
+  and writes the result to the 32-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  OrData  The value to OR with the PCI configuration register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT32\r
 EFIAPI\r
 PciSegmentOr32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT32                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINT32                    OrData\r
   )\r
 {\r
   return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
-  value.\r
-\r
-  Reads the 32-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 32-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized.\r
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
 \r
+  Reads the 32-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  and writes the result to the 32-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT32\r
 EFIAPI\r
 PciSegmentAnd32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT32                    AndData\r
+  IN UINT64                    Address,\r
+  IN UINT32                    AndData\r
   )\r
 {\r
   return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
 }\r
 \r
 /**\r
-  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
-  value, followed a  bitwise OR with another 32-bit value.\r
-\r
-  Reads the 32-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData,\r
-  performs a bitwise OR between the result of the AND operation and\r
-  the value specified by OrData, and writes the result to the 32-bit PCI\r
-  configuration register specified by Address. The value written to the PCI\r
-  configuration register is returned. This function must guarantee that all PCI\r
-  read and write operations are serialized.\r
-\r
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
+  followed a  bitwise OR with another 32-bit value.\r
+  \r
+  Reads the 32-bit PCI configuration register specified by Address,\r
+  performs a bitwise AND between the read result and the value specified by AndData,\r
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+  and writes the result to the 32-bit PCI configuration register specified by Address.\r
+  The value written to the PCI configuration register is returned.\r
+  This function must guarantee that all PCI read and write operations are serialized.\r
+  \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
 \r
-  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
-                  Register.\r
-  @param  AndData The value to AND with the PCI configuration register.\r
-  @param  OrData  The value to OR with the result of the AND operation.\r
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  AndData   The value to AND with the PCI configuration register.\r
+  @param  OrData    The value to OR with the PCI configuration register.\r
 \r
-  @return The value written back to the PCI configuration register.\r
+  @return The value written to the PCI configuration register.\r
 \r
 **/\r
 UINT32\r
 EFIAPI\r
 PciSegmentAndThenOr32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINT32                    AndData,\r
+  IN UINT32                    OrData\r
   )\r
 {\r
   return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
@@ -1110,6 +1084,7 @@ PciSegmentAndThenOr32 (
   returned.\r
 \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -1126,9 +1101,9 @@ PciSegmentAndThenOr32 (
 UINT32\r
 EFIAPI\r
 PciSegmentBitFieldRead32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit\r
   )\r
 {\r
   return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
@@ -1143,6 +1118,7 @@ PciSegmentBitFieldRead32 (
   32-bit register is returned.\r
 \r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
@@ -1160,10 +1136,10 @@ PciSegmentBitFieldRead32 (
 UINT32\r
 EFIAPI\r
 PciSegmentBitFieldWrite32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    Value\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT32                    Value\r
   )\r
 {\r
   return PciSegmentWrite32 (\r
@@ -1201,10 +1177,10 @@ PciSegmentBitFieldWrite32 (
 UINT32\r
 EFIAPI\r
 PciSegmentBitFieldOr32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT32                    OrData\r
   )\r
 {\r
   return PciSegmentWrite32 (\r
@@ -1217,17 +1193,18 @@ PciSegmentBitFieldOr32 (
   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
   AND, and writes the result back to the bit field in the 32-bit register.\r
 \r
-  Reads the 32-bit PCI configuration register specified by Address, performs a\r
-  bitwise AND between the read result and the value specified by AndData, and\r
-  writes the result to the 32-bit PCI configuration register specified by\r
-  Address. The value written to the PCI configuration register is returned.\r
-  This function must guarantee that all PCI read and write operations are\r
-  serialized. Extra left bits in AndData are stripped.\r
-\r
+  \r
+  Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
+  AND between the read result and the value specified by AndData, and writes the result\r
+  to the 32-bit PCI configuration register specified by Address. The value written to\r
+  the PCI configuration register is returned.  This function must guarantee that all PCI\r
+  read and write operations are serialized.  Extra left bits in AndData are stripped.\r
   If any reserved bits in Address are set, then ASSERT().\r
+  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
   If StartBit is greater than 31, then ASSERT().\r
   If EndBit is greater than 31, then ASSERT().\r
   If EndBit is less than StartBit, then ASSERT().\r
+  \r
 \r
   @param  Address   PCI configuration register to write.\r
   @param  StartBit  The ordinal of the least significant bit in the bit field.\r
@@ -1242,10 +1219,10 @@ PciSegmentBitFieldOr32 (
 UINT32\r
 EFIAPI\r
 PciSegmentBitFieldAnd32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT32                    AndData\r
   )\r
 {\r
   return PciSegmentWrite32 (\r
@@ -1286,11 +1263,11 @@ PciSegmentBitFieldAnd32 (
 UINT32\r
 EFIAPI\r
 PciSegmentBitFieldAndThenOr32 (\r
-  IN      UINT64                    Address,\r
-  IN      UINTN                     StartBit,\r
-  IN      UINTN                     EndBit,\r
-  IN      UINT32                    AndData,\r
-  IN      UINT32                    OrData\r
+  IN UINT64                    Address,\r
+  IN UINTN                     StartBit,\r
+  IN UINTN                     EndBit,\r
+  IN UINT32                    AndData,\r
+  IN UINT32                    OrData\r
   )\r
 {\r
   return PciSegmentWrite32 (\r
@@ -1302,28 +1279,32 @@ PciSegmentBitFieldAndThenOr32 (
 /**\r
   Reads a range of PCI configuration registers into a caller supplied buffer.\r
 \r
-  Reads the range of PCI configuration registers specified by StartAddress\r
-  and Size into the buffer specified by Buffer.\r
-  This function only allows the PCI configuration registers from a single PCI function to be read.\r
-  Size is returned.\r
-  \r
-  If any reserved bits in StartAddress are set, then ASSERT().\r
+  Reads the range of PCI configuration registers specified by StartAddress and\r
+  Size into the buffer specified by Buffer. This function only allows the PCI\r
+  configuration registers from a single PCI function to be read. Size is\r
+  returned. When possible 32-bit PCI configuration read cycles are used to read\r
+  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+  and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+  end of the range.\r
+\r
+  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
-  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,\r
+                        Function and Register.\r
   @param  Size          Size in bytes of the transfer.\r
   @param  Buffer        Pointer to a buffer receiving the data read.\r
 \r
-  @return The parameter of Size.\r
+  @return Size\r
 \r
 **/\r
 UINTN\r
 EFIAPI\r
 PciSegmentReadBuffer (\r
-  IN      UINT64                    StartAddress,\r
-  IN      UINTN                     Size,\r
-  OUT     VOID                      *Buffer\r
+  IN  UINT64                   StartAddress,\r
+  IN  UINTN                    Size,\r
+  OUT VOID                     *Buffer\r
   )\r
 {\r
   UINTN                                ReturnValue;\r
@@ -1393,18 +1374,23 @@ PciSegmentReadBuffer (
 }\r
 \r
 /**\r
-  Copies the data in a caller supplied buffer to a specified range of PCI configuration space.\r
-\r
-  Writes the range of PCI configuration registers specified by StartAddress\r
-  and Size from the buffer specified by Buffer.\r
-  This function only allows the PCI configuration registers from a single PCI function to be written.\r
-  Size is returned.\r
-  \r
-  If any reserved bits in StartAddress are set, then ASSERT().\r
+  Copies the data in a caller supplied buffer to a specified range of PCI\r
+  configuration space.\r
+\r
+  Writes the range of PCI configuration registers specified by StartAddress and\r
+  Size from the buffer specified by Buffer. This function only allows the PCI\r
+  configuration registers from a single PCI function to be written. Size is\r
+  returned. When possible 32-bit PCI configuration write cycles are used to\r
+  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+  8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+  and the end of the range.\r
+\r
+  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
   If Size > 0 and Buffer is NULL, then ASSERT().\r
 \r
-  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,\r
+                        Function and Register.\r
   @param  Size          Size in bytes of the transfer.\r
   @param  Buffer        Pointer to a buffer containing the data to write.\r
 \r
@@ -1414,9 +1400,9 @@ PciSegmentReadBuffer (
 UINTN\r
 EFIAPI\r
 PciSegmentWriteBuffer (\r
-  IN      UINT64                    StartAddress,\r
-  IN      UINTN                     Size,\r
-  IN      VOID                      *Buffer\r
+  IN UINT64                    StartAddress,\r
+  IN UINTN                     Size,\r
+  IN VOID                      *Buffer\r
   )\r
 {\r
   UINTN                                ReturnValue;\r

diff --git a/MdePkg/Library/UefiRuntimeLib/RuntimeService.c b/MdePkg/Library/UefiRuntimeLib/RuntimeService.c
index 982e20c7986042b8d414c422ec62fbe2040e8700..67b0237604371800764593d106bd5d2a4dcb2e8d 100644 (file)
--- a/MdePkg/Library/UefiRuntimeLib/RuntimeService.c
+++ b/MdePkg/Library/UefiRuntimeLib/RuntimeService.c
@@ -87,7 +87,7 @@ EFI_STATUS
 EFIAPI\r
 EfiGetTime (\r
   OUT EFI_TIME                    *Time,\r
-  OUT EFI_TIME_CAPABILITIES       *Capabilities   OPTIONAL\r
+  OUT EFI_TIME_CAPABILITIES       *Capabilities  OPTIONAL\r
   )\r
 {\r
   return mRT->GetTime (Time, Capabilities);\r
@@ -186,7 +186,7 @@ EFI_STATUS
 EFIAPI\r
 EfiSetWakeupTime (\r
   IN BOOLEAN                      Enable,\r
-  IN EFI_TIME                     *Time  OPTIONAL\r
+  IN EFI_TIME                     *Time   OPTIONAL\r
   )\r
 {\r
   return mRT->SetWakeupTime (Enable, Time);\r
@@ -226,11 +226,11 @@ EfiSetWakeupTime (
 EFI_STATUS\r
 EFIAPI\r
 EfiGetVariable (\r
-  IN CHAR16                       *VariableName,\r
-  IN EFI_GUID                     * VendorGuid,\r
-  OUT UINT32                      *Attributes OPTIONAL,\r
-  IN OUT UINTN                    *DataSize,\r
-  OUT VOID                        *Data\r
+  IN      CHAR16                   *VariableName,\r
+  IN      EFI_GUID                 *VendorGuid,\r
+  OUT     UINT32                   *Attributes OPTIONAL,\r
+  IN OUT  UINTN                    *DataSize,\r
+  OUT     VOID                     *Data\r
   )\r
 {\r
   return mRT->GetVariable (VariableName, VendorGuid, Attributes, DataSize, Data);\r
@@ -545,9 +545,9 @@ EfiSetVirtualAddressMap (
 EFI_STATUS\r
 EFIAPI\r
 EfiUpdateCapsule (\r
-  IN EFI_CAPSULE_HEADER   **CapsuleHeaderArray,\r
-  IN UINTN                CapsuleCount,\r
-  IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL\r
+  IN EFI_CAPSULE_HEADER       **CapsuleHeaderArray,\r
+  IN UINTN                    CapsuleCount,\r
+  IN EFI_PHYSICAL_ADDRESS     ScatterGatherList OPTIONAL\r
   )\r
 {\r
   return mRT->UpdateCapsule (\r
@@ -595,10 +595,10 @@ EfiUpdateCapsule (
 EFI_STATUS\r
 EFIAPI\r
 EfiQueryCapsuleCapabilities (\r
-  IN EFI_CAPSULE_HEADER   **CapsuleHeaderArray,\r
-  IN UINTN                CapsuleCount,\r
-  OUT UINT64              *MaximumCapsuleSize,\r
-  OUT EFI_RESET_TYPE      *ResetType\r
+  IN  EFI_CAPSULE_HEADER       **CapsuleHeaderArray,\r
+  IN  UINTN                    CapsuleCount,\r
+  OUT UINT64                   *MaximumCapsuleSize,\r
+  OUT EFI_RESET_TYPE           *ResetType\r
   )\r
 {\r
   return mRT->QueryCapsuleCapabilities (\r
@@ -647,10 +647,10 @@ EfiQueryCapsuleCapabilities (
 EFI_STATUS\r
 EFIAPI\r
 EfiQueryVariableInfo (\r
-  IN  UINT32      Attributes,\r
-  OUT UINT64      *MaximumVariableStorageSize,\r
-  OUT UINT64      *RemainingVariableStorageSize,\r
-  OUT UINT64      *MaximumVariableSize\r
+  IN UINT32   Attributes,\r
+  OUT UINT64  *MaximumVariableStorageSize,\r
+  OUT UINT64  *RemainingVariableStorageSize,\r
+  OUT UINT64  *MaximumVariableSize\r
   )\r
 {\r
   return mRT->QueryVariableInfo (\r

diff --git a/MdePkg/Library/UefiScsiLib/UefiScsiLib.c b/MdePkg/Library/UefiScsiLib/UefiScsiLib.c
index 5f125ab29f6352b256e5afd9ecab605ac171c342..e26905e1e33e9dbc61bf2ebae9dcf7b300a342b3 100644 (file)
--- a/MdePkg/Library/UefiScsiLib/UefiScsiLib.c
+++ b/MdePkg/Library/UefiScsiLib/UefiScsiLib.c
@@ -192,7 +192,7 @@ ScsiTestUnitReadyCommand (
                                          SCSI I/O Protocol in the UEFI Specification\r
                                          for details on the possible return values.\r
   @param[out]     TargetStatus           The status returned by the SCSI target specified\r
-                                         by ScsiIo when the SCSI Request Packat was\r
+                                         by ScsiIo when the SCSI Request Packet was\r
                                          executed on the SCSI Host Controller.\r
                                          See the EFI SCSI I/O Protocol in the UEFI\r
                                          Specification for details on the possible\r
@@ -338,7 +338,7 @@ ScsiInquiryCommand (
                                      UEFI Specification for details on the possible\r
                                      return values.\r
   @param[out]     TargetStatus       The status returned by the SCSI target specified\r
-                                     by ScsiIo when the SCSI Request Packat was executed\r
+                                     by ScsiIo when the SCSI Request Packet was executed\r
                                      on the SCSI Host Controller.  See the EFI SCSI\r
                                      I/O Protocol in the UEFI Specification for details\r
                                      on the possible return values.\r

diff --git a/MdePkg/Library/UefiUsbLib/Hid.c b/MdePkg/Library/UefiUsbLib/Hid.c
index d2a4b577ffd12e8f2919d1382e11d08131995167..4858ed6f7d189227ff53cadcc5e59efcb6c6a4b5 100644 (file)
--- a/MdePkg/Library/UefiUsbLib/Hid.c
+++ b/MdePkg/Library/UefiUsbLib/Hid.c
@@ -98,7 +98,7 @@ UsbGetHidDescriptor (
 \r
   @retval  EFI_SUCCESS           The request executed successfully.\r
   @retval  EFI_OUT_OF_RESOURCES  The request could not be completed because the\r
-                                 buffer specifed by DescriptorLength and DescriptorBuffer\r
+                                 buffer specified by DescriptorLength and DescriptorBuffer\r
                                  is not large enough to hold the result of the request.\r
   @retval  EFI_TIMEOUT           A timeout occurred executing the request.\r
   @retval  EFI_DEVICE_ERROR      The request failed due to a device error.\r
@@ -389,7 +389,7 @@ UsbSetReportRequest (
   IN UINT8                   Interface,\r
   IN UINT8                   ReportId,\r
   IN UINT8                   ReportType,\r
-  IN UINT16                  ReportLength,\r
+  IN UINT16                  ReportLen,\r
   IN UINT8                   *Report\r
   )\r
 {\r
@@ -415,7 +415,7 @@ UsbSetReportRequest (
                     EfiUsbDataOut,\r
                     TIMEOUT_VALUE,\r
                     Report,\r
-                    ReportLength,\r
+                    ReportLen,\r
                     &Status\r
                     );\r
 \r

diff --git a/MdePkg/Library/UefiUsbLib/UsbDxeLib.c b/MdePkg/Library/UefiUsbLib/UsbDxeLib.c
index 35b1880ce5a36216706d15ba7f1bdf7fb399306b..466ffeffa7a8bffd41a805397975a1f7f3d97939 100644 (file)
--- a/MdePkg/Library/UefiUsbLib/UsbDxeLib.c
+++ b/MdePkg/Library/UefiUsbLib/UsbDxeLib.c
@@ -590,7 +590,7 @@ UsbGetStatus (
 \r
   Retrieve the USB endpoint descriptor specified by UsbIo and EndPoint.\r
   If the USB endpoint descriptor can not be retrieved, then return EFI_NOT_FOUND.\r
-  If the endpoint descriptor is found, then clear the halt fature of this USB endpoint.\r
+  If the endpoint descriptor is found, then clear the halt feature of this USB endpoint.\r
   The status of the transfer is returned in Status.\r
   If UsbIo is NULL, then ASSERT().\r
   If Status is NULL, then ASSERT().\r