)\r
{\r
\r
- EFI_STATUS Status;\r
- PCI_IO_DEVICE *PciIoDevice;\r
UINT64 BaseAddress = 0;\r
UINT64 TempBaseAddress = 0;\r
UINT8 RevId = 0;\r
UINT64 MemSize;\r
UINTN MemSizeBits;\r
\r
-\r
- PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
switch ( VendorId) {\r
case ATI_VENDOR_ID:\r
//\r
//\r
// Get original BAR address\r
//\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &BaseAddress\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &BaseAddress\r
+ );\r
//\r
// Find BAR size\r
//\r
TempBaseAddress = 0xffffffff;\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &TempBaseAddress\r
- );\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &TempBaseAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &TempBaseAddress\r
+ );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &TempBaseAddress\r
+ );\r
TempBaseAddress &= 0xfffffffe;\r
MemSize = 1;\r
while ((TempBaseAddress & 0x01) == 0) {\r
//\r
// Free up allocated memory memory and re-allocate with increased size.\r
//\r
- Status = gDS->FreeMemorySpace (\r
- BaseAddress,\r
- MemSize\r
- );\r
+ gDS->FreeMemorySpace (\r
+ BaseAddress,\r
+ MemSize\r
+ );\r
//\r
// Force new alignment\r
//\r
MemSize = 0x8000000;\r
MemSizeBits = 28;\r
\r
- Status = gDS->AllocateMemorySpace (\r
- EfiGcdAllocateAnySearchBottomUp,\r
- EfiGcdMemoryTypeMemoryMappedIo,\r
- MemSizeBits, // Alignment\r
- MemSize,\r
- &BaseAddress,\r
- mImageHandle,\r
- NULL\r
- );\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &BaseAddress\r
- );\r
+ gDS->AllocateMemorySpace (\r
+ EfiGcdAllocateAnySearchBottomUp,\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ MemSizeBits, // Alignment\r
+ MemSize,\r
+ &BaseAddress,\r
+ mImageHandle,\r
+ NULL\r
+ );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &BaseAddress\r
+ );\r
\r
break;\r
case NCR_VENDOR_ID:\r
//\r
for (Bar = 0x10; Bar < 0x28; Bar+= 4) {\r
\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &BaseAddress\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &BaseAddress\r
+ );\r
if (BaseAddress && 0x01) {\r
TempBaseAddress = 0xffffffff;\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &TempBaseAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &TempBaseAddress\r
+ );\r
TempBaseAddress &= 0xfffffffc;\r
IoSize = 1;\r
while ((TempBaseAddress & 0x01) == 0) {\r
IoSize = IoSize << 1;\r
}\r
if (IoSize < MIN_NCR_IO_SIZE) {\r
- Status = gDS->FreeIoSpace (\r
- BaseAddress,\r
- IoSize\r
- );\r
-\r
- Status = gDS->AllocateIoSpace (\r
- EfiGcdAllocateAnySearchTopDown,\r
- EfiGcdIoTypeIo,\r
- NCR_GRAN, // Alignment\r
- MIN_NCR_IO_SIZE,\r
- &BaseAddress,\r
- mImageHandle,\r
- NULL\r
- );\r
+ gDS->FreeIoSpace (\r
+ BaseAddress,\r
+ IoSize\r
+ );\r
+\r
+ gDS->AllocateIoSpace (\r
+ EfiGcdAllocateAnySearchTopDown,\r
+ EfiGcdIoTypeIo,\r
+ NCR_GRAN, // Alignment\r
+ MIN_NCR_IO_SIZE,\r
+ &BaseAddress,\r
+ mImageHandle,\r
+ NULL\r
+ );\r
TempBaseAddress = BaseAddress + 1;\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &TempBaseAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &TempBaseAddress\r
+ );\r
}\r
}\r
}\r
// Controller.\r
// All Tekoa A2 or earlier step chips for now.\r
//\r
- Status = PciIo->Pci.Read (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_REVISION_ID_OFFSET,\r
- 1,\r
- &RevId\r
- );\r
+ PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PCI_REVISION_ID_OFFSET,\r
+ 1,\r
+ &RevId\r
+ );\r
if (RevId <= 0x02) {\r
for (Bar = 0x14; Bar < 0x24; Bar+= 4) {\r
//\r
// Bars don't worry aboyut freeing up thge allocs.\r
//\r
TempBaseAddress = 0x0;\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- Bar,\r
- 1,\r
- (VOID *) &TempBaseAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ Bar,\r
+ 1,\r
+ (VOID *) &TempBaseAddress\r
+ );\r
} // end for\r
}\r
else\r
//since Tekoa does not fully support IDE Bus Mastering\r
//\r
TempBaseAddress = 0x0;\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint32,\r
- 0x20,\r
- 1,\r
- (VOID *) &TempBaseAddress\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0x20,\r
+ 1,\r
+ (VOID *) &TempBaseAddress\r
+ );\r
}\r
}\r
break;\r
IN EFI_PCI_IO_PROTOCOL *PciIo\r
)\r
{\r
- EFI_STATUS Status;\r
-\r
//\r
// Program Master Latency Timer\r
//\r
if (mSystemConfiguration.PciLatency != 0) {\r
- Status = PciIo->Pci.Write (\r
- PciIo,\r
- EfiPciIoWidthUint8,\r
- PCI_LATENCY_TIMER_OFFSET,\r
- 1,\r
- &mSystemConfiguration.PciLatency\r
- );\r
+ PciIo->Pci.Write (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ PCI_LATENCY_TIMER_OFFSET,\r
+ 1,\r
+ &mSystemConfiguration.PciLatency\r
+ );\r
}\r
return;\r
}\r
)\r
{\r
UINTN VarSize;\r
- EFI_STATUS Status;\r
\r
VarSize = sizeof(SYSTEM_CONFIGURATION);\r
- Status = gRT->GetVariable(\r
- NORMAL_SETUP_NAME,\r
- &gEfiNormalSetupGuid,\r
- NULL,\r
- &VarSize,\r
- &mSystemConfiguration\r
- );\r
+ gRT->GetVariable(\r
+ NORMAL_SETUP_NAME,\r
+ &gEfiNormalSetupGuid,\r
+ NULL,\r
+ &VarSize,\r
+ &mSystemConfiguration\r
+ );\r
\r
//\r
//Program HDA PME_EN\r
)\r
{\r
UINTN VarSize;\r
- EFI_STATUS Status;\r
EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;\r
VarSize = sizeof(SYSTEM_CONFIGURATION);\r
- Status = gRT->GetVariable(\r
- NORMAL_SETUP_NAME,\r
- &gEfiNormalSetupGuid,\r
- NULL,\r
- &VarSize,\r
- &mSystemConfiguration\r
- );\r
- Status = gBS->LocateProtocol (\r
- &gEfiGlobalNvsAreaProtocolGuid,\r
- NULL,\r
- (void **)&GlobalNvsArea\r
- );\r
+ gRT->GetVariable(\r
+ NORMAL_SETUP_NAME,\r
+ &gEfiNormalSetupGuid,\r
+ NULL,\r
+ &VarSize,\r
+ &mSystemConfiguration\r
+ );\r
+ gBS->LocateProtocol (\r
+ &gEfiGlobalNvsAreaProtocolGuid,\r
+ NULL,\r
+ (void **)&GlobalNvsArea\r
+ );\r
GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;\r
GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;\r
}\r